decoder.isa (3975:10fa2125f19e) | decoder.isa (3980:9bcb2a2e9bb8) |
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1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 178 unchanged lines hidden (view full) --- 187 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}}); 188 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 189 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}}); 190 0x0A: umul({{ 191 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 192 Y = Rd<63:32>; 193 }}); 194 0x0B: smul({{ | 1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 178 unchanged lines hidden (view full) --- 187 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}}); 188 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 189 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}}); 190 0x0A: umul({{ 191 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 192 Y = Rd<63:32>; 193 }}); 194 0x0B: smul({{ |
195 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>; | 195 Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); |
196 Y = Rd.sdw<63:32>; 197 }}); 198 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 199 0x0D: udivx({{ 200 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 201 else Rd.udw = Rs1.udw / Rs2_or_imm13; 202 }}); 203 0x0E: udiv({{ --- 6 unchanged lines hidden (view full) --- 210 } 211 }}); 212 0x0F: sdiv({{ 213 if(Rs2_or_imm13.sdw == 0) 214 fault = new DivisionByZero; 215 else 216 { 217 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; | 196 Y = Rd.sdw<63:32>; 197 }}); 198 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 199 0x0D: udivx({{ 200 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 201 else Rd.udw = Rs1.udw / Rs2_or_imm13; 202 }}); 203 0x0E: udiv({{ --- 6 unchanged lines hidden (view full) --- 210 } 211 }}); 212 0x0F: sdiv({{ 213 if(Rs2_or_imm13.sdw == 0) 214 fault = new DivisionByZero; 215 else 216 { 217 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; |
218 if(Rd.udw<63:31> != 0) | 218 if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max()) |
219 Rd.udw = 0x7FFFFFFF; | 219 Rd.udw = 0x7FFFFFFF; |
220 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF) 221 Rd.udw = 0xFFFFFFFF80000000ULL; | 220 else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min()) 221 Rd.udw = ULL(0xFFFFFFFF80000000); |
222 } 223 }}); 224 } 225 format IntOpCc { 226 0x10: addcc({{ 227 int64_t resTemp, val2 = Rs2_or_imm13; 228 Rd = resTemp = Rs1 + val2;}}, 229 {{(Rs1<31:0> + val2<31:0>)<32:>}}, --- 17 unchanged lines hidden (view full) --- 247 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 248 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 249 0x18: addccc({{ 250 int64_t resTemp, val2 = Rs2_or_imm13; 251 int64_t carryin = Ccr<0:0>; 252 Rd = resTemp = Rs1 + val2 + carryin;}}, 253 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}}, 254 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, | 222 } 223 }}); 224 } 225 format IntOpCc { 226 0x10: addcc({{ 227 int64_t resTemp, val2 = Rs2_or_imm13; 228 Rd = resTemp = Rs1 + val2;}}, 229 {{(Rs1<31:0> + val2<31:0>)<32:>}}, --- 17 unchanged lines hidden (view full) --- 247 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 248 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 249 0x18: addccc({{ 250 int64_t resTemp, val2 = Rs2_or_imm13; 251 int64_t carryin = Ccr<0:0>; 252 Rd = resTemp = Rs1 + val2 + carryin;}}, 253 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}}, 254 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, |
255 {{(Rs1<63:1> + val2<63:1> + 256 ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}}, | 255 {{((Rs1 & val2) | (~resTemp & (Rs1 | val2)))<63:>}}, |
257 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 258 ); 259 0x1A: IntOpCcRes::umulcc({{ 260 uint64_t resTemp; 261 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 262 Y = resTemp<63:32>;}}); 263 0x1B: IntOpCcRes::smulcc({{ 264 int64_t resTemp; | 256 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 257 ); 258 0x1A: IntOpCcRes::umulcc({{ 259 uint64_t resTemp; 260 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 261 Y = resTemp<63:32>;}}); 262 0x1B: IntOpCcRes::smulcc({{ 263 int64_t resTemp; |
265 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>; | 264 Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); |
266 Y = resTemp<63:32>;}}); 267 0x1C: subccc({{ 268 int64_t resTemp, val2 = Rs2_or_imm13; 269 int64_t carryin = Ccr<0:0>; 270 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}}, | 265 Y = resTemp<63:32>;}}); 266 0x1C: subccc({{ 267 int64_t resTemp, val2 = Rs2_or_imm13; 268 int64_t carryin = Ccr<0:0>; 269 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}}, |
271 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}}, | 270 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<31:>}}, |
272 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, | 271 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, |
273 {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}}, | 272 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<63:>}}, |
274 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 275 ); 276 0x1D: IntOpCcRes::udivxcc({{ 277 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; 278 else Rd = Rs1.udw / Rs2_or_imm13.udw;}}); 279 0x1E: udivcc({{ 280 uint32_t resTemp, val2 = Rs2_or_imm13.udw; 281 int32_t overflow = 0; --- 12 unchanged lines hidden (view full) --- 294 ); 295 0x1F: sdivcc({{ 296 int64_t val2 = Rs2_or_imm13.sdw<31:0>; 297 bool overflow = false, underflow = false; 298 if(val2 == 0) fault = new DivisionByZero; 299 else 300 { 301 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; | 273 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 274 ); 275 0x1D: IntOpCcRes::udivxcc({{ 276 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; 277 else Rd = Rs1.udw / Rs2_or_imm13.udw;}}); 278 0x1E: udivcc({{ 279 uint32_t resTemp, val2 = Rs2_or_imm13.udw; 280 int32_t overflow = 0; --- 12 unchanged lines hidden (view full) --- 293 ); 294 0x1F: sdivcc({{ 295 int64_t val2 = Rs2_or_imm13.sdw<31:0>; 296 bool overflow = false, underflow = false; 297 if(val2 == 0) fault = new DivisionByZero; 298 else 299 { 300 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; |
302 overflow = (Rd<63:31> != 0); 303 underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF); | 301 overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max()); 302 underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min()); |
304 if(overflow) Rd = 0x7FFFFFFF; | 303 if(overflow) Rd = 0x7FFFFFFF; |
305 else if(underflow) Rd = 0xFFFFFFFF80000000ULL; | 304 else if(underflow) Rd = ULL(0xFFFFFFFF80000000); |
306 } }}, 307 {{0}}, 308 {{overflow || underflow}}, 309 {{0}}, 310 {{0}} 311 ); 312 0x20: taddcc({{ 313 int64_t resTemp, val2 = Rs2_or_imm13; --- 60 unchanged lines hidden (view full) --- 374 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 375 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 376 } 377 0x27: decode X { 378 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 379 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 380 } 381 0x28: decode RS1 { | 305 } }}, 306 {{0}}, 307 {{overflow || underflow}}, 308 {{0}}, 309 {{0}} 310 ); 311 0x20: taddcc({{ 312 int64_t resTemp, val2 = Rs2_or_imm13; --- 60 unchanged lines hidden (view full) --- 373 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 374 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 375 } 376 0x27: decode X { 377 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 378 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 379 } 380 0x28: decode RS1 { |
382 0x00: NoPriv::rdy({{Rd = Y;}}); | 381 0x00: NoPriv::rdy({{Rd = Y<31:0>;}}); |
383 //1 should cause an illegal instruction exception 384 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 385 0x03: NoPriv::rdasi({{Rd = Asi;}}); 386 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); 387 0x05: NoPriv::rdpc({{ 388 if(Pstate<3:>) 389 Rd = (xc->readPC())<31:0>; 390 else --- 133 unchanged lines hidden (view full) --- 524 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 525 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 526 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 527 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 528 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 529 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 530 } 531 0x30: decode RD { | 382 //1 should cause an illegal instruction exception 383 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 384 0x03: NoPriv::rdasi({{Rd = Asi;}}); 385 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); 386 0x05: NoPriv::rdpc({{ 387 if(Pstate<3:>) 388 Rd = (xc->readPC())<31:0>; 389 else --- 133 unchanged lines hidden (view full) --- 523 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 524 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 525 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 526 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 527 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 528 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 529 } 530 0x30: decode RD { |
532 0x00: NoPriv::wry({{Y = Rs1 ^ Rs2_or_imm13;}}); | 531 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}}); |
533 //0x01 should cause an illegal instruction exception 534 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 535 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); 536 //0x04-0x05 should cause an illegal instruction exception 537 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}}); 538 //0x07-0x0E should cause an illegal instruction exception 539 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}}); 540 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}}); --- 121 unchanged lines hidden (view full) --- 662 Fsr &= ~(0x1F); 663 }}); 664 0x02: fmovd({{ 665 Frd.udw = Frs2.udw; 666 //fsr.ftt = fsr.cexc = 0 667 Fsr &= ~(7 << 14); 668 Fsr &= ~(0x1F); 669 }}); | 532 //0x01 should cause an illegal instruction exception 533 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 534 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); 535 //0x04-0x05 should cause an illegal instruction exception 536 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}}); 537 //0x07-0x0E should cause an illegal instruction exception 538 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}}); 539 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}}); --- 121 unchanged lines hidden (view full) --- 661 Fsr &= ~(0x1F); 662 }}); 663 0x02: fmovd({{ 664 Frd.udw = Frs2.udw; 665 //fsr.ftt = fsr.cexc = 0 666 Fsr &= ~(7 << 14); 667 Fsr &= ~(0x1F); 668 }}); |
670 0x03: Trap::fmovq({{fault = new FpDisabled;}}); | 669 0x03: Trap::fmovq({{fault = new FpExceptionOther;}}); |
671 0x05: fnegs({{ 672 Frds.uw = Frs2s.uw ^ (1UL << 31); 673 //fsr.ftt = fsr.cexc = 0 674 Fsr &= ~(7 << 14); 675 Fsr &= ~(0x1F); 676 }}); 677 0x06: fnegd({{ 678 Frd.udw = Frs2.udw ^ (1ULL << 63); --- 10 unchanged lines hidden (view full) --- 689 }}); 690 0x0A: fabsd({{ 691 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw; 692 //fsr.ftt = fsr.cexc = 0 693 Fsr &= ~(7 << 14); 694 Fsr &= ~(0x1F); 695 }}); 696 0x0B: Trap::fabsq({{fault = new FpDisabled;}}); | 670 0x05: fnegs({{ 671 Frds.uw = Frs2s.uw ^ (1UL << 31); 672 //fsr.ftt = fsr.cexc = 0 673 Fsr &= ~(7 << 14); 674 Fsr &= ~(0x1F); 675 }}); 676 0x06: fnegd({{ 677 Frd.udw = Frs2.udw ^ (1ULL << 63); --- 10 unchanged lines hidden (view full) --- 688 }}); 689 0x0A: fabsd({{ 690 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw; 691 //fsr.ftt = fsr.cexc = 0 692 Fsr &= ~(7 << 14); 693 Fsr &= ~(0x1F); 694 }}); 695 0x0B: Trap::fabsq({{fault = new FpDisabled;}}); |
697 0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}}); 698 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}}); | 696 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}}); 697 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}}); |
699 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}}); 700 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}}); 701 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); 702 0x43: Trap::faddq({{fault = new FpDisabled;}}); 703 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}}); 704 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}}); 705 0x47: Trap::fsubq({{fault = new FpDisabled;}}); 706 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}}); --- 151 unchanged lines hidden (view full) --- 858 0x6D: Trap::fxors({{fault = new IllegalInstruction;}}); 859 0x6E: Trap::fnand({{fault = new IllegalInstruction;}}); 860 0x6F: Trap::fnands({{fault = new IllegalInstruction;}}); 861 0x70: Trap::fand({{fault = new IllegalInstruction;}}); 862 0x71: Trap::fands({{fault = new IllegalInstruction;}}); 863 0x72: Trap::fxnor({{fault = new IllegalInstruction;}}); 864 0x73: Trap::fxnors({{fault = new IllegalInstruction;}}); 865 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}}); | 698 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}}); 699 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}}); 700 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); 701 0x43: Trap::faddq({{fault = new FpDisabled;}}); 702 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}}); 703 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}}); 704 0x47: Trap::fsubq({{fault = new FpDisabled;}}); 705 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}}); --- 151 unchanged lines hidden (view full) --- 857 0x6D: Trap::fxors({{fault = new IllegalInstruction;}}); 858 0x6E: Trap::fnand({{fault = new IllegalInstruction;}}); 859 0x6F: Trap::fnands({{fault = new IllegalInstruction;}}); 860 0x70: Trap::fand({{fault = new IllegalInstruction;}}); 861 0x71: Trap::fands({{fault = new IllegalInstruction;}}); 862 0x72: Trap::fxnor({{fault = new IllegalInstruction;}}); 863 0x73: Trap::fxnors({{fault = new IllegalInstruction;}}); 864 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}}); |
866 0x75: BasicOperate::fsrc1s({{Frd.uw = Frs1.uw;}}); | 865 0x75: BasicOperate::fsrc1s({{Frds.uw = Frs1s.uw;}}); |
867 0x76: Trap::fornot2({{fault = new IllegalInstruction;}}); 868 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}}); 869 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}}); | 866 0x76: Trap::fornot2({{fault = new IllegalInstruction;}}); 867 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}}); 868 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}}); |
870 0x79: BasicOperate::fsrc2s({{Frd.uw = Frs2.uw;}}); | 869 0x79: BasicOperate::fsrc2s({{Frds.uw = Frs2s.uw;}}); |
871 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}}); 872 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}}); 873 0x7C: Trap::for({{fault = new IllegalInstruction;}}); 874 0x7D: Trap::fors({{fault = new IllegalInstruction;}}); 875 0x7E: Trap::fone({{fault = new IllegalInstruction;}}); 876 0x7F: Trap::fones({{fault = new IllegalInstruction;}}); 877 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 878 0x81: Trap::siam({{fault = new IllegalInstruction;}}); 879 } 880 0x37: Trap::impdep2({{fault = new IllegalInstruction;}}); 881 0x38: Branch::jmpl({{ 882 Addr target = Rs1 + Rs2_or_imm13; 883 if(target & 0x3) 884 fault = new MemAddressNotAligned; 885 else 886 { 887 if (Pstate<3:>) | 870 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}}); 871 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}}); 872 0x7C: Trap::for({{fault = new IllegalInstruction;}}); 873 0x7D: Trap::fors({{fault = new IllegalInstruction;}}); 874 0x7E: Trap::fone({{fault = new IllegalInstruction;}}); 875 0x7F: Trap::fones({{fault = new IllegalInstruction;}}); 876 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 877 0x81: Trap::siam({{fault = new IllegalInstruction;}}); 878 } 879 0x37: Trap::impdep2({{fault = new IllegalInstruction;}}); 880 0x38: Branch::jmpl({{ 881 Addr target = Rs1 + Rs2_or_imm13; 882 if(target & 0x3) 883 fault = new MemAddressNotAligned; 884 else 885 { 886 if (Pstate<3:>) |
888 (Rd = xc->readPC())<31:0>; | 887 Rd = (xc->readPC())<31:0>; |
889 else 890 Rd = xc->readPC(); 891 NNPC = target; 892 } 893 }}); 894 0x39: Branch::return({{ 895 Addr target = Rs1 + Rs2_or_imm13; 896 if(fault == NoFault) --- 135 unchanged lines hidden (view full) --- 1032 } 1033 format Load { 1034 0x08: ldsw({{Rd = (int32_t)Mem.sw;}}); 1035 0x09: ldsb({{Rd = (int8_t)Mem.sb;}}); 1036 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}}); 1037 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}}); 1038 } 1039 0x0D: LoadStore::ldstub( | 888 else 889 Rd = xc->readPC(); 890 NNPC = target; 891 } 892 }}); 893 0x39: Branch::return({{ 894 Addr target = Rs1 + Rs2_or_imm13; 895 if(fault == NoFault) --- 135 unchanged lines hidden (view full) --- 1031 } 1032 format Load { 1033 0x08: ldsw({{Rd = (int32_t)Mem.sw;}}); 1034 0x09: ldsb({{Rd = (int8_t)Mem.sb;}}); 1035 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}}); 1036 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}}); 1037 } 1038 0x0D: LoadStore::ldstub( |
1040 {{Rd = Mem.ub;}}, 1041 {{Mem.ub = 0xFF;}}); | 1039 {{uReg0 = Mem.ub;}}, 1040 {{Rd.ub = uReg0; 1041 Mem.ub = 0xFF;}}); |
1042 0x0E: Store::stx({{Mem.udw = Rd}}); 1043 0x0F: LoadStore::swap( | 1042 0x0E: Store::stx({{Mem.udw = Rd}}); 1043 0x0F: LoadStore::swap( |
1044 {{uReg0 = Rd.uw; 1045 Rd.uw = Mem.uw;}}, 1046 {{Mem.uw = uReg0;}}); | 1044 {{ uReg0 = Mem.uw}}, 1045 {{ Mem.uw = Rd.uw; 1046 Rd.uw = uReg0;}}); |
1047 format LoadAlt { 1048 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}}); 1049 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}}); 1050 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}}); 1051 0x13: decode EXT_ASI { 1052 //ASI_LDTD_AIUP 1053 0x22: TwinLoad::ldtx_aiup( | 1047 format LoadAlt { 1048 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}}); 1049 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}}); 1050 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}}); 1051 0x13: decode EXT_ASI { 1052 //ASI_LDTD_AIUP 1053 0x22: TwinLoad::ldtx_aiup( |
1054 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); | 1054 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); |
1055 //ASI_LDTD_AIUS 1056 0x23: TwinLoad::ldtx_aius( | 1055 //ASI_LDTD_AIUS 1056 0x23: TwinLoad::ldtx_aius( |
1057 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); | 1057 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); |
1058 //ASI_QUAD_LDD 1059 0x24: TwinLoad::ldtx_quad_ldd( | 1058 //ASI_QUAD_LDD 1059 0x24: TwinLoad::ldtx_quad_ldd( |
1060 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); | 1060 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); |
1061 //ASI_LDTX_REAL 1062 0x26: TwinLoad::ldtx_real( | 1061 //ASI_LDTX_REAL 1062 0x26: TwinLoad::ldtx_real( |
1063 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); | 1063 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); |
1064 //ASI_LDTX_N 1065 0x27: TwinLoad::ldtx_n( | 1064 //ASI_LDTX_N 1065 0x27: TwinLoad::ldtx_n( |
1066 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); | 1066 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); |
1067 //ASI_LDTX_L 1068 0x2C: TwinLoad::ldtx_l( | 1067 //ASI_LDTX_L 1068 0x2C: TwinLoad::ldtx_l( |
1069 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); | 1069 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); |
1070 //ASI_LDTX_REAL_L 1071 0x2E: TwinLoad::ldtx_real_l( | 1070 //ASI_LDTX_REAL_L 1071 0x2E: TwinLoad::ldtx_real_l( |
1072 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); | 1072 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); |
1073 //ASI_LDTX_N_L 1074 0x2F: TwinLoad::ldtx_n_l( | 1073 //ASI_LDTX_N_L 1074 0x2F: TwinLoad::ldtx_n_l( |
1075 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); | 1075 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); |
1076 //ASI_LDTX_P 1077 0xE2: TwinLoad::ldtx_p( | 1076 //ASI_LDTX_P 1077 0xE2: TwinLoad::ldtx_p( |
1078 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); | 1078 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); |
1079 //ASI_LDTX_S 1080 0xE3: TwinLoad::ldtx_s( | 1079 //ASI_LDTX_S 1080 0xE3: TwinLoad::ldtx_s( |
1081 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); | 1081 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}}); |
1082 default: ldtwa({{ 1083 uint64_t val = Mem.udw; 1084 RdLow = val<31:0>; 1085 RdHigh = val<63:32>; 1086 }}, {{EXT_ASI}}); 1087 } 1088 } 1089 format StoreAlt { --- 4 unchanged lines hidden (view full) --- 1094 } 1095 format LoadAlt { 1096 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}}); 1097 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}}); 1098 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}}); 1099 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}}); 1100 } 1101 0x1D: LoadStoreAlt::ldstuba( | 1082 default: ldtwa({{ 1083 uint64_t val = Mem.udw; 1084 RdLow = val<31:0>; 1085 RdHigh = val<63:32>; 1086 }}, {{EXT_ASI}}); 1087 } 1088 } 1089 format StoreAlt { --- 4 unchanged lines hidden (view full) --- 1094 } 1095 format LoadAlt { 1096 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}}); 1097 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}}); 1098 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}}); 1099 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}}); 1100 } 1101 0x1D: LoadStoreAlt::ldstuba( |
1102 {{Rd = Mem.ub;}}, 1103 {{Mem.ub = 0xFF}}, {{EXT_ASI}}); | 1102 {{uReg0 = Mem.ub;}}, 1103 {{Rd.ub = uReg0; 1104 Mem.ub = 0xFF;}}, {{EXT_ASI}}); |
1104 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}}); 1105 0x1F: LoadStoreAlt::swapa( | 1105 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}}); 1106 0x1F: LoadStoreAlt::swapa( |
1106 {{uReg0 = Rd.uw; 1107 Rd.uw = Mem.uw;}}, 1108 {{Mem.uw = uReg0;}}, {{EXT_ASI}}); | 1107 {{ uReg0 = Mem.uw}}, 1108 {{ Mem.uw = Rd.uw; 1109 Rd.uw = uReg0;}}, {{EXT_ASI}}); |
1109 format Trap { | 1110 format Trap { |
1110 0x20: Load::ldf({{Frd.uw = Mem.uw;}}); | 1111 0x20: Load::ldf({{Frds.uw = Mem.uw;}}); |
1111 0x21: decode X { 1112 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}}); 1113 0x1: Load::ldxfsr({{Fsr = Mem.udw;}}); 1114 } 1115 0x22: ldqf({{fault = new FpDisabled;}}); 1116 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); | 1112 0x21: decode X { 1113 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}}); 1114 0x1: Load::ldxfsr({{Fsr = Mem.udw;}}); 1115 } 1116 0x22: ldqf({{fault = new FpDisabled;}}); 1117 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); |
1117 0x24: Store::stf({{Mem.uw = Frd.uw;}}); | 1118 0x24: Store::stf({{Mem.uw = Frds.uw;}}); |
1118 0x25: decode X { 1119 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}}); 1120 0x1: Store::stxfsr({{Mem.udw = Fsr;}}); 1121 } 1122 0x26: stqf({{fault = new FpDisabled;}}); 1123 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 1124 0x2D: Nop::prefetch({{ }}); | 1119 0x25: decode X { 1120 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}}); 1121 0x1: Store::stxfsr({{Mem.udw = Fsr;}}); 1122 } 1123 0x26: stqf({{fault = new FpDisabled;}}); 1124 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 1125 0x2D: Nop::prefetch({{ }}); |
1125 0x30: LoadAlt::ldfa({{Frd.uw = Mem.uw;}}, {{EXT_ASI}}); | 1126 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}}); |
1126 0x32: ldqfa({{fault = new FpDisabled;}}); 1127 format LoadAlt { 1128 0x33: decode EXT_ASI { 1129 //ASI_NUCLEUS 1130 0x04: FailUnimpl::lddfa_n(); 1131 //ASI_NUCLEUS_LITTLE 1132 0x0C: FailUnimpl::lddfa_nl(); 1133 //ASI_AS_IF_USER_PRIMARY --- 66 unchanged lines hidden (view full) --- 1200 0xDA: FailUnimpl::ldshortf_16pl(); 1201 //ASI_FL16_SECONDARY_LITTLE 1202 0xDB: FailUnimpl::ldshortf_16sl(); 1203 //Not an ASI which is legal with lddfa 1204 default: Trap::lddfa_bad_asi( 1205 {{fault = new DataAccessException;}}); 1206 } 1207 } | 1127 0x32: ldqfa({{fault = new FpDisabled;}}); 1128 format LoadAlt { 1129 0x33: decode EXT_ASI { 1130 //ASI_NUCLEUS 1131 0x04: FailUnimpl::lddfa_n(); 1132 //ASI_NUCLEUS_LITTLE 1133 0x0C: FailUnimpl::lddfa_nl(); 1134 //ASI_AS_IF_USER_PRIMARY --- 66 unchanged lines hidden (view full) --- 1201 0xDA: FailUnimpl::ldshortf_16pl(); 1202 //ASI_FL16_SECONDARY_LITTLE 1203 0xDB: FailUnimpl::ldshortf_16sl(); 1204 //Not an ASI which is legal with lddfa 1205 default: Trap::lddfa_bad_asi( 1206 {{fault = new DataAccessException;}}); 1207 } 1208 } |
1208 0x34: Store::stfa({{Mem.uw = Frd.uw;}}); | 1209 0x34: Store::stfa({{Mem.uw = Frds.uw;}}); |
1209 0x36: stqfa({{fault = new FpDisabled;}}); 1210 format StoreAlt { 1211 0x37: decode EXT_ASI { 1212 //ASI_NUCLEUS 1213 0x04: FailUnimpl::stdfa_n(); 1214 //ASI_NUCLEUS_LITTLE 1215 0x0C: FailUnimpl::stdfa_nl(); 1216 //ASI_AS_IF_USER_PRIMARY --- 92 unchanged lines hidden --- | 1210 0x36: stqfa({{fault = new FpDisabled;}}); 1211 format StoreAlt { 1212 0x37: decode EXT_ASI { 1213 //ASI_NUCLEUS 1214 0x04: FailUnimpl::stdfa_n(); 1215 //ASI_NUCLEUS_LITTLE 1216 0x0C: FailUnimpl::stdfa_nl(); 1217 //ASI_AS_IF_USER_PRIMARY --- 92 unchanged lines hidden --- |