decoder.isa (3949:b6664282d899) decoder.isa (3952:092d03b2ab95)
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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1004 }
1005 }
1006 }
1007 0x3: decode OP3 {
1008 format Load {
1009 0x00: lduw({{Rd = Mem.uw;}});
1010 0x01: ldub({{Rd = Mem.ub;}});
1011 0x02: lduh({{Rd = Mem.uhw;}});
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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1004 }
1005 }
1006 }
1007 0x3: decode OP3 {
1008 format Load {
1009 0x00: lduw({{Rd = Mem.uw;}});
1010 0x01: ldub({{Rd = Mem.ub;}});
1011 0x02: lduh({{Rd = Mem.uhw;}});
1012 0x03: ldd({{
1012 0x03: ldtw({{
1013 uint64_t val = Mem.udw;
1014 RdLow = val<31:0>;
1015 RdHigh = val<63:32>;
1016 }});
1017 }
1018 format Store {
1019 0x04: stw({{Mem.uw = Rd.sw;}});
1020 0x05: stb({{Mem.ub = Rd.sb;}});
1021 0x06: sth({{Mem.uhw = Rd.shw;}});
1013 uint64_t val = Mem.udw;
1014 RdLow = val<31:0>;
1015 RdHigh = val<63:32>;
1016 }});
1017 }
1018 format Store {
1019 0x04: stw({{Mem.uw = Rd.sw;}});
1020 0x05: stb({{Mem.ub = Rd.sb;}});
1021 0x06: sth({{Mem.uhw = Rd.shw;}});
1022 0x07: std({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
1022 0x07: sttw({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
1023 }
1024 format Load {
1025 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
1026 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
1027 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
1028 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
1029 }
1030 0x0D: LoadStore::ldstub(
1031 {{Rd = Mem.ub;}},
1032 {{Mem.ub = 0xFF;}});
1033 0x0E: Store::stx({{Mem.udw = Rd}});
1034 0x0F: LoadStore::swap(
1035 {{uReg0 = Rd.uw;
1036 Rd.uw = Mem.uw;}},
1037 {{Mem.uw = uReg0;}});
1038 format LoadAlt {
1039 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
1040 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
1041 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
1023 }
1024 format Load {
1025 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
1026 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
1027 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
1028 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
1029 }
1030 0x0D: LoadStore::ldstub(
1031 {{Rd = Mem.ub;}},
1032 {{Mem.ub = 0xFF;}});
1033 0x0E: Store::stx({{Mem.udw = Rd}});
1034 0x0F: LoadStore::swap(
1035 {{uReg0 = Rd.uw;
1036 Rd.uw = Mem.uw;}},
1037 {{Mem.uw = uReg0;}});
1038 format LoadAlt {
1039 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
1040 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
1041 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
1042 0x13: ldda({{
1042 0x13: ldtwa({{
1043 uint64_t val = Mem.udw;
1044 RdLow = val<31:0>;
1045 RdHigh = val<63:32>;
1046 }}, {{EXT_ASI}});
1047 }
1048 format StoreAlt {
1049 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
1050 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
1051 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
1043 uint64_t val = Mem.udw;
1044 RdLow = val<31:0>;
1045 RdHigh = val<63:32>;
1046 }}, {{EXT_ASI}});
1047 }
1048 format StoreAlt {
1049 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
1050 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
1051 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
1052 0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}});
1052 0x17: sttwa({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}});
1053 }
1054 format LoadAlt {
1055 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
1056 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}});
1057 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}});
1058 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}});
1059 }
1060 0x1D: LoadStoreAlt::ldstuba(

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1100 //ASI_REAL
1101 0x14: FailUnimpl::lddfa_real();
1102 //ASI_REAL_LITTLE
1103 0x1C: FailUnimpl::lddfa_real_l();
1104 //ASI_REAL_IO
1105 0x15: FailUnimpl::lddfa_real_io();
1106 //ASI_REAL_IO_LITTLE
1107 0x1D: FailUnimpl::lddfa_real_io_l();
1053 }
1054 format LoadAlt {
1055 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
1056 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}});
1057 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}});
1058 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}});
1059 }
1060 0x1D: LoadStoreAlt::ldstuba(

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1100 //ASI_REAL
1101 0x14: FailUnimpl::lddfa_real();
1102 //ASI_REAL_LITTLE
1103 0x1C: FailUnimpl::lddfa_real_l();
1104 //ASI_REAL_IO
1105 0x15: FailUnimpl::lddfa_real_io();
1106 //ASI_REAL_IO_LITTLE
1107 0x1D: FailUnimpl::lddfa_real_io_l();
1108 //ASI_LDTX_REAL
1109 0x26: TwinLoad::ldtx_real(
1110 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1111 //ASI_LDTX_N
1112 0x27: TwinLoad::ldtx_n(
1113 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1114 //ASI_LDTX_REAL_L
1115 0x2E: TwinLoad::ldtx_real_l(
1116 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1117 //ASI_LDTX_N_L
1118 0x2F: TwinLoad::ldtx_n_l(
1119 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1108 //ASI_PRIMARY
1109 0x80: FailUnimpl::lddfa_p();
1110 //ASI_PRIMARY_LITTLE
1111 0x88: FailUnimpl::lddfa_pl();
1112 //ASI_SECONDARY
1113 0x81: FailUnimpl::lddfa_s();
1114 //ASI_SECONDARY_LITTLE
1115 0x89: FailUnimpl::lddfa_sl();

--- 152 unchanged lines hidden --- 		1120 //ASI_PRIMARY
1121 0x80: FailUnimpl::lddfa_p();
1122 //ASI_PRIMARY_LITTLE
1123 0x88: FailUnimpl::lddfa_pl();
1124 //ASI_SECONDARY
1125 0x81: FailUnimpl::lddfa_s();
1126 //ASI_SECONDARY_LITTLE
1127 0x89: FailUnimpl::lddfa_sl();

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