decoder.isa (3930:f96f7e258255) decoder.isa (3931:de791fa53d04)
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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181 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
182 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
183 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
184 0x0A: umul({{
185 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
186 Y = Rd<63:32>;
187 }});
188 0x0B: smul({{
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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181 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
182 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
183 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
184 0x0A: umul({{
185 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
186 Y = Rd<63:32>;
187 }});
188 0x0B: smul({{
189 Rd.sdw = sext<32>(Rs1.sdw) * sext<32>(Rs2_or_imm13);
189 Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
190 Y = Rd.sdw<63:32>;
191 }});
192 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
193 0x0D: udivx({{
194 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
195 else Rd.udw = Rs1.udw / Rs2_or_imm13;
196 }});
197 0x0E: udiv({{

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241 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
242 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
243 0x18: addccc({{
244 int64_t resTemp, val2 = Rs2_or_imm13;
245 int64_t carryin = Ccr<0:0>;
246 Rd = resTemp = Rs1 + val2 + carryin;}},
247 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
248 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
190 Y = Rd.sdw<63:32>;
191 }});
192 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
193 0x0D: udivx({{
194 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
195 else Rd.udw = Rs1.udw / Rs2_or_imm13;
196 }});
197 0x0E: udiv({{

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241 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
242 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
243 0x18: addccc({{
244 int64_t resTemp, val2 = Rs2_or_imm13;
245 int64_t carryin = Ccr<0:0>;
246 Rd = resTemp = Rs1 + val2 + carryin;}},
247 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
248 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
249 {{(Rs1<63:1> + val2<63:1> +
250 ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
249 {{((Rs1 & val2) | (~resTemp & (Rs1 | val2)))<63:>}},
251 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
252 );
253 0x1A: umulcc({{
254 uint64_t resTemp;
255 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
256 Y = resTemp<63:32>;}},
257 {{0}},{{0}},{{0}},{{0}});
258 0x1B: smulcc({{
259 int64_t resTemp;
250 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
251 );
252 0x1A: umulcc({{
253 uint64_t resTemp;
254 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
255 Y = resTemp<63:32>;}},
256 {{0}},{{0}},{{0}},{{0}});
257 0x1B: smulcc({{
258 int64_t resTemp;
260 Rd = resTemp = sext<32>(Rs1.sdw) * sext<32>(Rs2_or_imm13);
259 Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
261 Y = resTemp<63:32>;}},
262 {{0}},{{0}},{{0}},{{0}});
263 0x1C: subccc({{
264 int64_t resTemp, val2 = Rs2_or_imm13;
265 int64_t carryin = Ccr<0:0>;
266 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
260 Y = resTemp<63:32>;}},
261 {{0}},{{0}},{{0}},{{0}});
262 0x1C: subccc({{
263 int64_t resTemp, val2 = Rs2_or_imm13;
264 int64_t carryin = Ccr<0:0>;
265 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
267 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
266 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<31:>}},
268 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
267 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
269 {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
268 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<63:>}},
270 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
271 );
272 0x1D: udivxcc({{
273 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
274 else Rd = Rs1.udw / Rs2_or_imm13.udw;}}
275 ,{{0}},{{0}},{{0}},{{0}});
276 0x1E: udivcc({{
277 uint32_t resTemp, val2 = Rs2_or_imm13.udw;

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659 Fsr &= ~(0x1F);
660 }});
661 0x02: fmovd({{
662 Frd.udw = Frs2.udw;
663 //fsr.ftt = fsr.cexc = 0
664 Fsr &= ~(7 << 14);
665 Fsr &= ~(0x1F);
666 }});
269 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
270 );
271 0x1D: udivxcc({{
272 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
273 else Rd = Rs1.udw / Rs2_or_imm13.udw;}}
274 ,{{0}},{{0}},{{0}},{{0}});
275 0x1E: udivcc({{
276 uint32_t resTemp, val2 = Rs2_or_imm13.udw;

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658 Fsr &= ~(0x1F);
659 }});
660 0x02: fmovd({{
661 Frd.udw = Frs2.udw;
662 //fsr.ftt = fsr.cexc = 0
663 Fsr &= ~(7 << 14);
664 Fsr &= ~(0x1F);
665 }});
667 0x03: Trap::fmovq({{fault = new FpDisabled;}});
666 0x03: Trap::fmovq({{fault = new FpExceptionOther;}});
668 0x05: fnegs({{
669 Frds.uw = Frs2s.uw ^ (1UL << 31);
670 //fsr.ftt = fsr.cexc = 0
671 Fsr &= ~(7 << 14);
672 Fsr &= ~(0x1F);
673 }});
674 0x06: fnegd({{
675 Frd.udw = Frs2.udw ^ (1ULL << 63);

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686 }});
687 0x0A: fabsd({{
688 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;
689 //fsr.ftt = fsr.cexc = 0
690 Fsr &= ~(7 << 14);
691 Fsr &= ~(0x1F);
692 }});
693 0x0B: Trap::fabsq({{fault = new FpDisabled;}});
667 0x05: fnegs({{
668 Frds.uw = Frs2s.uw ^ (1UL << 31);
669 //fsr.ftt = fsr.cexc = 0
670 Fsr &= ~(7 << 14);
671 Fsr &= ~(0x1F);
672 }});
673 0x06: fnegd({{
674 Frd.udw = Frs2.udw ^ (1ULL << 63);

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685 }});
686 0x0A: fabsd({{
687 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;
688 //fsr.ftt = fsr.cexc = 0
689 Fsr &= ~(7 << 14);
690 Fsr &= ~(0x1F);
691 }});
692 0x0B: Trap::fabsq({{fault = new FpDisabled;}});
694 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}});
695 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}});
693 0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}});
694 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}});
696 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
697 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
698 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
699 0x43: Trap::faddq({{fault = new FpDisabled;}});
700 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
701 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
702 0x47: Trap::fsubq({{fault = new FpDisabled;}});
703 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});

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855 0x6D: Trap::fxors({{fault = new IllegalInstruction;}});
856 0x6E: Trap::fnand({{fault = new IllegalInstruction;}});
857 0x6F: Trap::fnands({{fault = new IllegalInstruction;}});
858 0x70: Trap::fand({{fault = new IllegalInstruction;}});
859 0x71: Trap::fands({{fault = new IllegalInstruction;}});
860 0x72: Trap::fxnor({{fault = new IllegalInstruction;}});
861 0x73: Trap::fxnors({{fault = new IllegalInstruction;}});
862 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}});
695 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
696 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
697 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
698 0x43: Trap::faddq({{fault = new FpDisabled;}});
699 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
700 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
701 0x47: Trap::fsubq({{fault = new FpDisabled;}});
702 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});

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854 0x6D: Trap::fxors({{fault = new IllegalInstruction;}});
855 0x6E: Trap::fnand({{fault = new IllegalInstruction;}});
856 0x6F: Trap::fnands({{fault = new IllegalInstruction;}});
857 0x70: Trap::fand({{fault = new IllegalInstruction;}});
858 0x71: Trap::fands({{fault = new IllegalInstruction;}});
859 0x72: Trap::fxnor({{fault = new IllegalInstruction;}});
860 0x73: Trap::fxnors({{fault = new IllegalInstruction;}});
861 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}});
863 0x75: BasicOperate::fsrc1s({{Frd.uw = Frs1.uw;}});
862 0x75: BasicOperate::fsrc1s({{Frds.uw = Frs1s.uw;}});
864 0x76: Trap::fornot2({{fault = new IllegalInstruction;}});
865 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}});
866 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}});
863 0x76: Trap::fornot2({{fault = new IllegalInstruction;}});
864 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}});
865 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}});
867 0x79: BasicOperate::fsrc2s({{Frd.uw = Frs2.uw;}});
866 0x79: BasicOperate::fsrc2s({{Frds.uw = Frs2s.uw;}});
868 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}});
869 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}});
870 0x7C: Trap::for({{fault = new IllegalInstruction;}});
871 0x7D: Trap::fors({{fault = new IllegalInstruction;}});
872 0x7E: Trap::fone({{fault = new IllegalInstruction;}});
873 0x7F: Trap::fones({{fault = new IllegalInstruction;}});
874 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
875 0x81: Trap::siam({{fault = new IllegalInstruction;}});

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1125 {{Rd.ub = uReg0;
1126 Mem.ub = 0xFF;}}, {{EXT_ASI}});
1127 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}});
1128 0x1F: LoadStoreAlt::swapa(
1129 {{ uReg0 = Mem.uw}},
1130 {{ Mem.uw = Rd.uw;
1131 Rd.uw = uReg0;}}, {{EXT_ASI}});
1132 format Trap {
867 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}});
868 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}});
869 0x7C: Trap::for({{fault = new IllegalInstruction;}});
870 0x7D: Trap::fors({{fault = new IllegalInstruction;}});
871 0x7E: Trap::fone({{fault = new IllegalInstruction;}});
872 0x7F: Trap::fones({{fault = new IllegalInstruction;}});
873 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
874 0x81: Trap::siam({{fault = new IllegalInstruction;}});

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1124 {{Rd.ub = uReg0;
1125 Mem.ub = 0xFF;}}, {{EXT_ASI}});
1126 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}});
1127 0x1F: LoadStoreAlt::swapa(
1128 {{ uReg0 = Mem.uw}},
1129 {{ Mem.uw = Rd.uw;
1130 Rd.uw = uReg0;}}, {{EXT_ASI}});
1131 format Trap {
1133 0x20: Load::ldf({{Frd.uw = Mem.uw;}});
1132 0x20: Load::ldf({{Frds.uw = Mem.uw;}});
1134 0x21: decode X {
1135 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}});
1136 0x1: Load::ldxfsr({{Fsr = Mem.udw;}});
1137 }
1138 0x22: ldqf({{fault = new FpDisabled;}});
1139 0x23: Load::lddf({{Frd.udw = Mem.udw;}});
1133 0x21: decode X {
1134 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}});
1135 0x1: Load::ldxfsr({{Fsr = Mem.udw;}});
1136 }
1137 0x22: ldqf({{fault = new FpDisabled;}});
1138 0x23: Load::lddf({{Frd.udw = Mem.udw;}});
1140 0x24: Store::stf({{Mem.uw = Frd.uw;}});
1139 0x24: Store::stf({{Mem.uw = Frds.uw;}});
1141 0x25: decode X {
1142 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}});
1143 0x1: Store::stxfsr({{Mem.udw = Fsr;}});
1144 }
1145 0x26: stqf({{fault = new FpDisabled;}});
1146 0x27: Store::stdf({{Mem.udw = Frd.udw;}});
1147 0x2D: Nop::prefetch({{ }});
1140 0x25: decode X {
1141 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}});
1142 0x1: Store::stxfsr({{Mem.udw = Fsr;}});
1143 }
1144 0x26: stqf({{fault = new FpDisabled;}});
1145 0x27: Store::stdf({{Mem.udw = Frd.udw;}});
1146 0x2D: Nop::prefetch({{ }});
1148 0x30: LoadAlt::ldfa({{Frd.uw = Mem.uw;}}, {{EXT_ASI}});
1147 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}});
1149 0x32: ldqfa({{fault = new FpDisabled;}});
1150 format LoadAlt {
1151 0x33: decode EXT_ASI {
1152 //ASI_NUCLEUS
1153 0x04: FailUnimpl::lddfa_n();
1154 //ASI_NUCLEUS_LITTLE
1155 0x0C: FailUnimpl::lddfa_nl();
1156 //ASI_AS_IF_USER_PRIMARY

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1223 0xDA: FailUnimpl::ldshortf_16pl();
1224 //ASI_FL16_SECONDARY_LITTLE
1225 0xDB: FailUnimpl::ldshortf_16sl();
1226 //Not an ASI which is legal with lddfa
1227 default: Trap::lddfa_bad_asi(
1228 {{fault = new DataAccessException;}});
1229 }
1230 }
1148 0x32: ldqfa({{fault = new FpDisabled;}});
1149 format LoadAlt {
1150 0x33: decode EXT_ASI {
1151 //ASI_NUCLEUS
1152 0x04: FailUnimpl::lddfa_n();
1153 //ASI_NUCLEUS_LITTLE
1154 0x0C: FailUnimpl::lddfa_nl();
1155 //ASI_AS_IF_USER_PRIMARY

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1222 0xDA: FailUnimpl::ldshortf_16pl();
1223 //ASI_FL16_SECONDARY_LITTLE
1224 0xDB: FailUnimpl::ldshortf_16sl();
1225 //Not an ASI which is legal with lddfa
1226 default: Trap::lddfa_bad_asi(
1227 {{fault = new DataAccessException;}});
1228 }
1229 }
1231 0x34: Store::stfa({{Mem.uw = Frd.uw;}});
1230 0x34: Store::stfa({{Mem.uw = Frds.uw;}});
1232 0x36: stqfa({{fault = new FpDisabled;}});
1233 format StoreAlt {
1234 0x37: decode EXT_ASI {
1235 //ASI_NUCLEUS
1236 0x04: FailUnimpl::stdfa_n();
1237 //ASI_NUCLEUS_LITTLE
1238 0x0C: FailUnimpl::stdfa_nl();
1239 //ASI_AS_IF_USER_PRIMARY

--- 92 unchanged lines hidden --- 		1231 0x36: stqfa({{fault = new FpDisabled;}});
1232 format StoreAlt {
1233 0x37: decode EXT_ASI {
1234 //ASI_NUCLEUS
1235 0x04: FailUnimpl::stdfa_n();
1236 //ASI_NUCLEUS_LITTLE
1237 0x0C: FailUnimpl::stdfa_nl();
1238 //ASI_AS_IF_USER_PRIMARY

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