decoder.isa (3928:9486450f013f) decoder.isa (3929:3640569369a5)
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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181 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
182 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
183 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
184 0x0A: umul({{
185 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
186 Y = Rd<63:32>;
187 }});
188 0x0B: smul({{
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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181 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
182 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
183 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
184 0x0A: umul({{
185 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
186 Y = Rd<63:32>;
187 }});
188 0x0B: smul({{
189 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
189 Rd.sdw = sext<32>(Rs1.sdw) * sext<32>(Rs2_or_imm13);
190 Y = Rd.sdw<63:32>;
191 }});
192 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
193 0x0D: udivx({{
194 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
195 else Rd.udw = Rs1.udw / Rs2_or_imm13;
196 }});
197 0x0E: udiv({{

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204 }
205 }});
206 0x0F: sdiv({{
207 if(Rs2_or_imm13.sdw == 0)
208 fault = new DivisionByZero;
209 else
210 {
211 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
190 Y = Rd.sdw<63:32>;
191 }});
192 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
193 0x0D: udivx({{
194 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
195 else Rd.udw = Rs1.udw / Rs2_or_imm13;
196 }});
197 0x0E: udiv({{

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204 }
205 }});
206 0x0F: sdiv({{
207 if(Rs2_or_imm13.sdw == 0)
208 fault = new DivisionByZero;
209 else
210 {
211 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
212 if(Rd.udw<63:31> != 0)
212 if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max())
213 Rd.udw = 0x7FFFFFFF;
213 Rd.udw = 0x7FFFFFFF;
214 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
215 Rd.udw = 0xFFFFFFFF80000000ULL;
214 else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min())
215 Rd.udw = ULL(0xFFFFFFFF80000000);
216 }
217 }});
218 }
219 format IntOpCc {
220 0x10: addcc({{
221 int64_t resTemp, val2 = Rs2_or_imm13;
222 Rd = resTemp = Rs1 + val2;}},
223 {{(Rs1<31:0> + val2<31:0>)<32:>}},

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252 );
253 0x1A: umulcc({{
254 uint64_t resTemp;
255 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
256 Y = resTemp<63:32>;}},
257 {{0}},{{0}},{{0}},{{0}});
258 0x1B: smulcc({{
259 int64_t resTemp;
216 }
217 }});
218 }
219 format IntOpCc {
220 0x10: addcc({{
221 int64_t resTemp, val2 = Rs2_or_imm13;
222 Rd = resTemp = Rs1 + val2;}},
223 {{(Rs1<31:0> + val2<31:0>)<32:>}},

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252 );
253 0x1A: umulcc({{
254 uint64_t resTemp;
255 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
256 Y = resTemp<63:32>;}},
257 {{0}},{{0}},{{0}},{{0}});
258 0x1B: smulcc({{
259 int64_t resTemp;
260 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>;
260 Rd = resTemp = sext<32>(Rs1.sdw) * sext<32>(Rs2_or_imm13);
261 Y = resTemp<63:32>;}},
262 {{0}},{{0}},{{0}},{{0}});
263 0x1C: subccc({{
264 int64_t resTemp, val2 = Rs2_or_imm13;
265 int64_t carryin = Ccr<0:0>;
266 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
267 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
268 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},

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291 );
292 0x1F: sdivcc({{
293 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
294 bool overflow = false, underflow = false;
295 if(val2 == 0) fault = new DivisionByZero;
296 else
297 {
298 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
261 Y = resTemp<63:32>;}},
262 {{0}},{{0}},{{0}},{{0}});
263 0x1C: subccc({{
264 int64_t resTemp, val2 = Rs2_or_imm13;
265 int64_t carryin = Ccr<0:0>;
266 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
267 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
268 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},

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291 );
292 0x1F: sdivcc({{
293 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
294 bool overflow = false, underflow = false;
295 if(val2 == 0) fault = new DivisionByZero;
296 else
297 {
298 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
299 overflow = (Rd<63:31> != 0);
300 underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF);
299 overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max());
300 underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min());
301 if(overflow) Rd = 0x7FFFFFFF;
301 if(overflow) Rd = 0x7FFFFFFF;
302 else if(underflow) Rd = 0xFFFFFFFF80000000ULL;
302 else if(underflow) Rd = ULL(0xFFFFFFFF80000000);
303 } }},
304 {{0}},
305 {{overflow || underflow}},
306 {{0}},
307 {{0}}
308 );
309 0x20: taddcc({{
310 int64_t resTemp, val2 = Rs2_or_imm13;

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371 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
372 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
373 }
374 0x27: decode X {
375 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
376 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
377 }
378 0x28: decode RS1 {
303 } }},
304 {{0}},
305 {{overflow || underflow}},
306 {{0}},
307 {{0}}
308 );
309 0x20: taddcc({{
310 int64_t resTemp, val2 = Rs2_or_imm13;

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371 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
372 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
373 }
374 0x27: decode X {
375 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
376 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
377 }
378 0x28: decode RS1 {
379 0x00: NoPriv::rdy({{Rd = Y;}});
379 0x00: NoPriv::rdy({{Rd = Y<31:0>;}});
380 //1 should cause an illegal instruction exception
381 0x02: NoPriv::rdccr({{Rd = Ccr;}});
382 0x03: NoPriv::rdasi({{Rd = Asi;}});
383 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
384 0x05: NoPriv::rdpc({{
385 if(Pstate<3:>)
386 Rd = (xc->readPC())<31:0>;
387 else

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521 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
522 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
523 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
524 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
525 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
526 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
527 }
528 0x30: decode RD {
380 //1 should cause an illegal instruction exception
381 0x02: NoPriv::rdccr({{Rd = Ccr;}});
382 0x03: NoPriv::rdasi({{Rd = Asi;}});
383 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
384 0x05: NoPriv::rdpc({{
385 if(Pstate<3:>)
386 Rd = (xc->readPC())<31:0>;
387 else

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521 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
522 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
523 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
524 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
525 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
526 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
527 }
528 0x30: decode RD {
529 0x00: NoPriv::wry({{Y = Rs1 ^ Rs2_or_imm13;}});
529 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}});
530 //0x01 should cause an illegal instruction exception
531 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
532 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
533 //0x04-0x05 should cause an illegal instruction exception
534 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
535 //0x07-0x0E should cause an illegal instruction exception
536 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
537 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});

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877 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
878 0x38: Branch::jmpl({{
879 Addr target = Rs1 + Rs2_or_imm13;
880 if(target & 0x3)
881 fault = new MemAddressNotAligned;
882 else
883 {
884 if (Pstate<3:>)
530 //0x01 should cause an illegal instruction exception
531 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
532 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
533 //0x04-0x05 should cause an illegal instruction exception
534 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
535 //0x07-0x0E should cause an illegal instruction exception
536 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
537 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});

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877 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
878 0x38: Branch::jmpl({{
879 Addr target = Rs1 + Rs2_or_imm13;
880 if(target & 0x3)
881 fault = new MemAddressNotAligned;
882 else
883 {
884 if (Pstate<3:>)
885 (Rd = xc->readPC())<31:0>;
885 Rd = (xc->readPC())<31:0>;
886 else
887 Rd = xc->readPC();
888 NNPC = target;
889 }
890 }});
891 0x39: Branch::return({{
892 //If both MemAddressNotAligned and
893 //a fill trap happen, it's not clear

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1053 }
1054 format Load {
1055 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
1056 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
1057 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
1058 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
1059 }
1060 0x0D: LoadStore::ldstub(
886 else
887 Rd = xc->readPC();
888 NNPC = target;
889 }
890 }});
891 0x39: Branch::return({{
892 //If both MemAddressNotAligned and
893 //a fill trap happen, it's not clear

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1053 }
1054 format Load {
1055 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
1056 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
1057 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
1058 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
1059 }
1060 0x0D: LoadStore::ldstub(
1061 {{Rd = Mem.ub;}},
1062 {{Mem.ub = 0xFF;}});
1061 {{uReg0 = Mem.ub;}},
1062 {{Rd.ub = uReg0;
1063 Mem.ub = 0xFF;}});
1063 0x0E: Store::stx({{Mem.udw = Rd}});
1064 0x0F: LoadStore::swap(
1064 0x0E: Store::stx({{Mem.udw = Rd}});
1065 0x0F: LoadStore::swap(
1065 {{uReg0 = Rd.uw;
1066 Rd.uw = Mem.uw;}},
1067 {{Mem.uw = uReg0;}});
1066 {{ uReg0 = Mem.uw}},
1067 {{ Mem.uw = Rd.uw;
1068 Rd.uw = uReg0;}});
1068 format LoadAlt {
1069 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
1070 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
1071 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
1072 0x13: decode EXT_ASI {
1073 //ASI_LDTD_AIUP
1074 0x22: TwinLoad::ldtx_aiup(
1069 format LoadAlt {
1070 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
1071 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
1072 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
1073 0x13: decode EXT_ASI {
1074 //ASI_LDTD_AIUP
1075 0x22: TwinLoad::ldtx_aiup(
1075 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1076 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1076 //ASI_LDTD_AIUS
1077 0x23: TwinLoad::ldtx_aius(
1077 //ASI_LDTD_AIUS
1078 0x23: TwinLoad::ldtx_aius(
1078 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1079 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1079 //ASI_QUAD_LDD
1080 0x24: TwinLoad::ldtx_quad_ldd(
1080 //ASI_QUAD_LDD
1081 0x24: TwinLoad::ldtx_quad_ldd(
1081 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1082 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1082 //ASI_LDTX_REAL
1083 0x26: TwinLoad::ldtx_real(
1083 //ASI_LDTX_REAL
1084 0x26: TwinLoad::ldtx_real(
1084 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1085 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1085 //ASI_LDTX_N
1086 0x27: TwinLoad::ldtx_n(
1086 //ASI_LDTX_N
1087 0x27: TwinLoad::ldtx_n(
1087 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1088 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1088 //ASI_LDTX_L
1089 0x2C: TwinLoad::ldtx_l(
1089 //ASI_LDTX_L
1090 0x2C: TwinLoad::ldtx_l(
1090 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1091 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1091 //ASI_LDTX_REAL_L
1092 0x2E: TwinLoad::ldtx_real_l(
1092 //ASI_LDTX_REAL_L
1093 0x2E: TwinLoad::ldtx_real_l(
1093 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1094 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1094 //ASI_LDTX_N_L
1095 0x2F: TwinLoad::ldtx_n_l(
1095 //ASI_LDTX_N_L
1096 0x2F: TwinLoad::ldtx_n_l(
1096 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1097 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1097 //ASI_LDTX_P
1098 0xE2: TwinLoad::ldtx_p(
1098 //ASI_LDTX_P
1099 0xE2: TwinLoad::ldtx_p(
1099 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1100 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1100 //ASI_LDTX_S
1101 0xE3: TwinLoad::ldtx_s(
1101 //ASI_LDTX_S
1102 0xE3: TwinLoad::ldtx_s(
1102 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1103 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1103 default: ldtwa({{
1104 uint64_t val = Mem.udw;
1105 RdLow = val<31:0>;
1106 RdHigh = val<63:32>;
1107 }}, {{EXT_ASI}});
1108 }
1109 }
1110 format StoreAlt {

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1115 }
1116 format LoadAlt {
1117 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
1118 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}});
1119 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}});
1120 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}});
1121 }
1122 0x1D: LoadStoreAlt::ldstuba(
1104 default: ldtwa({{
1105 uint64_t val = Mem.udw;
1106 RdLow = val<31:0>;
1107 RdHigh = val<63:32>;
1108 }}, {{EXT_ASI}});
1109 }
1110 }
1111 format StoreAlt {

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1116 }
1117 format LoadAlt {
1118 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
1119 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}});
1120 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}});
1121 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}});
1122 }
1123 0x1D: LoadStoreAlt::ldstuba(
1123 {{Rd = Mem.ub;}},
1124 {{Mem.ub = 0xFF}}, {{EXT_ASI}});
1124 {{uReg0 = Mem.ub;}},
1125 {{Rd.ub = uReg0;
1126 Mem.ub = 0xFF;}}, {{EXT_ASI}});
1125 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}});
1126 0x1F: LoadStoreAlt::swapa(
1127 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}});
1128 0x1F: LoadStoreAlt::swapa(
1127 {{uReg0 = Rd.uw;
1128 Rd.uw = Mem.uw;}},
1129 {{Mem.uw = uReg0;}}, {{EXT_ASI}});
1129 {{ uReg0 = Mem.uw}},
1130 {{ Mem.uw = Rd.uw;
1131 Rd.uw = uReg0;}}, {{EXT_ASI}});
1130 format Trap {
1131 0x20: Load::ldf({{Frd.uw = Mem.uw;}});
1132 0x21: decode X {
1133 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}});
1134 0x1: Load::ldxfsr({{Fsr = Mem.udw;}});
1135 }
1136 0x22: ldqf({{fault = new FpDisabled;}});
1137 0x23: Load::lddf({{Frd.udw = Mem.udw;}});

--- 192 unchanged lines hidden --- 		1132 format Trap {
1133 0x20: Load::ldf({{Frd.uw = Mem.uw;}});
1134 0x21: decode X {
1135 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}});
1136 0x1: Load::ldxfsr({{Fsr = Mem.udw;}});
1137 }
1138 0x22: ldqf({{fault = new FpDisabled;}});
1139 0x23: Load::lddf({{Frd.udw = Mem.udw;}});

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