decoder.isa (3926:c57925da8d38) | decoder.isa (3928:9486450f013f) |
---|---|
1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 149 unchanged lines hidden (view full) --- 158 } 159 } 160 //SETHI (or NOP if rd == 0 and imm == 0) 161 0x4: SetHi::sethi({{Rd.udw = imm;}}); 162 0x5: Trap::fbpfcc({{fault = new FpDisabled;}}); 163 0x6: Trap::fbfcc({{fault = new FpDisabled;}}); 164 } 165 0x1: BranchN::call(30, {{ | 1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 149 unchanged lines hidden (view full) --- 158 } 159 } 160 //SETHI (or NOP if rd == 0 and imm == 0) 161 0x4: SetHi::sethi({{Rd.udw = imm;}}); 162 0x5: Trap::fbpfcc({{fault = new FpDisabled;}}); 163 0x6: Trap::fbfcc({{fault = new FpDisabled;}}); 164 } 165 0x1: BranchN::call(30, {{ |
166 R15 = xc->readPC(); | 166 if (Pstate<3:>) 167 R15 = (xc->readPC())<31:0>; 168 else 169 R15 = xc->readPC(); |
167 NNPC = R15 + disp; 168 }}); 169 0x2: decode OP3 { 170 format IntOp { 171 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 172 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}}); 173 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}}); 174 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}}); --- 398 unchanged lines hidden (view full) --- 573 0x1: Priv::restored({{ 574 assert(Cansave || Otherwin); 575 assert(Canrestore < NWindows - 2); 576 Canrestore = Canrestore + 1; 577 if(Otherwin == 0) 578 Cansave = Cansave - 1; 579 else 580 Otherwin = Otherwin - 1; | 170 NNPC = R15 + disp; 171 }}); 172 0x2: decode OP3 { 173 format IntOp { 174 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 175 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}}); 176 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}}); 177 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}}); --- 398 unchanged lines hidden (view full) --- 576 0x1: Priv::restored({{ 577 assert(Cansave || Otherwin); 578 assert(Canrestore < NWindows - 2); 579 Canrestore = Canrestore + 1; 580 if(Otherwin == 0) 581 Cansave = Cansave - 1; 582 else 583 Otherwin = Otherwin - 1; |
584 585 if(Cleanwin < NWindows - 1) 586 Cleanwin = Cleanwin + 1; |
|
581 }}); 582 } 583 0x32: decode RD { 584 0x00: Priv::wrprtpc({{ 585 if(Tl == 0) 586 return new IllegalInstruction; 587 else 588 Tpc = Rs1 ^ Rs2_or_imm13; --- 281 unchanged lines hidden (view full) --- 870 } 871 0x37: Trap::impdep2({{fault = new IllegalInstruction;}}); 872 0x38: Branch::jmpl({{ 873 Addr target = Rs1 + Rs2_or_imm13; 874 if(target & 0x3) 875 fault = new MemAddressNotAligned; 876 else 877 { | 587 }}); 588 } 589 0x32: decode RD { 590 0x00: Priv::wrprtpc({{ 591 if(Tl == 0) 592 return new IllegalInstruction; 593 else 594 Tpc = Rs1 ^ Rs2_or_imm13; --- 281 unchanged lines hidden (view full) --- 876 } 877 0x37: Trap::impdep2({{fault = new IllegalInstruction;}}); 878 0x38: Branch::jmpl({{ 879 Addr target = Rs1 + Rs2_or_imm13; 880 if(target & 0x3) 881 fault = new MemAddressNotAligned; 882 else 883 { |
878 Rd = xc->readPC(); | 884 if (Pstate<3:>) 885 (Rd = xc->readPC())<31:0>; 886 else 887 Rd = xc->readPC(); |
879 NNPC = target; 880 } 881 }}); 882 0x39: Branch::return({{ 883 //If both MemAddressNotAligned and 884 //a fill trap happen, it's not clear 885 //which one should be returned. 886 Addr target = Rs1 + Rs2_or_imm13; --- 434 unchanged lines hidden --- | 888 NNPC = target; 889 } 890 }}); 891 0x39: Branch::return({{ 892 //If both MemAddressNotAligned and 893 //a fill trap happen, it's not clear 894 //which one should be returned. 895 Addr target = Rs1 + Rs2_or_imm13; --- 434 unchanged lines hidden --- |