decoder.isa (3918:1f9a98d198e8) decoder.isa (3926:c57925da8d38)
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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463 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});
464 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}});
465 0x0E: Priv::rdprwstate({{Rd = Wstate;}});
466 //0x0F should cause an illegal instruction exception
467 0x10: Priv::rdprgl({{Rd = Gl;}});
468 //0x11-0x1F should cause an illegal instruction exception
469 }
470 0x2B: BasicOperate::flushw({{
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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463 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});
464 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}});
465 0x0E: Priv::rdprwstate({{Rd = Wstate;}});
466 //0x0F should cause an illegal instruction exception
467 0x10: Priv::rdprgl({{Rd = Gl;}});
468 //0x11-0x1F should cause an illegal instruction exception
469 }
470 0x2B: BasicOperate::flushw({{
471 if(NWindows - 2 - Cansave == 0)
471 if(NWindows - 2 - Cansave != 0)
472 {
473 if(Otherwin)
472 {
473 if(Otherwin)
474 fault = new SpillNOther(Wstate<5:3>);
474 fault = new SpillNOther(4*Wstate<5:3>);
475 else
475 else
476 fault = new SpillNNormal(Wstate<2:0>);
476 fault = new SpillNNormal(4*Wstate<2:0>);
477 }
478 }});
479 0x2C: decode MOVCC3
480 {
481 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
482 0x1: decode CC
483 {
484 0x0: movcci({{

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680 }});
681 0x0A: fabsd({{
682 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;
683 //fsr.ftt = fsr.cexc = 0
684 Fsr &= ~(7 << 14);
685 Fsr &= ~(0x1F);
686 }});
687 0x0B: Trap::fabsq({{fault = new FpDisabled;}});
477 }
478 }});
479 0x2C: decode MOVCC3
480 {
481 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
482 0x1: decode CC
483 {
484 0x0: movcci({{

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680 }});
681 0x0A: fabsd({{
682 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;
683 //fsr.ftt = fsr.cexc = 0
684 Fsr &= ~(7 << 14);
685 Fsr &= ~(0x1F);
686 }});
687 0x0B: Trap::fabsq({{fault = new FpDisabled;}});
688 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}});
689 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}});
688 0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}});
689 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}});
690 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
691 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
692 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
693 0x43: Trap::faddq({{fault = new FpDisabled;}});
694 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
695 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
696 0x47: Trap::fsubq({{fault = new FpDisabled;}});
697 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});

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888 fault = new MemAddressNotAligned;
889 else
890 NNPC = target;
891 if(fault == NoFault)
892 {
893 if(Canrestore == 0)
894 {
895 if(Otherwin)
690 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
691 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
692 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
693 0x43: Trap::faddq({{fault = new FpDisabled;}});
694 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
695 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
696 0x47: Trap::fsubq({{fault = new FpDisabled;}});
697 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});

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888 fault = new MemAddressNotAligned;
889 else
890 NNPC = target;
891 if(fault == NoFault)
892 {
893 if(Canrestore == 0)
894 {
895 if(Otherwin)
896 fault = new FillNOther(Wstate<5:3>);
896 fault = new FillNOther(4*Wstate<5:3>);
897 else
897 else
898 fault = new FillNNormal(Wstate<2:0>);
898 fault = new FillNNormal(4*Wstate<2:0>);
899 }
900 else
901 {
902 //CWP should be set directly so that it always happens
903 //Also, this will allow writing to the new window and
904 //reading from the old one
905 Cwp = (Cwp - 1 + NWindows) % NWindows;
906 Cansave = Cansave + 1;

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944 0x3B: Nop::flush({{/*Instruction memory flush*/}});
945 0x3C: save({{
946 //CWP should be set directly so that it always happens
947 //Also, this will allow writing to the new window and
948 //reading from the old one
949 if(Cansave == 0)
950 {
951 if(Otherwin)
899 }
900 else
901 {
902 //CWP should be set directly so that it always happens
903 //Also, this will allow writing to the new window and
904 //reading from the old one
905 Cwp = (Cwp - 1 + NWindows) % NWindows;
906 Cansave = Cansave + 1;

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944 0x3B: Nop::flush({{/*Instruction memory flush*/}});
945 0x3C: save({{
946 //CWP should be set directly so that it always happens
947 //Also, this will allow writing to the new window and
948 //reading from the old one
949 if(Cansave == 0)
950 {
951 if(Otherwin)
952 fault = new SpillNOther(Wstate<5:3>);
952 fault = new SpillNOther(4*Wstate<5:3>);
953 else
953 else
954 fault = new SpillNNormal(Wstate<2:0>);
954 fault = new SpillNNormal(4*Wstate<2:0>);
955 //Cwp = (Cwp + 2) % NWindows;
956 }
957 else if(Cleanwin - Canrestore == 0)
958 {
959 //Cwp = (Cwp + 1) % NWindows;
960 fault = new CleanWindow;
961 }
962 else

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970 //are written in the new window as well.
971 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
972 }
973 }});
974 0x3D: restore({{
975 if(Canrestore == 0)
976 {
977 if(Otherwin)
955 //Cwp = (Cwp + 2) % NWindows;
956 }
957 else if(Cleanwin - Canrestore == 0)
958 {
959 //Cwp = (Cwp + 1) % NWindows;
960 fault = new CleanWindow;
961 }
962 else

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970 //are written in the new window as well.
971 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
972 }
973 }});
974 0x3D: restore({{
975 if(Canrestore == 0)
976 {
977 if(Otherwin)
978 fault = new FillNOther(Wstate<5:3>);
978 fault = new FillNOther(4*Wstate<5:3>);
979 else
979 else
980 fault = new FillNNormal(Wstate<2:0>);
980 fault = new FillNNormal(4*Wstate<2:0>);
981 }
982 else
983 {
984 //CWP should be set directly so that it always happens
985 //Also, this will allow writing to the new window and
986 //reading from the old one
987 Cwp = (Cwp - 1 + NWindows) % NWindows;
988 Rd = Rs1 + Rs2_or_imm13;

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1056 {{uReg0 = Rd.uw;
1057 Rd.uw = Mem.uw;}},
1058 {{Mem.uw = uReg0;}});
1059 format LoadAlt {
1060 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
1061 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
1062 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
1063 0x13: decode EXT_ASI {
981 }
982 else
983 {
984 //CWP should be set directly so that it always happens
985 //Also, this will allow writing to the new window and
986 //reading from the old one
987 Cwp = (Cwp - 1 + NWindows) % NWindows;
988 Rd = Rs1 + Rs2_or_imm13;

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1056 {{uReg0 = Rd.uw;
1057 Rd.uw = Mem.uw;}},
1058 {{Mem.uw = uReg0;}});
1059 format LoadAlt {
1060 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
1061 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
1062 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
1063 0x13: decode EXT_ASI {
1064 //ASI_LDTD_AIUP
1065 0x22: TwinLoad::ldtx_aiup(
1066 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1067 //ASI_LDTD_AIUS
1068 0x23: TwinLoad::ldtx_aius(
1069 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1064 //ASI_QUAD_LDD
1065 0x24: TwinLoad::ldtx_quad_ldd(
1066 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1067 //ASI_LDTX_REAL
1068 0x26: TwinLoad::ldtx_real(
1069 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1070 //ASI_LDTX_N
1071 0x27: TwinLoad::ldtx_n(

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1077 0x2E: TwinLoad::ldtx_real_l(
1078 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1079 //ASI_LDTX_N_L
1080 0x2F: TwinLoad::ldtx_n_l(
1081 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1082 //ASI_LDTX_P
1083 0xE2: TwinLoad::ldtx_p(
1084 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1070 //ASI_QUAD_LDD
1071 0x24: TwinLoad::ldtx_quad_ldd(
1072 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1073 //ASI_LDTX_REAL
1074 0x26: TwinLoad::ldtx_real(
1075 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1076 //ASI_LDTX_N
1077 0x27: TwinLoad::ldtx_n(

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1083 0x2E: TwinLoad::ldtx_real_l(
1084 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1085 //ASI_LDTX_N_L
1086 0x2F: TwinLoad::ldtx_n_l(
1087 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1088 //ASI_LDTX_P
1089 0xE2: TwinLoad::ldtx_p(
1090 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1091 //ASI_LDTX_S
1092 0xE3: TwinLoad::ldtx_s(
1093 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
1085 default: ldtwa({{
1086 uint64_t val = Mem.udw;
1087 RdLow = val<31:0>;
1088 RdHigh = val<63:32>;
1089 }}, {{EXT_ASI}});
1090 }
1091 }
1092 format StoreAlt {

--- 219 unchanged lines hidden --- 		1094 default: ldtwa({{
1095 uint64_t val = Mem.udw;
1096 RdLow = val<31:0>;
1097 RdHigh = val<63:32>;
1098 }}, {{EXT_ASI}});
1099 }
1100 }
1101 format StoreAlt {

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