decoder.isa (3826:e35adf01a285) decoder.isa (3835:97b3b03865fb)
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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1025 }
1026 }
1027 }
1028 0x3: decode OP3 {
1029 format Load {
1030 0x00: lduw({{Rd = Mem.uw;}});
1031 0x01: ldub({{Rd = Mem.ub;}});
1032 0x02: lduh({{Rd = Mem.uhw;}});
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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1025 }
1026 }
1027 }
1028 0x3: decode OP3 {
1029 format Load {
1030 0x00: lduw({{Rd = Mem.uw;}});
1031 0x01: ldub({{Rd = Mem.ub;}});
1032 0x02: lduh({{Rd = Mem.uhw;}});
1033 0x03: ldd({{
1033 0x03: ldtw({{
1034 uint64_t val = Mem.udw;
1035 RdLow = val<31:0>;
1036 RdHigh = val<63:32>;
1037 }});
1038 }
1039 format Store {
1040 0x04: stw({{Mem.uw = Rd.sw;}});
1041 0x05: stb({{Mem.ub = Rd.sb;}});
1042 0x06: sth({{Mem.uhw = Rd.shw;}});
1034 uint64_t val = Mem.udw;
1035 RdLow = val<31:0>;
1036 RdHigh = val<63:32>;
1037 }});
1038 }
1039 format Store {
1040 0x04: stw({{Mem.uw = Rd.sw;}});
1041 0x05: stb({{Mem.ub = Rd.sb;}});
1042 0x06: sth({{Mem.uhw = Rd.shw;}});
1043 0x07: std({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
1043 0x07: sttw({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
1044 }
1045 format Load {
1046 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
1047 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
1048 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
1049 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
1050 }
1051 0x0D: LoadStore::ldstub(
1052 {{Rd = Mem.ub;}},
1053 {{Mem.ub = 0xFF;}});
1054 0x0E: Store::stx({{Mem.udw = Rd}});
1055 0x0F: LoadStore::swap(
1056 {{uReg0 = Rd.uw;
1057 Rd.uw = Mem.uw;}},
1058 {{Mem.uw = uReg0;}});
1059 format LoadAlt {
1060 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
1061 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
1062 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
1044 }
1045 format Load {
1046 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
1047 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
1048 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
1049 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
1050 }
1051 0x0D: LoadStore::ldstub(
1052 {{Rd = Mem.ub;}},
1053 {{Mem.ub = 0xFF;}});
1054 0x0E: Store::stx({{Mem.udw = Rd}});
1055 0x0F: LoadStore::swap(
1056 {{uReg0 = Rd.uw;
1057 Rd.uw = Mem.uw;}},
1058 {{Mem.uw = uReg0;}});
1059 format LoadAlt {
1060 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
1061 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
1062 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
1063 0x13: ldda({{
1063 0x13: ldtwa({{
1064 uint64_t val = Mem.udw;
1065 RdLow = val<31:0>;
1066 RdHigh = val<63:32>;
1067 }}, {{EXT_ASI}});
1068 }
1069 format StoreAlt {
1070 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
1071 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
1072 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
1064 uint64_t val = Mem.udw;
1065 RdLow = val<31:0>;
1066 RdHigh = val<63:32>;
1067 }}, {{EXT_ASI}});
1068 }
1069 format StoreAlt {
1070 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
1071 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
1072 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
1073 0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}});
1073 0x17: sttwa({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}});
1074 }
1075 format LoadAlt {
1076 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
1077 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}});
1078 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}});
1079 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}});
1080 }
1081 0x1D: LoadStoreAlt::ldstuba(

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1075 format LoadAlt {
1076 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
1077 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}});
1078 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}});
1079 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}});
1080 }
1081 0x1D: LoadStoreAlt::ldstuba(

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