decoder.isa (3821:07d1f7105924) decoder.isa (3823:1c8f87aa103e)
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 363 unchanged lines hidden (view full) ---

372 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
373 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
374 }
375 0x28: decode RS1 {
376 0x00: NoPriv::rdy({{Rd = Y;}});
377 //1 should cause an illegal instruction exception
378 0x02: NoPriv::rdccr({{Rd = Ccr;}});
379 0x03: NoPriv::rdasi({{Rd = Asi;}});
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 363 unchanged lines hidden (view full) ---

372 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
373 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
374 }
375 0x28: decode RS1 {
376 0x00: NoPriv::rdy({{Rd = Y;}});
377 //1 should cause an illegal instruction exception
378 0x02: NoPriv::rdccr({{Rd = Ccr;}});
379 0x03: NoPriv::rdasi({{Rd = Asi;}});
380 0x04: PrivCheck::rdtick(
381 {{ Rd = xc->readMiscRegWithEffect(MISCREG_TICK);}},
382 {{Tick<63:>}});
380 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
383 0x05: NoPriv::rdpc({{
384 if(Pstate<3:>)
385 Rd = (xc->readPC())<31:0>;
386 else
387 Rd = xc->readPC();}});
388 0x06: NoPriv::rdfprs({{
389 //Wait for all fpops to finish.
390 Rd = Fprs;

--- 9 unchanged lines hidden (view full) ---

400 0x13: NoPriv::rdgsr({{
401 if(Fprs<2:> == 0 || Pstate<4:> == 0)
402 Rd = Gsr;
403 else
404 fault = new FpDisabled;
405 }});
406 //0x14-0x15 should cause an illegal instruction exception
407 0x16: Priv::rdsoftint({{Rd = Softint;}});
381 0x05: NoPriv::rdpc({{
382 if(Pstate<3:>)
383 Rd = (xc->readPC())<31:0>;
384 else
385 Rd = xc->readPC();}});
386 0x06: NoPriv::rdfprs({{
387 //Wait for all fpops to finish.
388 Rd = Fprs;

--- 9 unchanged lines hidden (view full) ---

398 0x13: NoPriv::rdgsr({{
399 if(Fprs<2:> == 0 || Pstate<4:> == 0)
400 Rd = Gsr;
401 else
402 fault = new FpDisabled;
403 }});
404 //0x14-0x15 should cause an illegal instruction exception
405 0x16: Priv::rdsoftint({{Rd = Softint;}});
408 0x17: Priv::rdtick_cmpr({{
409 Rd = xc->readMiscRegWithEffect(MISCREG_TICK_CMPR);
410 }});
411 0x18: PrivCheck::rdstick({{
412 Rd = xc->readMiscRegWithEffect(MISCREG_STICK);
413 }}, {{Stick<63:>}});
414 0x19: Priv::rdstick_cmpr({{
415 Rd = xc->readMiscRegWithEffect(MISCREG_STICK_CMPR);
416 }});
406 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
407 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}});
408 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
417 0x1A: Priv::rdstrand_sts_reg({{
418 if(Pstate<2:> && !Hpstate<2:>)
419 Rd = StrandStsReg<0:>;
420 else
421 Rd = StrandStsReg;
422 }});
423 //0x1A is supposed to be reserved, but it reads the strand
424 //status register.

--- 7 unchanged lines hidden (view full) ---

432 Rd = Htstate;
433 }});
434 //0x02 should cause an illegal instruction exception
435 0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
436 //0x04 should cause an illegal instruction exception
437 0x05: HPriv::rdhprhtba({{Rd = Htba;}});
438 0x06: HPriv::rdhprhver({{Rd = Hver;}});
439 //0x07-0x1E should cause an illegal instruction exception
409 0x1A: Priv::rdstrand_sts_reg({{
410 if(Pstate<2:> && !Hpstate<2:>)
411 Rd = StrandStsReg<0:>;
412 else
413 Rd = StrandStsReg;
414 }});
415 //0x1A is supposed to be reserved, but it reads the strand
416 //status register.

--- 7 unchanged lines hidden (view full) ---

424 Rd = Htstate;
425 }});
426 //0x02 should cause an illegal instruction exception
427 0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
428 //0x04 should cause an illegal instruction exception
429 0x05: HPriv::rdhprhtba({{Rd = Htba;}});
430 0x06: HPriv::rdhprhver({{Rd = Hver;}});
431 //0x07-0x1E should cause an illegal instruction exception
440 0x1F: HPriv::rdhprhstick_cmpr({{
441 Rd = xc->readMiscRegWithEffect(MISCREG_HSTICK_CMPR);
442 }});
432 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
443 }
444 0x2A: decode RS1 {
445 0x00: Priv::rdprtpc({{
446 if(Tl == 0)
447 return new IllegalInstruction;
448 Rd = Tpc;
449 }});
450 0x01: Priv::rdprtnpc({{

--- 6 unchanged lines hidden (view full) ---

457 return new IllegalInstruction;
458 Rd = Tstate;
459 }});
460 0x03: Priv::rdprtt({{
461 if(Tl == 0)
462 return new IllegalInstruction;
463 Rd = Tt;
464 }});
433 }
434 0x2A: decode RS1 {
435 0x00: Priv::rdprtpc({{
436 if(Tl == 0)
437 return new IllegalInstruction;
438 Rd = Tpc;
439 }});
440 0x01: Priv::rdprtnpc({{

--- 6 unchanged lines hidden (view full) ---

447 return new IllegalInstruction;
448 Rd = Tstate;
449 }});
450 0x03: Priv::rdprtt({{
451 if(Tl == 0)
452 return new IllegalInstruction;
453 Rd = Tt;
454 }});
465 0x04: Priv::rdprtick({{
466 Rd = xc->readMiscRegWithEffect(MISCREG_TICK);
467 }});
455 0x04: Priv::rdprtick({{Rd = Tick;}});
468 0x05: Priv::rdprtba({{Rd = Tba;}});
469 0x06: Priv::rdprpstate({{Rd = Pstate;}});
470 0x07: Priv::rdprtl({{Rd = Tl;}});
471 0x08: Priv::rdprpil({{Rd = Pil;}});
472 0x09: Priv::rdprcwp({{Rd = Cwp;}});
473 0x0A: Priv::rdprcansave({{Rd = Cansave;}});
474 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});
475 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});

--- 73 unchanged lines hidden (view full) ---

549 0x13: NoPriv::wrgsr({{
550 if(Fprs<2:> == 0 || Pstate<4:> == 0)
551 return new FpDisabled;
552 Gsr = Rs1 ^ Rs2_or_imm13;
553 }});
554 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
555 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});
556 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
456 0x05: Priv::rdprtba({{Rd = Tba;}});
457 0x06: Priv::rdprpstate({{Rd = Pstate;}});
458 0x07: Priv::rdprtl({{Rd = Tl;}});
459 0x08: Priv::rdprpil({{Rd = Pil;}});
460 0x09: Priv::rdprcwp({{Rd = Cwp;}});
461 0x0A: Priv::rdprcansave({{Rd = Cansave;}});
462 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});
463 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});

--- 73 unchanged lines hidden (view full) ---

537 0x13: NoPriv::wrgsr({{
538 if(Fprs<2:> == 0 || Pstate<4:> == 0)
539 return new FpDisabled;
540 Gsr = Rs1 ^ Rs2_or_imm13;
541 }});
542 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
543 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});
544 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
557 0x17: Priv::wrtick_cmpr({{
558 xc->setMiscRegWithEffect(MISCREG_TICK_CMPR, Rs1 ^ Rs2_or_imm13);
559 }});
545 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}});
560 0x18: NoPriv::wrstick({{
561 if(!Hpstate<2:>)
562 return new IllegalInstruction;
546 0x18: NoPriv::wrstick({{
547 if(!Hpstate<2:>)
548 return new IllegalInstruction;
563 xc->setMiscRegWithEffect(MISCREG_STICK, Rs1 ^ Rs2_or_imm13);
549 Stick = Rs1 ^ Rs2_or_imm13;
564 }});
550 }});
565 0x19: Priv::wrstick_cmpr({{
566 xc->setMiscRegWithEffect(MISCREG_STICK_CMPR, Rs1 ^ Rs2_or_imm13);
567 }});
551 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}});
568 0x1A: Priv::wrstrand_sts_reg({{
569 if(Pstate<2:> && !Hpstate<2:>)
570 StrandStsReg = StrandStsReg<63:1> |
571 (Rs1 ^ Rs2_or_imm13)<0:>;
572 else
573 StrandStsReg = Rs1 ^ Rs2_or_imm13;
574 }});
575 //0x1A is supposed to be reserved, but it writes the strand

--- 40 unchanged lines hidden (view full) ---

616 Tstate = Rs1 ^ Rs2_or_imm13;
617 }});
618 0x03: Priv::wrprtt({{
619 if(Tl == 0)
620 return new IllegalInstruction;
621 else
622 Tt = Rs1 ^ Rs2_or_imm13;
623 }});
552 0x1A: Priv::wrstrand_sts_reg({{
553 if(Pstate<2:> && !Hpstate<2:>)
554 StrandStsReg = StrandStsReg<63:1> |
555 (Rs1 ^ Rs2_or_imm13)<0:>;
556 else
557 StrandStsReg = Rs1 ^ Rs2_or_imm13;
558 }});
559 //0x1A is supposed to be reserved, but it writes the strand

--- 40 unchanged lines hidden (view full) ---

600 Tstate = Rs1 ^ Rs2_or_imm13;
601 }});
602 0x03: Priv::wrprtt({{
603 if(Tl == 0)
604 return new IllegalInstruction;
605 else
606 Tt = Rs1 ^ Rs2_or_imm13;
607 }});
624 0x04: HPriv::wrprtick({{
625 xc->setMiscRegWithEffect(MISCREG_TICK, Rs1 ^ Rs2_or_imm13);
626 }});
608 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
627 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
628 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
629 0x07: Priv::wrprtl({{
630 if(Pstate<2:> && !Hpstate<2:>)
631 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
632 else
633 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);
634 }});

--- 20 unchanged lines hidden (view full) ---

655 return new IllegalInstruction;
656 Htstate = Rs1 ^ Rs2_or_imm13;
657 }});
658 //0x02 should cause an illegal instruction exception
659 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
660 //0x04 should cause an illegal instruction exception
661 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
662 //0x06-0x01D should cause an illegal instruction exception
609 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
610 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
611 0x07: Priv::wrprtl({{
612 if(Pstate<2:> && !Hpstate<2:>)
613 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
614 else
615 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);
616 }});

--- 20 unchanged lines hidden (view full) ---

637 return new IllegalInstruction;
638 Htstate = Rs1 ^ Rs2_or_imm13;
639 }});
640 //0x02 should cause an illegal instruction exception
641 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
642 //0x04 should cause an illegal instruction exception
643 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
644 //0x06-0x01D should cause an illegal instruction exception
663 0x1F: HPriv::wrhprhstick_cmpr({{
664 xc->setMiscRegWithEffect(MISCREG_HSTICK_CMPR, Rs1 ^ Rs2_or_imm13);
665 }});
645 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
666 }
667 0x34: decode OPF{
668 format BasicOperate{
669 0x01: fmovs({{
670 Frds.uw = Frs2s.uw;
671 //fsr.ftt = fsr.cexc = 0
672 Fsr &= ~(7 << 14);
673 Fsr &= ~(0x1F);

--- 633 unchanged lines hidden --- 		646 }
647 0x34: decode OPF{
648 format BasicOperate{
649 0x01: fmovs({{
650 Frds.uw = Frs2s.uw;
651 //fsr.ftt = fsr.cexc = 0
652 Fsr &= ~(7 << 14);
653 Fsr &= ~(0x1F);

--- 633 unchanged lines hidden ---