decoder.isa (3814:33bd4ec9d66a) | decoder.isa (3821:07d1f7105924) |
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1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 1060 unchanged lines hidden (view full) --- 1069 0x0D: LoadStore::ldstub( 1070 {{Rd = Mem.ub;}}, 1071 {{Mem.ub = 0xFF;}}); 1072 0x0E: Store::stx({{Mem.udw = Rd}}); 1073 0x0F: LoadStore::swap( 1074 {{uReg0 = Rd.uw; 1075 Rd.uw = Mem.uw;}}, 1076 {{Mem.uw = uReg0;}}); | 1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 1060 unchanged lines hidden (view full) --- 1069 0x0D: LoadStore::ldstub( 1070 {{Rd = Mem.ub;}}, 1071 {{Mem.ub = 0xFF;}}); 1072 0x0E: Store::stx({{Mem.udw = Rd}}); 1073 0x0F: LoadStore::swap( 1074 {{uReg0 = Rd.uw; 1075 Rd.uw = Mem.uw;}}, 1076 {{Mem.uw = uReg0;}}); |
1077 format Load { 1078 0x10: lduwa({{Rd = Mem.uw;}}); 1079 0x11: lduba({{Rd = Mem.ub;}}); 1080 0x12: lduha({{Rd = Mem.uhw;}}); | 1077 format LoadAlt { 1078 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}}); 1079 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}}); 1080 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}}); |
1081 0x13: ldda({{ 1082 uint64_t val = Mem.udw; 1083 RdLow = val<31:0>; 1084 RdHigh = val<63:32>; | 1081 0x13: ldda({{ 1082 uint64_t val = Mem.udw; 1083 RdLow = val<31:0>; 1084 RdHigh = val<63:32>; |
1085 }}); | 1085 }}, {{EXT_ASI}}); |
1086 } | 1086 } |
1087 format Store { 1088 0x14: stwa({{Mem.uw = Rd;}}); 1089 0x15: stba({{Mem.ub = Rd;}}); 1090 0x16: stha({{Mem.uhw = Rd;}}); 1091 0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}); | 1087 format StoreAlt { 1088 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}}); 1089 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}}); 1090 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}}); 1091 0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}}); |
1092 } | 1092 } |
1093 format Load { 1094 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}); 1095 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}); 1096 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}); 1097 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}); | 1093 format LoadAlt { 1094 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}}); 1095 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}}); 1096 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}}); 1097 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}}); |
1098 } | 1098 } |
1099 0x1D: LoadStore::ldstuba( | 1099 0x1D: LoadStoreAlt::ldstuba( |
1100 {{Rd = Mem.ub;}}, | 1100 {{Rd = Mem.ub;}}, |
1101 {{Mem.ub = 0xFF}}); 1102 0x1E: Store::stxa({{Mem.udw = Rd}}); 1103 0x1F: LoadStore::swapa( | 1101 {{Mem.ub = 0xFF}}, {{EXT_ASI}}); 1102 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}}); 1103 0x1F: LoadStoreAlt::swapa( |
1104 {{uReg0 = Rd.uw; 1105 Rd.uw = Mem.uw;}}, | 1104 {{uReg0 = Rd.uw; 1105 Rd.uw = Mem.uw;}}, |
1106 {{Mem.uw = uReg0;}}); | 1106 {{Mem.uw = uReg0;}}, {{EXT_ASI}}); |
1107 format Trap { 1108 0x20: Load::ldf({{Frd.uw = Mem.uw;}}); 1109 0x21: decode X { 1110 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}}); 1111 0x1: Load::ldxfsr({{Fsr = Mem.udw;}}); 1112 } 1113 0x22: ldqf({{fault = new FpDisabled;}}); 1114 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 1115 0x24: Store::stf({{Mem.uw = Frd.uw;}}); 1116 0x25: decode X { 1117 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}}); 1118 0x1: Store::stxfsr({{Mem.udw = Fsr;}}); 1119 } 1120 0x26: stqf({{fault = new FpDisabled;}}); 1121 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 1122 0x2D: Nop::prefetch({{ }}); | 1107 format Trap { 1108 0x20: Load::ldf({{Frd.uw = Mem.uw;}}); 1109 0x21: decode X { 1110 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}}); 1111 0x1: Load::ldxfsr({{Fsr = Mem.udw;}}); 1112 } 1113 0x22: ldqf({{fault = new FpDisabled;}}); 1114 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 1115 0x24: Store::stf({{Mem.uw = Frd.uw;}}); 1116 0x25: decode X { 1117 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}}); 1118 0x1: Store::stxfsr({{Mem.udw = Fsr;}}); 1119 } 1120 0x26: stqf({{fault = new FpDisabled;}}); 1121 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 1122 0x2D: Nop::prefetch({{ }}); |
1123 0x30: Load::ldfa({{Frd.uw = Mem.uw;}}); | 1123 0x30: LoadAlt::ldfa({{Frd.uw = Mem.uw;}}, {{EXT_ASI}}); |
1124 0x32: ldqfa({{fault = new FpDisabled;}}); 1125 format LoadAlt { 1126 0x33: decode EXT_ASI { 1127 //ASI_NUCLEUS 1128 0x04: FailUnimpl::lddfa_n(); 1129 //ASI_NUCLEUS_LITTLE 1130 0x0C: FailUnimpl::lddfa_nl(); 1131 //ASI_AS_IF_USER_PRIMARY --- 35 unchanged lines hidden (view full) --- 1167 0x16: FailUnimpl::ldblockf_aiup(); 1168 //ASI_BLOCK_AS_IF_USER_SECONDARY 1169 0x17: FailUnimpl::ldblockf_aius(); 1170 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1171 0x1E: FailUnimpl::ldblockf_aiupl(); 1172 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1173 0x1F: FailUnimpl::ldblockf_aiusl(); 1174 //ASI_BLOCK_PRIMARY | 1124 0x32: ldqfa({{fault = new FpDisabled;}}); 1125 format LoadAlt { 1126 0x33: decode EXT_ASI { 1127 //ASI_NUCLEUS 1128 0x04: FailUnimpl::lddfa_n(); 1129 //ASI_NUCLEUS_LITTLE 1130 0x0C: FailUnimpl::lddfa_nl(); 1131 //ASI_AS_IF_USER_PRIMARY --- 35 unchanged lines hidden (view full) --- 1167 0x16: FailUnimpl::ldblockf_aiup(); 1168 //ASI_BLOCK_AS_IF_USER_SECONDARY 1169 0x17: FailUnimpl::ldblockf_aius(); 1170 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1171 0x1E: FailUnimpl::ldblockf_aiupl(); 1172 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1173 0x1F: FailUnimpl::ldblockf_aiusl(); 1174 //ASI_BLOCK_PRIMARY |
1175 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}); | 1175 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}}); |
1176 //ASI_BLOCK_SECONDARY 1177 0xF1: FailUnimpl::ldblockf_s(); 1178 //ASI_BLOCK_PRIMARY_LITTLE 1179 0xF8: FailUnimpl::ldblockf_pl(); 1180 //ASI_BLOCK_SECONDARY_LITTLE 1181 0xF9: FailUnimpl::ldblockf_sl(); 1182 } 1183 --- 66 unchanged lines hidden (view full) --- 1250 0x16: FailUnimpl::stblockf_aiup(); 1251 //ASI_BLOCK_AS_IF_USER_SECONDARY 1252 0x17: FailUnimpl::stblockf_aius(); 1253 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1254 0x1E: FailUnimpl::stblockf_aiupl(); 1255 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1256 0x1F: FailUnimpl::stblockf_aiusl(); 1257 //ASI_BLOCK_PRIMARY | 1176 //ASI_BLOCK_SECONDARY 1177 0xF1: FailUnimpl::ldblockf_s(); 1178 //ASI_BLOCK_PRIMARY_LITTLE 1179 0xF8: FailUnimpl::ldblockf_pl(); 1180 //ASI_BLOCK_SECONDARY_LITTLE 1181 0xF9: FailUnimpl::ldblockf_sl(); 1182 } 1183 --- 66 unchanged lines hidden (view full) --- 1250 0x16: FailUnimpl::stblockf_aiup(); 1251 //ASI_BLOCK_AS_IF_USER_SECONDARY 1252 0x17: FailUnimpl::stblockf_aius(); 1253 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1254 0x1E: FailUnimpl::stblockf_aiupl(); 1255 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1256 0x1F: FailUnimpl::stblockf_aiusl(); 1257 //ASI_BLOCK_PRIMARY |
1258 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}); | 1258 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}}); |
1259 //ASI_BLOCK_SECONDARY 1260 0xF1: FailUnimpl::stblockf_s(); 1261 //ASI_BLOCK_PRIMARY_LITTLE 1262 0xF8: FailUnimpl::stblockf_pl(); 1263 //ASI_BLOCK_SECONDARY_LITTLE 1264 0xF9: FailUnimpl::stblockf_sl(); 1265 } 1266 --- 20 unchanged lines hidden (view full) --- 1287 } 1288 } 1289 0x3C: Cas::casa( 1290 {{uReg0 = Mem.uw;}}, 1291 {{if(Rs2.uw == uReg0) 1292 Mem.uw = Rd.uw; 1293 else 1294 storeCond = false; | 1259 //ASI_BLOCK_SECONDARY 1260 0xF1: FailUnimpl::stblockf_s(); 1261 //ASI_BLOCK_PRIMARY_LITTLE 1262 0xF8: FailUnimpl::stblockf_pl(); 1263 //ASI_BLOCK_SECONDARY_LITTLE 1264 0xF9: FailUnimpl::stblockf_sl(); 1265 } 1266 --- 20 unchanged lines hidden (view full) --- 1287 } 1288 } 1289 0x3C: Cas::casa( 1290 {{uReg0 = Mem.uw;}}, 1291 {{if(Rs2.uw == uReg0) 1292 Mem.uw = Rd.uw; 1293 else 1294 storeCond = false; |
1295 Rd.uw = uReg0;}}); | 1295 Rd.uw = uReg0;}}, {{EXT_ASI}}); |
1296 0x3D: Nop::prefetcha({{ }}); 1297 0x3E: Cas::casxa( 1298 {{uReg0 = Mem.udw;}}, 1299 {{if(Rs2 == uReg0) 1300 Mem.udw = Rd; 1301 else 1302 storeCond = false; | 1296 0x3D: Nop::prefetcha({{ }}); 1297 0x3E: Cas::casxa( 1298 {{uReg0 = Mem.udw;}}, 1299 {{if(Rs2 == uReg0) 1300 Mem.udw = Rd; 1301 else 1302 storeCond = false; |
1303 Rd = uReg0;}}); | 1303 Rd = uReg0;}}, {{EXT_ASI}}); |
1304 } 1305 } 1306} | 1304 } 1305 } 1306} |