decoder.isa (3810:c2caa5f3f09f) | decoder.isa (3814:33bd4ec9d66a) |
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1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 363 unchanged lines hidden (view full) --- 372 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 373 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 374 } 375 0x28: decode RS1 { 376 0x00: NoPriv::rdy({{Rd = Y;}}); 377 //1 should cause an illegal instruction exception 378 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 379 0x03: NoPriv::rdasi({{Rd = Asi;}}); | 1// Copyright (c) 2006 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 363 unchanged lines hidden (view full) --- 372 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 373 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 374 } 375 0x28: decode RS1 { 376 0x00: NoPriv::rdy({{Rd = Y;}}); 377 //1 should cause an illegal instruction exception 378 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 379 0x03: NoPriv::rdasi({{Rd = Asi;}}); |
380 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); | 380 0x04: PrivCheck::rdtick( 381 {{ Rd = xc->readMiscRegWithEffect(MISCREG_TICK);}}, 382 {{Tick<63:>}}); |
381 0x05: NoPriv::rdpc({{ 382 if(Pstate<3:>) 383 Rd = (xc->readPC())<31:0>; 384 else 385 Rd = xc->readPC();}}); 386 0x06: NoPriv::rdfprs({{ 387 //Wait for all fpops to finish. 388 Rd = Fprs; --- 9 unchanged lines hidden (view full) --- 398 0x13: NoPriv::rdgsr({{ 399 if(Fprs<2:> == 0 || Pstate<4:> == 0) 400 Rd = Gsr; 401 else 402 fault = new FpDisabled; 403 }}); 404 //0x14-0x15 should cause an illegal instruction exception 405 0x16: Priv::rdsoftint({{Rd = Softint;}}); | 383 0x05: NoPriv::rdpc({{ 384 if(Pstate<3:>) 385 Rd = (xc->readPC())<31:0>; 386 else 387 Rd = xc->readPC();}}); 388 0x06: NoPriv::rdfprs({{ 389 //Wait for all fpops to finish. 390 Rd = Fprs; --- 9 unchanged lines hidden (view full) --- 400 0x13: NoPriv::rdgsr({{ 401 if(Fprs<2:> == 0 || Pstate<4:> == 0) 402 Rd = Gsr; 403 else 404 fault = new FpDisabled; 405 }}); 406 //0x14-0x15 should cause an illegal instruction exception 407 0x16: Priv::rdsoftint({{Rd = Softint;}}); |
406 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}}); 407 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}}); 408 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}}); | 408 0x17: Priv::rdtick_cmpr({{ 409 Rd = xc->readMiscRegWithEffect(MISCREG_TICK_CMPR); 410 }}); 411 0x18: PrivCheck::rdstick({{ 412 Rd = xc->readMiscRegWithEffect(MISCREG_STICK); 413 }}, {{Stick<63:>}}); 414 0x19: Priv::rdstick_cmpr({{ 415 Rd = xc->readMiscRegWithEffect(MISCREG_STICK_CMPR); 416 }}); |
409 0x1A: Priv::rdstrand_sts_reg({{ 410 if(Pstate<2:> && !Hpstate<2:>) 411 Rd = StrandStsReg<0:>; 412 else 413 Rd = StrandStsReg; 414 }}); 415 //0x1A is supposed to be reserved, but it reads the strand 416 //status register. --- 7 unchanged lines hidden (view full) --- 424 Rd = Htstate; 425 }}); 426 //0x02 should cause an illegal instruction exception 427 0x03: HPriv::rdhprhintp({{Rd = Hintp;}}); 428 //0x04 should cause an illegal instruction exception 429 0x05: HPriv::rdhprhtba({{Rd = Htba;}}); 430 0x06: HPriv::rdhprhver({{Rd = Hver;}}); 431 //0x07-0x1E should cause an illegal instruction exception | 417 0x1A: Priv::rdstrand_sts_reg({{ 418 if(Pstate<2:> && !Hpstate<2:>) 419 Rd = StrandStsReg<0:>; 420 else 421 Rd = StrandStsReg; 422 }}); 423 //0x1A is supposed to be reserved, but it reads the strand 424 //status register. --- 7 unchanged lines hidden (view full) --- 432 Rd = Htstate; 433 }}); 434 //0x02 should cause an illegal instruction exception 435 0x03: HPriv::rdhprhintp({{Rd = Hintp;}}); 436 //0x04 should cause an illegal instruction exception 437 0x05: HPriv::rdhprhtba({{Rd = Htba;}}); 438 0x06: HPriv::rdhprhver({{Rd = Hver;}}); 439 //0x07-0x1E should cause an illegal instruction exception |
432 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}}); | 440 0x1F: HPriv::rdhprhstick_cmpr({{ 441 Rd = xc->readMiscRegWithEffect(MISCREG_HSTICK_CMPR); 442 }}); |
433 } 434 0x2A: decode RS1 { 435 0x00: Priv::rdprtpc({{ 436 if(Tl == 0) 437 return new IllegalInstruction; 438 Rd = Tpc; 439 }}); 440 0x01: Priv::rdprtnpc({{ --- 6 unchanged lines hidden (view full) --- 447 return new IllegalInstruction; 448 Rd = Tstate; 449 }}); 450 0x03: Priv::rdprtt({{ 451 if(Tl == 0) 452 return new IllegalInstruction; 453 Rd = Tt; 454 }}); | 443 } 444 0x2A: decode RS1 { 445 0x00: Priv::rdprtpc({{ 446 if(Tl == 0) 447 return new IllegalInstruction; 448 Rd = Tpc; 449 }}); 450 0x01: Priv::rdprtnpc({{ --- 6 unchanged lines hidden (view full) --- 457 return new IllegalInstruction; 458 Rd = Tstate; 459 }}); 460 0x03: Priv::rdprtt({{ 461 if(Tl == 0) 462 return new IllegalInstruction; 463 Rd = Tt; 464 }}); |
455 0x04: Priv::rdprtick({{Rd = Tick;}}); | 465 0x04: Priv::rdprtick({{ 466 Rd = xc->readMiscRegWithEffect(MISCREG_TICK); 467 }}); |
456 0x05: Priv::rdprtba({{Rd = Tba;}}); 457 0x06: Priv::rdprpstate({{Rd = Pstate;}}); 458 0x07: Priv::rdprtl({{Rd = Tl;}}); 459 0x08: Priv::rdprpil({{Rd = Pil;}}); 460 0x09: Priv::rdprcwp({{Rd = Cwp;}}); 461 0x0A: Priv::rdprcansave({{Rd = Cansave;}}); 462 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}}); 463 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}}); --- 73 unchanged lines hidden (view full) --- 537 0x13: NoPriv::wrgsr({{ 538 if(Fprs<2:> == 0 || Pstate<4:> == 0) 539 return new FpDisabled; 540 Gsr = Rs1 ^ Rs2_or_imm13; 541 }}); 542 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}}); 543 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}}); 544 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}}); | 468 0x05: Priv::rdprtba({{Rd = Tba;}}); 469 0x06: Priv::rdprpstate({{Rd = Pstate;}}); 470 0x07: Priv::rdprtl({{Rd = Tl;}}); 471 0x08: Priv::rdprpil({{Rd = Pil;}}); 472 0x09: Priv::rdprcwp({{Rd = Cwp;}}); 473 0x0A: Priv::rdprcansave({{Rd = Cansave;}}); 474 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}}); 475 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}}); --- 73 unchanged lines hidden (view full) --- 549 0x13: NoPriv::wrgsr({{ 550 if(Fprs<2:> == 0 || Pstate<4:> == 0) 551 return new FpDisabled; 552 Gsr = Rs1 ^ Rs2_or_imm13; 553 }}); 554 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}}); 555 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}}); 556 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}}); |
545 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}}); | 557 0x17: Priv::wrtick_cmpr({{ 558 xc->setMiscRegWithEffect(MISCREG_TICK_CMPR, Rs1 ^ Rs2_or_imm13); 559 }}); |
546 0x18: NoPriv::wrstick({{ 547 if(!Hpstate<2:>) 548 return new IllegalInstruction; | 560 0x18: NoPriv::wrstick({{ 561 if(!Hpstate<2:>) 562 return new IllegalInstruction; |
549 Stick = Rs1 ^ Rs2_or_imm13; | 563 xc->setMiscRegWithEffect(MISCREG_STICK, Rs1 ^ Rs2_or_imm13); |
550 }}); | 564 }}); |
551 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}}); | 565 0x19: Priv::wrstick_cmpr({{ 566 xc->setMiscRegWithEffect(MISCREG_STICK_CMPR, Rs1 ^ Rs2_or_imm13); 567 }}); |
552 0x1A: Priv::wrstrand_sts_reg({{ 553 if(Pstate<2:> && !Hpstate<2:>) 554 StrandStsReg = StrandStsReg<63:1> | 555 (Rs1 ^ Rs2_or_imm13)<0:>; 556 else 557 StrandStsReg = Rs1 ^ Rs2_or_imm13; 558 }}); 559 //0x1A is supposed to be reserved, but it writes the strand --- 40 unchanged lines hidden (view full) --- 600 Tstate = Rs1 ^ Rs2_or_imm13; 601 }}); 602 0x03: Priv::wrprtt({{ 603 if(Tl == 0) 604 return new IllegalInstruction; 605 else 606 Tt = Rs1 ^ Rs2_or_imm13; 607 }}); | 568 0x1A: Priv::wrstrand_sts_reg({{ 569 if(Pstate<2:> && !Hpstate<2:>) 570 StrandStsReg = StrandStsReg<63:1> | 571 (Rs1 ^ Rs2_or_imm13)<0:>; 572 else 573 StrandStsReg = Rs1 ^ Rs2_or_imm13; 574 }}); 575 //0x1A is supposed to be reserved, but it writes the strand --- 40 unchanged lines hidden (view full) --- 616 Tstate = Rs1 ^ Rs2_or_imm13; 617 }}); 618 0x03: Priv::wrprtt({{ 619 if(Tl == 0) 620 return new IllegalInstruction; 621 else 622 Tt = Rs1 ^ Rs2_or_imm13; 623 }}); |
608 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); | 624 0x04: HPriv::wrprtick({{ 625 xc->setMiscRegWithEffect(MISCREG_TICK, Rs1 ^ Rs2_or_imm13); 626 }}); |
609 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 610 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 611 0x07: Priv::wrprtl({{ 612 if(Pstate<2:> && !Hpstate<2:>) 613 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL); 614 else 615 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL); 616 }}); --- 20 unchanged lines hidden (view full) --- 637 return new IllegalInstruction; 638 Htstate = Rs1 ^ Rs2_or_imm13; 639 }}); 640 //0x02 should cause an illegal instruction exception 641 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}}); 642 //0x04 should cause an illegal instruction exception 643 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); 644 //0x06-0x01D should cause an illegal instruction exception | 627 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 628 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 629 0x07: Priv::wrprtl({{ 630 if(Pstate<2:> && !Hpstate<2:>) 631 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL); 632 else 633 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL); 634 }}); --- 20 unchanged lines hidden (view full) --- 655 return new IllegalInstruction; 656 Htstate = Rs1 ^ Rs2_or_imm13; 657 }}); 658 //0x02 should cause an illegal instruction exception 659 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}}); 660 //0x04 should cause an illegal instruction exception 661 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); 662 //0x06-0x01D should cause an illegal instruction exception |
645 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}}); | 663 0x1F: HPriv::wrhprhstick_cmpr({{ 664 xc->setMiscRegWithEffect(MISCREG_HSTICK_CMPR, Rs1 ^ Rs2_or_imm13); 665 }}); |
646 } 647 0x34: decode OPF{ 648 format BasicOperate{ 649 0x01: fmovs({{ 650 Frds.uw = Frs2s.uw; 651 //fsr.ftt = fsr.cexc = 0 652 Fsr &= ~(7 << 14); 653 Fsr &= ~(0x1F); --- 395 unchanged lines hidden (view full) --- 1049 0x0D: LoadStore::ldstub( 1050 {{Rd = Mem.ub;}}, 1051 {{Mem.ub = 0xFF;}}); 1052 0x0E: Store::stx({{Mem.udw = Rd}}); 1053 0x0F: LoadStore::swap( 1054 {{uReg0 = Rd.uw; 1055 Rd.uw = Mem.uw;}}, 1056 {{Mem.uw = uReg0;}}); | 666 } 667 0x34: decode OPF{ 668 format BasicOperate{ 669 0x01: fmovs({{ 670 Frds.uw = Frs2s.uw; 671 //fsr.ftt = fsr.cexc = 0 672 Fsr &= ~(7 << 14); 673 Fsr &= ~(0x1F); --- 395 unchanged lines hidden (view full) --- 1069 0x0D: LoadStore::ldstub( 1070 {{Rd = Mem.ub;}}, 1071 {{Mem.ub = 0xFF;}}); 1072 0x0E: Store::stx({{Mem.udw = Rd}}); 1073 0x0F: LoadStore::swap( 1074 {{uReg0 = Rd.uw; 1075 Rd.uw = Mem.uw;}}, 1076 {{Mem.uw = uReg0;}}); |
1057 format LoadAlt { 1058 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}}); 1059 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}}); 1060 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}}); | 1077 format Load { 1078 0x10: lduwa({{Rd = Mem.uw;}}); 1079 0x11: lduba({{Rd = Mem.ub;}}); 1080 0x12: lduha({{Rd = Mem.uhw;}}); |
1061 0x13: ldda({{ 1062 uint64_t val = Mem.udw; 1063 RdLow = val<31:0>; 1064 RdHigh = val<63:32>; | 1081 0x13: ldda({{ 1082 uint64_t val = Mem.udw; 1083 RdLow = val<31:0>; 1084 RdHigh = val<63:32>; |
1065 }}, {{EXT_ASI}}); | 1085 }}); |
1066 } | 1086 } |
1067 format StoreAlt { 1068 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}}); 1069 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}}); 1070 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}}); 1071 0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}}); | 1087 format Store { 1088 0x14: stwa({{Mem.uw = Rd;}}); 1089 0x15: stba({{Mem.ub = Rd;}}); 1090 0x16: stha({{Mem.uhw = Rd;}}); 1091 0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}); |
1072 } | 1092 } |
1073 format LoadAlt { 1074 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}}); 1075 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}}); 1076 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}}); 1077 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}}); | 1093 format Load { 1094 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}); 1095 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}); 1096 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}); 1097 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}); |
1078 } | 1098 } |
1079 0x1D: LoadStoreAlt::ldstuba( | 1099 0x1D: LoadStore::ldstuba( |
1080 {{Rd = Mem.ub;}}, | 1100 {{Rd = Mem.ub;}}, |
1081 {{Mem.ub = 0xFF}}, {{EXT_ASI}}); 1082 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}}); 1083 0x1F: LoadStoreAlt::swapa( | 1101 {{Mem.ub = 0xFF}}); 1102 0x1E: Store::stxa({{Mem.udw = Rd}}); 1103 0x1F: LoadStore::swapa( |
1084 {{uReg0 = Rd.uw; 1085 Rd.uw = Mem.uw;}}, | 1104 {{uReg0 = Rd.uw; 1105 Rd.uw = Mem.uw;}}, |
1086 {{Mem.uw = uReg0;}}, {{EXT_ASI}}); | 1106 {{Mem.uw = uReg0;}}); |
1087 format Trap { 1088 0x20: Load::ldf({{Frd.uw = Mem.uw;}}); 1089 0x21: decode X { 1090 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}}); 1091 0x1: Load::ldxfsr({{Fsr = Mem.udw;}}); 1092 } 1093 0x22: ldqf({{fault = new FpDisabled;}}); 1094 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 1095 0x24: Store::stf({{Mem.uw = Frd.uw;}}); 1096 0x25: decode X { 1097 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}}); 1098 0x1: Store::stxfsr({{Mem.udw = Fsr;}}); 1099 } 1100 0x26: stqf({{fault = new FpDisabled;}}); 1101 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 1102 0x2D: Nop::prefetch({{ }}); | 1107 format Trap { 1108 0x20: Load::ldf({{Frd.uw = Mem.uw;}}); 1109 0x21: decode X { 1110 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}}); 1111 0x1: Load::ldxfsr({{Fsr = Mem.udw;}}); 1112 } 1113 0x22: ldqf({{fault = new FpDisabled;}}); 1114 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 1115 0x24: Store::stf({{Mem.uw = Frd.uw;}}); 1116 0x25: decode X { 1117 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}}); 1118 0x1: Store::stxfsr({{Mem.udw = Fsr;}}); 1119 } 1120 0x26: stqf({{fault = new FpDisabled;}}); 1121 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 1122 0x2D: Nop::prefetch({{ }}); |
1103 0x30: LoadAlt::ldfa({{Frd.uw = Mem.uw;}}, {{EXT_ASI}}); | 1123 0x30: Load::ldfa({{Frd.uw = Mem.uw;}}); |
1104 0x32: ldqfa({{fault = new FpDisabled;}}); 1105 format LoadAlt { 1106 0x33: decode EXT_ASI { 1107 //ASI_NUCLEUS 1108 0x04: FailUnimpl::lddfa_n(); 1109 //ASI_NUCLEUS_LITTLE 1110 0x0C: FailUnimpl::lddfa_nl(); 1111 //ASI_AS_IF_USER_PRIMARY --- 35 unchanged lines hidden (view full) --- 1147 0x16: FailUnimpl::ldblockf_aiup(); 1148 //ASI_BLOCK_AS_IF_USER_SECONDARY 1149 0x17: FailUnimpl::ldblockf_aius(); 1150 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1151 0x1E: FailUnimpl::ldblockf_aiupl(); 1152 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1153 0x1F: FailUnimpl::ldblockf_aiusl(); 1154 //ASI_BLOCK_PRIMARY | 1124 0x32: ldqfa({{fault = new FpDisabled;}}); 1125 format LoadAlt { 1126 0x33: decode EXT_ASI { 1127 //ASI_NUCLEUS 1128 0x04: FailUnimpl::lddfa_n(); 1129 //ASI_NUCLEUS_LITTLE 1130 0x0C: FailUnimpl::lddfa_nl(); 1131 //ASI_AS_IF_USER_PRIMARY --- 35 unchanged lines hidden (view full) --- 1167 0x16: FailUnimpl::ldblockf_aiup(); 1168 //ASI_BLOCK_AS_IF_USER_SECONDARY 1169 0x17: FailUnimpl::ldblockf_aius(); 1170 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1171 0x1E: FailUnimpl::ldblockf_aiupl(); 1172 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1173 0x1F: FailUnimpl::ldblockf_aiusl(); 1174 //ASI_BLOCK_PRIMARY |
1155 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}}); | 1175 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}); |
1156 //ASI_BLOCK_SECONDARY 1157 0xF1: FailUnimpl::ldblockf_s(); 1158 //ASI_BLOCK_PRIMARY_LITTLE 1159 0xF8: FailUnimpl::ldblockf_pl(); 1160 //ASI_BLOCK_SECONDARY_LITTLE 1161 0xF9: FailUnimpl::ldblockf_sl(); 1162 } 1163 --- 66 unchanged lines hidden (view full) --- 1230 0x16: FailUnimpl::stblockf_aiup(); 1231 //ASI_BLOCK_AS_IF_USER_SECONDARY 1232 0x17: FailUnimpl::stblockf_aius(); 1233 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1234 0x1E: FailUnimpl::stblockf_aiupl(); 1235 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1236 0x1F: FailUnimpl::stblockf_aiusl(); 1237 //ASI_BLOCK_PRIMARY | 1176 //ASI_BLOCK_SECONDARY 1177 0xF1: FailUnimpl::ldblockf_s(); 1178 //ASI_BLOCK_PRIMARY_LITTLE 1179 0xF8: FailUnimpl::ldblockf_pl(); 1180 //ASI_BLOCK_SECONDARY_LITTLE 1181 0xF9: FailUnimpl::ldblockf_sl(); 1182 } 1183 --- 66 unchanged lines hidden (view full) --- 1250 0x16: FailUnimpl::stblockf_aiup(); 1251 //ASI_BLOCK_AS_IF_USER_SECONDARY 1252 0x17: FailUnimpl::stblockf_aius(); 1253 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1254 0x1E: FailUnimpl::stblockf_aiupl(); 1255 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1256 0x1F: FailUnimpl::stblockf_aiusl(); 1257 //ASI_BLOCK_PRIMARY |
1238 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}}); | 1258 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}); |
1239 //ASI_BLOCK_SECONDARY 1240 0xF1: FailUnimpl::stblockf_s(); 1241 //ASI_BLOCK_PRIMARY_LITTLE 1242 0xF8: FailUnimpl::stblockf_pl(); 1243 //ASI_BLOCK_SECONDARY_LITTLE 1244 0xF9: FailUnimpl::stblockf_sl(); 1245 } 1246 --- 20 unchanged lines hidden (view full) --- 1267 } 1268 } 1269 0x3C: Cas::casa( 1270 {{uReg0 = Mem.uw;}}, 1271 {{if(Rs2.uw == uReg0) 1272 Mem.uw = Rd.uw; 1273 else 1274 storeCond = false; | 1259 //ASI_BLOCK_SECONDARY 1260 0xF1: FailUnimpl::stblockf_s(); 1261 //ASI_BLOCK_PRIMARY_LITTLE 1262 0xF8: FailUnimpl::stblockf_pl(); 1263 //ASI_BLOCK_SECONDARY_LITTLE 1264 0xF9: FailUnimpl::stblockf_sl(); 1265 } 1266 --- 20 unchanged lines hidden (view full) --- 1287 } 1288 } 1289 0x3C: Cas::casa( 1290 {{uReg0 = Mem.uw;}}, 1291 {{if(Rs2.uw == uReg0) 1292 Mem.uw = Rd.uw; 1293 else 1294 storeCond = false; |
1275 Rd.uw = uReg0;}}, {{EXT_ASI}}); | 1295 Rd.uw = uReg0;}}); |
1276 0x3D: Nop::prefetcha({{ }}); 1277 0x3E: Cas::casxa( 1278 {{uReg0 = Mem.udw;}}, 1279 {{if(Rs2 == uReg0) 1280 Mem.udw = Rd; 1281 else 1282 storeCond = false; | 1296 0x3D: Nop::prefetcha({{ }}); 1297 0x3E: Cas::casxa( 1298 {{uReg0 = Mem.udw;}}, 1299 {{if(Rs2 == uReg0) 1300 Mem.udw = Rd; 1301 else 1302 storeCond = false; |
1283 Rd = uReg0;}}, {{EXT_ASI}}); | 1303 Rd = uReg0;}}); |
1284 } 1285 } 1286} | 1304 } 1305 } 1306} |