decoder.isa (3427:b217e3aa3018) decoder.isa (3438:d625052ff893)
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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846 0x06: sth({{Mem.uhw = Rd.shw;}});
847 0x07: std({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
848 }
849 format Load {
850 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
851 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
852 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
853 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 837 unchanged lines hidden (view full) ---

846 0x06: sth({{Mem.uhw = Rd.shw;}});
847 0x07: std({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
848 }
849 format Load {
850 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
851 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
852 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
853 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
854 0x0D: ldstub({{
855 Rd = Mem.ub;
856 Mem.ub = 0xFF;
857 }});
858 }
854 }
855 0x0D: LoadStore::ldstub(
856 {{Rd = Mem.ub;}},
857 {{Mem.ub = 0xFF;}});
859 0x0E: Store::stx({{Mem.udw = Rd}});
860 0x0F: LoadStore::swap(
858 0x0E: Store::stx({{Mem.udw = Rd}});
859 0x0F: LoadStore::swap(
861 {{*temp = Rd.uw;
860 {{uReg0 = Rd.uw;
862 Rd.uw = Mem.uw;}},
861 Rd.uw = Mem.uw;}},
863 {{Mem.uw = *temp;}});
862 {{Mem.uw = uReg0;}});
864 format Load {
865 0x10: lduwa({{Rd = Mem.uw;}});
866 0x11: lduba({{Rd = Mem.ub;}});
867 0x12: lduha({{Rd = Mem.uhw;}});
868 0x13: ldda({{
869 uint64_t val = Mem.udw;
870 RdLow = val<31:0>;
871 RdHigh = val<63:32>;

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883 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}});
884 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}});
885 }
886 0x1D: LoadStore::ldstuba(
887 {{Rd = Mem.ub;}},
888 {{Mem.ub = 0xFF}});
889 0x1E: Store::stxa({{Mem.udw = Rd}});
890 0x1F: LoadStore::swapa(
863 format Load {
864 0x10: lduwa({{Rd = Mem.uw;}});
865 0x11: lduba({{Rd = Mem.ub;}});
866 0x12: lduha({{Rd = Mem.uhw;}});
867 0x13: ldda({{
868 uint64_t val = Mem.udw;
869 RdLow = val<31:0>;
870 RdHigh = val<63:32>;

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882 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}});
883 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}});
884 }
885 0x1D: LoadStore::ldstuba(
886 {{Rd = Mem.ub;}},
887 {{Mem.ub = 0xFF}});
888 0x1E: Store::stxa({{Mem.udw = Rd}});
889 0x1F: LoadStore::swapa(
891 {{*temp = Rd.uw;
890 {{uReg0 = Rd.uw;
892 Rd.uw = Mem.uw;}},
891 Rd.uw = Mem.uw;}},
893 {{Mem.uw = *temp;}});
892 {{Mem.uw = uReg0;}});
894 format Trap {
895 0x20: Load::ldf({{Frd.uw = Mem.uw;}});
896 0x21: decode X {
897 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}});
898 0x1: Load::ldxfsr({{Fsr = Mem.udw;}});
899 }
900 0x22: ldqf({{fault = new FpDisabled;}});
901 0x23: Load::lddf({{Frd.udw = Mem.udw;}});

--- 190 unchanged lines hidden --- 		893 format Trap {
894 0x20: Load::ldf({{Frd.uw = Mem.uw;}});
895 0x21: decode X {
896 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}});
897 0x1: Load::ldxfsr({{Fsr = Mem.udw;}});
898 }
899 0x22: ldqf({{fault = new FpDisabled;}});
900 0x23: Load::lddf({{Frd.udw = Mem.udw;}});

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