decoder.isa (3057:60d4eb3843f7) decoder.isa (3272:c28038eaefb8)
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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815 NNPC = Tnpc + 4;
816 Tl = Tl - 1;
817 }});
818 }
819 }
820 }
821 0x3: decode OP3 {
822 format Load {
1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 806 unchanged lines hidden (view full) ---

815 NNPC = Tnpc + 4;
816 Tl = Tl - 1;
817 }});
818 }
819 }
820 }
821 0x3: decode OP3 {
822 format Load {
823 0x00: lduw({{Rd = Mem;}}, {{32}});
824 0x01: ldub({{Rd = Mem;}}, {{8}});
825 0x02: lduh({{Rd = Mem;}}, {{16}});
823 0x00: lduw({{Rd = Mem.uw;}});
824 0x01: ldub({{Rd = Mem.ub;}});
825 0x02: lduh({{Rd = Mem.uhw;}});
826 0x03: ldd({{
826 0x03: ldd({{
827 uint64_t val = Mem;
827 uint64_t val = Mem.udw;
828 RdLow = val<31:0>;
829 RdHigh = val<63:32>;
828 RdLow = val<31:0>;
829 RdHigh = val<63:32>;
830 }}, {{64}});
830 }});
831 }
832 format Store {
831 }
832 format Store {
833 0x04: stw({{Mem = Rd.sw;}}, {{32}});
834 0x05: stb({{Mem = Rd.sb;}}, {{8}});
835 0x06: sth({{Mem = Rd.shw;}}, {{16}});
836 0x07: std({{Mem = RdLow<31:0> | (RdHigh<31:0> << 32);}}, {{64}});
833 0x04: stw({{Mem.uw = Rd.sw;}});
834 0x05: stb({{Mem.ub = Rd.sb;}});
835 0x06: sth({{Mem.uhw = Rd.shw;}});
836 0x07: std({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
837 }
838 format Load {
837 }
838 format Load {
839 0x08: ldsw({{Rd = (int32_t)Mem;}}, {{32}});
840 0x09: ldsb({{Rd = (int8_t)Mem;}}, {{8}});
841 0x0A: ldsh({{Rd = (int16_t)Mem;}}, {{16}});
842 0x0B: ldx({{Rd = (int64_t)Mem;}}, {{64}});
839 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
840 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
841 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
842 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
843 0x0D: ldstub({{
843 0x0D: ldstub({{
844 Rd = Mem;
845 Mem = 0xFF;
846 }}, {{8}});
844 Rd = Mem.ub;
845 Mem.ub = 0xFF;
846 }});
847 }
847 }
848 0x0E: Store::stx({{Mem = Rd}}, {{64}});
848 0x0E: Store::stx({{Mem.udw = Rd}});
849 0x0F: LoadStore::swap({{
850 uint32_t temp = Rd;
849 0x0F: LoadStore::swap({{
850 uint32_t temp = Rd;
851 Rd = Mem;
852 Mem = temp;
853 }}, {{32}});
851 Rd = Mem.uw;
852 Mem.uw = temp;
853 }});
854 format Load {
854 format Load {
855 0x10: lduwa({{Rd = Mem;}}, {{32}});
856 0x11: lduba({{Rd = Mem;}}, {{8}});
857 0x12: lduha({{Rd = Mem;}}, {{16}});
855 0x10: lduwa({{Rd = Mem.uw;}});
856 0x11: lduba({{Rd = Mem.ub;}});
857 0x12: lduha({{Rd = Mem.uhw;}});
858 0x13: ldda({{
858 0x13: ldda({{
859 uint64_t val = Mem;
859 uint64_t val = Mem.udw;
860 RdLow = val<31:0>;
861 RdHigh = val<63:32>;
860 RdLow = val<31:0>;
861 RdHigh = val<63:32>;
862 }}, {{64}});
862 }});
863 }
864 format Store {
863 }
864 format Store {
865 0x14: stwa({{Mem = Rd;}}, {{32}});
866 0x15: stba({{Mem = Rd;}}, {{8}});
867 0x16: stha({{Mem = Rd;}}, {{16}});
868 0x17: stda({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}});
865 0x14: stwa({{Mem.uw = Rd;}});
866 0x15: stba({{Mem.ub = Rd;}});
867 0x16: stha({{Mem.uhw = Rd;}});
868 0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}});
869 }
870 format Load {
869 }
870 format Load {
871 0x18: ldswa({{Rd = (int32_t)Mem;}}, {{32}});
872 0x19: ldsba({{Rd = (int8_t)Mem;}}, {{8}});
873 0x1A: ldsha({{Rd = (int16_t)Mem;}}, {{16}});
874 0x1B: ldxa({{Rd = (int64_t)Mem;}}, {{64}});
871 0x18: ldswa({{Rd = (int32_t)Mem.sw;}});
872 0x19: ldsba({{Rd = (int8_t)Mem.sb;}});
873 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}});
874 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}});
875 }
876 0x1D: LoadStore::ldstuba({{
875 }
876 0x1D: LoadStore::ldstuba({{
877 Rd = Mem;
878 Mem = 0xFF;
879 }}, {{8}});
880 0x1E: Store::stxa({{Mem = Rd}}, {{64}});
877 Rd = Mem.ub;
878 Mem.ub = 0xFF;
879 }});
880 0x1E: Store::stxa({{Mem.udw = Rd}});
881 0x1F: LoadStore::swapa({{
882 uint32_t temp = Rd;
881 0x1F: LoadStore::swapa({{
882 uint32_t temp = Rd;
883 Rd = Mem;
884 Mem = temp;
885 }}, {{32}});
883 Rd = Mem.uw;
884 Mem.uw = temp;
885 }});
886 format Trap {
886 format Trap {
887 0x20: Load::ldf({{Frd.uw = Mem;}}, {{32}});
887 0x20: Load::ldf({{Frd.uw = Mem.uw;}});
888 0x21: decode X {
888 0x21: decode X {
889 0x0: Load::ldfsr({{Fsr = Mem<31:0> | Fsr<63:32>;}}, {{32}});
890 0x1: Load::ldxfsr({{Fsr = Mem;}}, {{64}});
889 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}});
890 0x1: Load::ldxfsr({{Fsr = Mem.udw;}});
891 }
892 0x22: ldqf({{fault = new FpDisabled;}});
891 }
892 0x22: ldqf({{fault = new FpDisabled;}});
893 0x23: Load::lddf({{Frd.udw = Mem;}}, {{64}});
894 0x24: Store::stf({{Mem = Frd.uw;}}, {{32}});
893 0x23: Load::lddf({{Frd.udw = Mem.udw;}});
894 0x24: Store::stf({{Mem.uw = Frd.uw;}});
895 0x25: decode X {
895 0x25: decode X {
896 0x0: Store::stfsr({{Mem = Fsr<31:0>;}}, {{32}});
897 0x1: Store::stxfsr({{Mem = Fsr;}}, {{64}});
896 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}});
897 0x1: Store::stxfsr({{Mem.udw = Fsr;}});
898 }
899 0x26: stqf({{fault = new FpDisabled;}});
898 }
899 0x26: stqf({{fault = new FpDisabled;}});
900 0x27: Store::stdf({{Mem = Frd.udw;}}, {{64}});
900 0x27: Store::stdf({{Mem.udw = Frd.udw;}});
901 0x2D: Nop::prefetch({{ }});
901 0x2D: Nop::prefetch({{ }});
902 0x30: Load::ldfa({{Frd.uw = Mem;}}, {{32}});
902 0x30: Load::ldfa({{Frd.uw = Mem.uw;}});
903 0x32: ldqfa({{fault = new FpDisabled;}});
903 0x32: ldqfa({{fault = new FpDisabled;}});
904 0x33: Load::lddfa({{Frd.udw = Mem;}}, {{64}});
905 0x34: Store::stfa({{Mem = Frd.uw;}}, {{32}});
904 format LoadAlt {
905 0x33: decode EXT_ASI {
906 //ASI_NUCLEUS
907 0x04: FailUnimpl::lddfa_n();
908 //ASI_NUCLEUS_LITTLE
909 0x0C: FailUnimpl::lddfa_nl();
910 //ASI_AS_IF_USER_PRIMARY
911 0x10: FailUnimpl::lddfa_aiup();
912 //ASI_AS_IF_USER_PRIMARY_LITTLE
913 0x18: FailUnimpl::lddfa_aiupl();
914 //ASI_AS_IF_USER_SECONDARY
915 0x11: FailUnimpl::lddfa_aius();
916 //ASI_AS_IF_USER_SECONDARY_LITTLE
917 0x19: FailUnimpl::lddfa_aiusl();
918 //ASI_REAL
919 0x14: FailUnimpl::lddfa_real();
920 //ASI_REAL_LITTLE
921 0x1C: FailUnimpl::lddfa_real_l();
922 //ASI_REAL_IO
923 0x15: FailUnimpl::lddfa_real_io();
924 //ASI_REAL_IO_LITTLE
925 0x1D: FailUnimpl::lddfa_real_io_l();
926 //ASI_PRIMARY
927 0x80: FailUnimpl::lddfa_p();
928 //ASI_PRIMARY_LITTLE
929 0x88: FailUnimpl::lddfa_pl();
930 //ASI_SECONDARY
931 0x81: FailUnimpl::lddfa_s();
932 //ASI_SECONDARY_LITTLE
933 0x89: FailUnimpl::lddfa_sl();
934 //ASI_PRIMARY_NO_FAULT
935 0x82: FailUnimpl::lddfa_pnf();
936 //ASI_PRIMARY_NO_FAULT_LITTLE
937 0x8A: FailUnimpl::lddfa_pnfl();
938 //ASI_SECONDARY_NO_FAULT
939 0x83: FailUnimpl::lddfa_snf();
940 //ASI_SECONDARY_NO_FAULT_LITTLE
941 0x8B: FailUnimpl::lddfa_snfl();
942
943 format BlockLoad {
944 // LDBLOCKF
945 //ASI_BLOCK_AS_IF_USER_PRIMARY
946 0x16: FailUnimpl::ldblockf_aiup();
947 //ASI_BLOCK_AS_IF_USER_SECONDARY
948 0x17: FailUnimpl::ldblockf_aius();
949 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
950 0x1E: FailUnimpl::ldblockf_aiupl();
951 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
952 0x1F: FailUnimpl::ldblockf_aiusl();
953 //ASI_BLOCK_PRIMARY
954 0xF0: ldblockf_p({{Frd_%(micro_pc)d = Mem.udw}});
955 //ASI_BLOCK_SECONDARY
956 0xF1: FailUnimpl::ldblockf_s();
957 //ASI_BLOCK_PRIMARY_LITTLE
958 0xF8: FailUnimpl::ldblockf_pl();
959 //ASI_BLOCK_SECONDARY_LITTLE
960 0xF9: FailUnimpl::ldblockf_sl();
961 }
962
963 //LDSHORTF
964 //ASI_FL8_PRIMARY
965 0xD0: FailUnimpl::ldshortf_8p();
966 //ASI_FL8_SECONDARY
967 0xD1: FailUnimpl::ldshortf_8s();
968 //ASI_FL8_PRIMARY_LITTLE
969 0xD8: FailUnimpl::ldshortf_8pl();
970 //ASI_FL8_SECONDARY_LITTLE
971 0xD9: FailUnimpl::ldshortf_8sl();
972 //ASI_FL16_PRIMARY
973 0xD2: FailUnimpl::ldshortf_16p();
974 //ASI_FL16_SECONDARY
975 0xD3: FailUnimpl::ldshortf_16s();
976 //ASI_FL16_PRIMARY_LITTLE
977 0xDA: FailUnimpl::ldshortf_16pl();
978 //ASI_FL16_SECONDARY_LITTLE
979 0xDB: FailUnimpl::ldshortf_16sl();
980 //Not an ASI which is legal with lddfa
981 default: Trap::lddfa_bad_asi({{fault = new DataAccessException;}});
982
983 //LoadAlt::lddfa({{
984 //Do the actual loading
985 //if(fault == NoFault)
986 //{
987 //if(AsiIsBlock(asi))
988 //{
989 //Do the block transfer
990 //}
991 //else
992 //{
993 //uint64_t val = Mem;
994 //if(AsiIsLittle(asi))
995 //val = gtole(val);
996 //Frd.udw = val;
997 //}
998 //}
999 //}}, {{64}});*/
1000 }
1001 }
1002 0x34: Store::stfa({{Mem.uw = Frd.uw;}});
906 0x36: stqfa({{fault = new FpDisabled;}});
907 //XXX need to work in the ASI thing
1003 0x36: stqfa({{fault = new FpDisabled;}});
1004 //XXX need to work in the ASI thing
908 0x37: Store::stdfa({{Mem = Frd.udw;}}, {{64}});
1005 0x37: Store::stdfa({{Mem.udw = Frd.udw;}});
909 0x3C: Cas::casa({{
910 uint64_t val = Mem.uw;
911 if(Rs2.uw == val)
912 Mem.uw = Rd.uw;
913 Rd.uw = val;
914 }});
915 0x3D: Nop::prefetcha({{ }});
916 0x3E: Cas::casxa({{
917 uint64_t val = Mem.udw;
918 if(Rs2 == val)
919 Mem.udw = Rd;
920 Rd = val;
921 }});
922 }
923 }
924}
1006 0x3C: Cas::casa({{
1007 uint64_t val = Mem.uw;
1008 if(Rs2.uw == val)
1009 Mem.uw = Rd.uw;
1010 Rd.uw = val;
1011 }});
1012 0x3D: Nop::prefetcha({{ }});
1013 0x3E: Cas::casxa({{
1014 uint64_t val = Mem.udw;
1015 if(Rs2 == val)
1016 Mem.udw = Rd;
1017 Rd = val;
1018 }});
1019 }
1020 }
1021}