decoder.isa (12289:abb573c4e7ed) decoder.isa (12386:2bf5fb25a5f1)
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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1097 }
1098 }
1099 0x3: decode OP3 {
1100 format Load {
1101 0x00: lduw({{Rd = Mem_uw;}});
1102 0x01: ldub({{Rd = Mem_ub;}});
1103 0x02: lduh({{Rd = Mem_uhw;}});
1104 0x03: ldtw({{
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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1097 }
1098 }
1099 0x3: decode OP3 {
1100 format Load {
1101 0x00: lduw({{Rd = Mem_uw;}});
1102 0x01: ldub({{Rd = Mem_ub;}});
1103 0x02: lduh({{Rd = Mem_uhw;}});
1104 0x03: ldtw({{
1105 RdLow = (Mem_tuw).a;
1106 RdHigh = (Mem_tuw).b;
1105 RdLow = Mem_tuw[0];
1106 RdHigh = Mem_tuw[1];
1107 }});
1108 }
1109 format Store {
1110 0x04: stw({{Mem_uw = Rd_sw;}});
1111 0x05: stb({{Mem_ub = Rd_sb;}});
1112 0x06: sth({{Mem_uhw = Rd_shw;}});
1113 0x07: sttw({{
1114 // This temporary needs to be here so that the parser
1115 // will correctly identify this instruction as a store.
1116 // It's probably either the parenthesis or referencing
1117 // the member variable that throws confuses it.
1107 }});
1108 }
1109 format Store {
1110 0x04: stw({{Mem_uw = Rd_sw;}});
1111 0x05: stb({{Mem_ub = Rd_sb;}});
1112 0x06: sth({{Mem_uhw = Rd_shw;}});
1113 0x07: sttw({{
1114 // This temporary needs to be here so that the parser
1115 // will correctly identify this instruction as a store.
1116 // It's probably either the parenthesis or referencing
1117 // the member variable that throws confuses it.
1118 Twin32_t temp;
1119 temp.a = RdLow<31:0>;
1120 temp.b = RdHigh<31:0>;
1118 std::array<uint32_t, 2> temp;
1119 temp[0] = RdLow<31:0>;
1120 temp[1] = RdHigh<31:0>;
1121 Mem_tuw = temp;
1122 }});
1123 }
1124 format Load {
1125 0x08: ldsw({{Rd = Mem_sw;}});
1126 0x09: ldsb({{Rd = Mem_sb;}});
1127 0x0A: ldsh({{Rd = Mem_shw;}});
1128 0x0B: ldx({{Rd = Mem_sdw;}});

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1140 }}, MEM_SWAP);
1141 format LoadAlt {
1142 0x10: lduwa({{Rd = Mem_uw;}});
1143 0x11: lduba({{Rd = Mem_ub;}});
1144 0x12: lduha({{Rd = Mem_uhw;}});
1145 0x13: decode EXT_ASI {
1146 // ASI_LDTD_AIUP
1147 0x22: TwinLoad::ldtx_aiup(
1121 Mem_tuw = temp;
1122 }});
1123 }
1124 format Load {
1125 0x08: ldsw({{Rd = Mem_sw;}});
1126 0x09: ldsb({{Rd = Mem_sb;}});
1127 0x0A: ldsh({{Rd = Mem_shw;}});
1128 0x0B: ldx({{Rd = Mem_sdw;}});

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1140 }}, MEM_SWAP);
1141 format LoadAlt {
1142 0x10: lduwa({{Rd = Mem_uw;}});
1143 0x11: lduba({{Rd = Mem_ub;}});
1144 0x12: lduha({{Rd = Mem_uhw;}});
1145 0x13: decode EXT_ASI {
1146 // ASI_LDTD_AIUP
1147 0x22: TwinLoad::ldtx_aiup(
1148 {{RdLow_udw = (Mem_tudw).a;
1149 RdHigh_udw = (Mem_tudw).b;}});
1148 {{RdLow_udw = Mem_tudw[0];
1149 RdHigh_udw = Mem_tudw[1];}});
1150 // ASI_LDTD_AIUS
1151 0x23: TwinLoad::ldtx_aius(
1150 // ASI_LDTD_AIUS
1151 0x23: TwinLoad::ldtx_aius(
1152 {{RdLow_udw = (Mem_tudw).a;
1153 RdHigh_udw = (Mem_tudw).b;}});
1152 {{RdLow_udw = Mem_tudw[0];
1153 RdHigh_udw = Mem_tudw[1];}});
1154 // ASI_QUAD_LDD
1155 0x24: TwinLoad::ldtx_quad_ldd(
1154 // ASI_QUAD_LDD
1155 0x24: TwinLoad::ldtx_quad_ldd(
1156 {{RdLow_udw = (Mem_tudw).a;
1157 RdHigh_udw = (Mem_tudw).b;}});
1156 {{RdLow_udw = Mem_tudw[0];
1157 RdHigh_udw = Mem_tudw[1];}});
1158 // ASI_LDTX_REAL
1159 0x26: TwinLoad::ldtx_real(
1158 // ASI_LDTX_REAL
1159 0x26: TwinLoad::ldtx_real(
1160 {{RdLow_udw = (Mem_tudw).a;
1161 RdHigh_udw = (Mem_tudw).b;}});
1160 {{RdLow_udw = Mem_tudw[0];
1161 RdHigh_udw = Mem_tudw[1];}});
1162 // ASI_LDTX_N
1163 0x27: TwinLoad::ldtx_n(
1162 // ASI_LDTX_N
1163 0x27: TwinLoad::ldtx_n(
1164 {{RdLow_udw = (Mem_tudw).a;
1165 RdHigh_udw = (Mem_tudw).b;}});
1164 {{RdLow_udw = Mem_tudw[0];
1165 RdHigh_udw = Mem_tudw[1];}});
1166 // ASI_LDTX_AIUP_L
1167 0x2A: TwinLoad::ldtx_aiup_l(
1166 // ASI_LDTX_AIUP_L
1167 0x2A: TwinLoad::ldtx_aiup_l(
1168 {{RdLow_udw = (Mem_tudw).a;
1169 RdHigh_udw = (Mem_tudw).b;}});
1168 {{RdLow_udw = Mem_tudw[0];
1169 RdHigh_udw = Mem_tudw[1];}});
1170 // ASI_LDTX_AIUS_L
1171 0x2B: TwinLoad::ldtx_aius_l(
1170 // ASI_LDTX_AIUS_L
1171 0x2B: TwinLoad::ldtx_aius_l(
1172 {{RdLow_udw = (Mem_tudw).a;
1173 RdHigh_udw = (Mem_tudw).b;}});
1172 {{RdLow_udw = Mem_tudw[0];
1173 RdHigh_udw = Mem_tudw[1];}});
1174 // ASI_LDTX_L
1175 0x2C: TwinLoad::ldtx_l(
1174 // ASI_LDTX_L
1175 0x2C: TwinLoad::ldtx_l(
1176 {{RdLow_udw = (Mem_tudw).a;
1177 RdHigh_udw = (Mem_tudw).b;}});
1176 {{RdLow_udw = Mem_tudw[0];
1177 RdHigh_udw = Mem_tudw[1];}});
1178 // ASI_LDTX_REAL_L
1179 0x2E: TwinLoad::ldtx_real_l(
1178 // ASI_LDTX_REAL_L
1179 0x2E: TwinLoad::ldtx_real_l(
1180 {{RdLow_udw = (Mem_tudw).a;
1181 RdHigh_udw = (Mem_tudw).b;}});
1180 {{RdLow_udw = Mem_tudw[0];
1181 RdHigh_udw = Mem_tudw[1];}});
1182 // ASI_LDTX_N_L
1183 0x2F: TwinLoad::ldtx_n_l(
1182 // ASI_LDTX_N_L
1183 0x2F: TwinLoad::ldtx_n_l(
1184 {{RdLow_udw = (Mem_tudw).a;
1185 RdHigh_udw = (Mem_tudw).b;}});
1184 {{RdLow_udw = Mem_tudw[0];
1185 RdHigh_udw = Mem_tudw[1];}});
1186 // ASI_LDTX_P
1187 0xE2: TwinLoad::ldtx_p(
1186 // ASI_LDTX_P
1187 0xE2: TwinLoad::ldtx_p(
1188 {{RdLow_udw = (Mem_tudw).a;
1189 RdHigh_udw = (Mem_tudw).b;}});
1188 {{RdLow_udw = Mem_tudw[0];
1189 RdHigh_udw = Mem_tudw[1];}});
1190 // ASI_LDTX_S
1191 0xE3: TwinLoad::ldtx_s(
1190 // ASI_LDTX_S
1191 0xE3: TwinLoad::ldtx_s(
1192 {{RdLow_udw = (Mem_tudw).a;
1193 RdHigh_udw = (Mem_tudw).b;}});
1192 {{RdLow_udw = Mem_tudw[0];
1193 RdHigh_udw = Mem_tudw[1];}});
1194 // ASI_LDTX_PL
1195 0xEA: TwinLoad::ldtx_pl(
1194 // ASI_LDTX_PL
1195 0xEA: TwinLoad::ldtx_pl(
1196 {{RdLow_udw = (Mem_tudw).a;
1197 RdHigh_udw = (Mem_tudw).b;}});
1196 {{RdLow_udw = Mem_tudw[0];
1197 RdHigh_udw = Mem_tudw[1];}});
1198 // ASI_LDTX_SL
1199 0xEB: TwinLoad::ldtx_sl(
1198 // ASI_LDTX_SL
1199 0xEB: TwinLoad::ldtx_sl(
1200 {{RdLow_udw = (Mem_tudw).a;
1201 RdHigh_udw = (Mem_tudw).b;}});
1200 {{RdLow_udw = Mem_tudw[0];
1201 RdHigh_udw = Mem_tudw[1];}});
1202 default: ldtwa({{
1202 default: ldtwa({{
1203 RdLow = (Mem_tuw).a;
1204 RdHigh = (Mem_tuw).b;}});
1203 RdLow = Mem_tuw[0];
1204 RdHigh = Mem_tuw[1];}});
1205 }
1206 }
1207 format StoreAlt {
1208 0x14: stwa({{Mem_uw = Rd;}});
1209 0x15: stba({{Mem_ub = Rd;}});
1210 0x16: stha({{Mem_uhw = Rd;}});
1211 0x17: sttwa({{
1212 // This temporary needs to be here so that the parser
1213 // will correctly identify this instruction as a store.
1214 // It's probably either the parenthesis or referencing
1215 // the member variable that throws confuses it.
1205 }
1206 }
1207 format StoreAlt {
1208 0x14: stwa({{Mem_uw = Rd;}});
1209 0x15: stba({{Mem_ub = Rd;}});
1210 0x16: stha({{Mem_uhw = Rd;}});
1211 0x17: sttwa({{
1212 // This temporary needs to be here so that the parser
1213 // will correctly identify this instruction as a store.
1214 // It's probably either the parenthesis or referencing
1215 // the member variable that throws confuses it.
1216 Twin32_t temp;
1217 temp.a = RdLow<31:0>;
1218 temp.b = RdHigh<31:0>;
1216 std::array<uint32_t, 2> temp;
1217 temp[0] = RdLow<31:0>;
1218 temp[1] = RdHigh<31:0>;
1219 Mem_tuw = temp;
1220 }});
1221 }
1222 format LoadAlt {
1223 0x18: ldswa({{Rd = Mem_sw;}});
1224 0x19: ldsba({{Rd = Mem_sb;}});
1225 0x1A: ldsha({{Rd = Mem_shw;}});
1226 0x1B: ldxa({{Rd = Mem_sdw;}});

--- 223 unchanged lines hidden --- 		1219 Mem_tuw = temp;
1220 }});
1221 }
1222 format LoadAlt {
1223 0x18: ldswa({{Rd = Mem_sw;}});
1224 0x19: ldsba({{Rd = Mem_sb;}});
1225 0x1A: ldsha({{Rd = Mem_shw;}});
1226 0x1B: ldxa({{Rd = Mem_sdw;}});

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