decoder.isa (11294:a368064a2ab5) decoder.isa (12287:4163eeb6210c)
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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362 Rd = StrandStsReg;
363 }});
364 // 0x1A is supposed to be reserved, but it reads the strand
365 // status register.
366 // 0x1B-0x1F should cause an illegal instruction exception
367 }
368 0x29: decode RS1 {
369 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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362 Rd = StrandStsReg;
363 }});
364 // 0x1A is supposed to be reserved, but it reads the strand
365 // status register.
366 // 0x1B-0x1F should cause an illegal instruction exception
367 }
368 0x29: decode RS1 {
369 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
370 0x01: HPriv::rdhprhtstate({{Rd = Htstate;}}, checkTl=true);
370 0x01: HPriv::rdhprhtstate({{Rd = Htstate;}}, check_tl=true);
371 // 0x02 should cause an illegal instruction exception
372 0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
373 // 0x04 should cause an illegal instruction exception
374 0x05: HPriv::rdhprhtba({{Rd = Htba;}});
375 0x06: HPriv::rdhprhver({{Rd = Hver;}});
376 // 0x07-0x1E should cause an illegal instruction exception
377 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
378 }
379 0x2A: decode RS1 {
371 // 0x02 should cause an illegal instruction exception
372 0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
373 // 0x04 should cause an illegal instruction exception
374 0x05: HPriv::rdhprhtba({{Rd = Htba;}});
375 0x06: HPriv::rdhprhver({{Rd = Hver;}});
376 // 0x07-0x1E should cause an illegal instruction exception
377 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
378 }
379 0x2A: decode RS1 {
380 0x00: Priv::rdprtpc({{Rd = Tpc;}}, checkTl=true);
381 0x01: Priv::rdprtnpc({{Rd = Tnpc;}}, checkTl=true);
382 0x02: Priv::rdprtstate({{Rd = Tstate;}}, checkTl=true);
383 0x03: Priv::rdprtt({{Rd = Tt;}}, checkTl=true);
380 0x00: Priv::rdprtpc({{Rd = Tpc;}}, check_tl=true);
381 0x01: Priv::rdprtnpc({{Rd = Tnpc;}}, check_tl=true);
382 0x02: Priv::rdprtstate({{Rd = Tstate;}}, check_tl=true);
383 0x03: Priv::rdprtt({{Rd = Tt;}}, check_tl=true);
384 0x04: Priv::rdprtick({{Rd = Tick;}});
385 0x05: Priv::rdprtba({{Rd = Tba;}});
386 0x06: Priv::rdprpstate({{Rd = Pstate;}});
387 0x07: Priv::rdprtl({{Rd = Tl;}});
388 0x08: Priv::rdprpil({{Rd = Pil;}});
389 0x09: Priv::rdprcwp({{Rd = Cwp;}});
390 0x0A: Priv::rdprcansave({{Rd = Cansave;}});
391 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});

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464 0x5: movrne({{Rd = (Rs1_sdw != 0) ? Rs2_or_imm10 : Rd;}});
465 0x6: movrg({{Rd = (Rs1_sdw > 0) ? Rs2_or_imm10 : Rd;}});
466 0x7: movrge({{Rd = (Rs1_sdw >= 0) ? Rs2_or_imm10 : Rd;}});
467 }
468 0x30: decode RD {
469 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}});
470 // 0x01 should cause an illegal instruction exception
471 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
384 0x04: Priv::rdprtick({{Rd = Tick;}});
385 0x05: Priv::rdprtba({{Rd = Tba;}});
386 0x06: Priv::rdprpstate({{Rd = Pstate;}});
387 0x07: Priv::rdprtl({{Rd = Tl;}});
388 0x08: Priv::rdprpil({{Rd = Pil;}});
389 0x09: Priv::rdprcwp({{Rd = Cwp;}});
390 0x0A: Priv::rdprcansave({{Rd = Cansave;}});
391 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});

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464 0x5: movrne({{Rd = (Rs1_sdw != 0) ? Rs2_or_imm10 : Rd;}});
465 0x6: movrg({{Rd = (Rs1_sdw > 0) ? Rs2_or_imm10 : Rd;}});
466 0x7: movrge({{Rd = (Rs1_sdw >= 0) ? Rs2_or_imm10 : Rd;}});
467 }
468 0x30: decode RD {
469 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}});
470 // 0x01 should cause an illegal instruction exception
471 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
472 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}, false,
472 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}},
473 IsSquashAfter);
474 // 0x04-0x05 should cause an illegal instruction exception
475 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
476 // 0x07-0x0E should cause an illegal instruction exception
477 0x0F: Trap::softreset({{fault = std::make_shared<SoftwareInitiatedReset>();}});
478 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
479 0x11: Priv::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
480 // 0x12 should cause an illegal instruction exception

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520 Otherwin = Otherwin - 1;
521
522 if (Cleanwin < NWindows - 1)
523 Cleanwin = Cleanwin + 1;
524 }});
525 }
526 0x32: decode RD {
527 0x00: Priv::wrprtpc(
473 IsSquashAfter);
474 // 0x04-0x05 should cause an illegal instruction exception
475 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
476 // 0x07-0x0E should cause an illegal instruction exception
477 0x0F: Trap::softreset({{fault = std::make_shared<SoftwareInitiatedReset>();}});
478 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
479 0x11: Priv::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
480 // 0x12 should cause an illegal instruction exception

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520 Otherwin = Otherwin - 1;
521
522 if (Cleanwin < NWindows - 1)
523 Cleanwin = Cleanwin + 1;
524 }});
525 }
526 0x32: decode RD {
527 0x00: Priv::wrprtpc(
528 {{Tpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
528 {{Tpc = Rs1 ^ Rs2_or_imm13;}}, check_tl=true);
529 0x01: Priv::wrprtnpc(
529 0x01: Priv::wrprtnpc(
530 {{Tnpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
530 {{Tnpc = Rs1 ^ Rs2_or_imm13;}}, check_tl=true);
531 0x02: Priv::wrprtstate(
531 0x02: Priv::wrprtstate(
532 {{Tstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
532 {{Tstate = Rs1 ^ Rs2_or_imm13;}}, check_tl=true);
533 0x03: Priv::wrprtt(
533 0x03: Priv::wrprtt(
534 {{Tt = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
534 {{Tt = Rs1 ^ Rs2_or_imm13;}}, check_tl=true);
535 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
536 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
537 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
538 0x07: Priv::wrprtl({{
539 if (Pstate.priv && !Hpstate.hpriv)
540 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
541 else
542 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);

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555 else
556 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
557 }});
558 // 0x11-0x1F should cause an illegal instruction exception
559 }
560 0x33: decode RD {
561 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
562 0x01: HPriv::wrhprhtstate(
535 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
536 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
537 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
538 0x07: Priv::wrprtl({{
539 if (Pstate.priv && !Hpstate.hpriv)
540 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
541 else
542 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);

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555 else
556 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
557 }});
558 // 0x11-0x1F should cause an illegal instruction exception
559 }
560 0x33: decode RD {
561 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
562 0x01: HPriv::wrhprhtstate(
563 {{Htstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
563 {{Htstate = Rs1 ^ Rs2_or_imm13;}}, check_tl=true);
564 // 0x02 should cause an illegal instruction exception
565 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
566 // 0x04 should cause an illegal instruction exception
567 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
568 // 0x06-0x01D should cause an illegal instruction exception
569 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
570 }
571 0x34: decode OPF{

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1077 Pstate = Tstate<20:8>;
1078 Asi = Tstate<31:24>;
1079 Ccr = Tstate<39:32>;
1080 Gl = Tstate<42:40>;
1081 Hpstate = Htstate;
1082 NPC = Tnpc;
1083 NNPC = Tnpc + 4;
1084 Tl = Tl - 1;
564 // 0x02 should cause an illegal instruction exception
565 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
566 // 0x04 should cause an illegal instruction exception
567 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
568 // 0x06-0x01D should cause an illegal instruction exception
569 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
570 }
571 0x34: decode OPF{

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1077 Pstate = Tstate<20:8>;
1078 Asi = Tstate<31:24>;
1079 Ccr = Tstate<39:32>;
1080 Gl = Tstate<42:40>;
1081 Hpstate = Htstate;
1082 NPC = Tnpc;
1083 NNPC = Tnpc + 4;
1084 Tl = Tl - 1;
1085 }}, checkTl=true);
1085 }}, check_tl=true);
1086 0x1: Priv::retry({{
1087 Cwp = Tstate<4:0>;
1088 Pstate = Tstate<20:8>;
1089 Asi = Tstate<31:24>;
1090 Ccr = Tstate<39:32>;
1091 Gl = Tstate<42:40>;
1092 Hpstate = Htstate;
1093 NPC = Tpc;
1094 NNPC = Tnpc;
1095 Tl = Tl - 1;
1086 0x1: Priv::retry({{
1087 Cwp = Tstate<4:0>;
1088 Pstate = Tstate<20:8>;
1089 Asi = Tstate<31:24>;
1090 Ccr = Tstate<39:32>;
1091 Gl = Tstate<42:40>;
1092 Hpstate = Htstate;
1093 NPC = Tpc;
1094 NNPC = Tnpc;
1095 Tl = Tl - 1;
1096 }}, checkTl=true);
1096 }}, check_tl=true);
1097 }
1098 }
1099 }
1100 0x3: decode OP3 {
1101 format Load {
1102 0x00: lduw({{Rd = Mem_uw;}});
1103 0x01: ldub({{Rd = Mem_ub;}});
1104 0x02: lduh({{Rd = Mem_uhw;}});

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1098 }
1099 }
1100 0x3: decode OP3 {
1101 format Load {
1102 0x00: lduw({{Rd = Mem_uw;}});
1103 0x01: ldub({{Rd = Mem_ub;}});
1104 0x02: lduh({{Rd = Mem_uhw;}});

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