1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the 10// documentation and/or other materials provided with the distribution; 11// neither the name of the copyright holders nor the names of its 12// contributors may be used to endorse or promote products derived from 13// this software without specific prior written permission. 14// 15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26// 27// Authors: Ali Saidi 28// Gabe Black 29// Steve Reinhardt 30 31//////////////////////////////////////////////////////////////////// 32// 33// The actual decoder specification 34// 35 36decode OP default Unknown::unknown() 37{ 38 0x0: decode OP2 39 { 40 //Throw an illegal instruction acception 41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}}); 42 format BranchN 43 { 44 //bpcc 45 0x1: decode COND2 46 { 47 //Branch Always 48 0x8: decode A 49 { 50 0x0: bpa(19, {{ 51 NNPC = xc->readPC() + disp; 52 }}); 53 0x1: bpa(19, {{ 54 NPC = xc->readPC() + disp; 55 NNPC = NPC + 4; 56 }}, ',a'); 57 } 58 //Branch Never 59 0x0: decode A 60 { 61 0x0: bpn(19, {{ 62 NNPC = NNPC;//Don't do anything 63 }}); 64 0x1: bpn(19, {{ 65 NNPC = NPC + 8; 66 NPC = NPC + 4; 67 }}, ',a'); 68 } 69 default: decode BPCC 70 { 71 0x0: bpcci(19, {{ 72 if(passesCondition(Ccr<3:0>, COND2)) 73 NNPC = xc->readPC() + disp; 74 else 75 handle_annul 76 }}); 77 0x2: bpccx(19, {{ 78 if(passesCondition(Ccr<7:4>, COND2)) 79 NNPC = xc->readPC() + disp; 80 else 81 handle_annul 82 }}); 83 } 84 } 85 //bicc 86 0x2: decode COND2 87 { 88 //Branch Always 89 0x8: decode A 90 { 91 0x0: ba(22, {{ 92 NNPC = xc->readPC() + disp; 93 }}); 94 0x1: ba(22, {{ 95 NPC = xc->readPC() + disp; 96 NNPC = NPC + 4; 97 }}, ',a'); 98 } 99 //Branch Never 100 0x0: decode A 101 { 102 0x0: bn(22, {{ 103 NNPC = NNPC;//Don't do anything 104 }}); 105 0x1: bn(22, {{ 106 NNPC = NPC + 8; 107 NPC = NPC + 4; 108 }}, ',a'); 109 } 110 default: bicc(22, {{ 111 if(passesCondition(Ccr<3:0>, COND2)) 112 NNPC = xc->readPC() + disp; 113 else 114 handle_annul 115 }}); 116 } 117 } 118 0x3: decode RCOND2 119 { 120 format BranchSplit 121 { 122 0x1: bpreq({{ 123 if(Rs1.sdw == 0) 124 NNPC = xc->readPC() + disp; 125 else 126 handle_annul 127 }}); 128 0x2: bprle({{ 129 if(Rs1.sdw <= 0) 130 NNPC = xc->readPC() + disp; 131 else 132 handle_annul 133 }}); 134 0x3: bprl({{ 135 if(Rs1.sdw < 0) 136 NNPC = xc->readPC() + disp; 137 else 138 handle_annul 139 }}); 140 0x5: bprne({{ 141 if(Rs1.sdw != 0) 142 NNPC = xc->readPC() + disp; 143 else 144 handle_annul 145 }}); 146 0x6: bprg({{ 147 if(Rs1.sdw > 0) 148 NNPC = xc->readPC() + disp; 149 else 150 handle_annul 151 }}); 152 0x7: bprge({{ 153 if(Rs1.sdw >= 0) 154 NNPC = xc->readPC() + disp; 155 else 156 handle_annul 157 }}); 158 } 159 } 160 //SETHI (or NOP if rd == 0 and imm == 0) 161 0x4: SetHi::sethi({{Rd.udw = imm;}}); 162 //fbpfcc 163 0x5: decode COND2 { 164 format BranchN { 165 //Branch Always 166 0x8: decode A 167 { 168 0x0: fbpa(22, {{ 169 NNPC = xc->readPC() + disp; 170 }}); 171 0x1: fbpa(22, {{ 172 NPC = xc->readPC() + disp; 173 NNPC = NPC + 4; 174 }}, ',a'); 175 } 176 //Branch Never 177 0x0: decode A 178 { 179 0x0: fbpn(22, {{ 180 NNPC = NNPC;//Don't do anything 181 }}); 182 0x1: fbpn(22, {{ 183 NNPC = NPC + 8; 184 NPC = NPC + 4; 185 }}, ',a'); 186 } 187 default: decode BPCC { 188 0x0: fbpcc0(22, {{ 189 if(passesFpCondition(Fsr<11:10>, COND2)) 190 NNPC = xc->readPC() + disp; 191 else 192 handle_annul 193 }}); 194 0x1: fbpcc1(22, {{ 195 if(passesFpCondition(Fsr<33:32>, COND2)) 196 NNPC = xc->readPC() + disp; 197 else 198 handle_annul 199 }}); 200 0x2: fbpcc2(22, {{ 201 if(passesFpCondition(Fsr<35:34>, COND2)) 202 NNPC = xc->readPC() + disp; 203 else 204 handle_annul 205 }}); 206 0x3: fbpcc3(22, {{ 207 if(passesFpCondition(Fsr<37:36>, COND2)) 208 NNPC = xc->readPC() + disp; 209 else 210 handle_annul 211 }}); 212 } 213 } 214 } 215 //fbfcc 216 0x6: decode COND2 { 217 format BranchN { 218 //Branch Always 219 0x8: decode A 220 { 221 0x0: fba(22, {{ 222 NNPC = xc->readPC() + disp; 223 }}); 224 0x1: fba(22, {{ 225 NPC = xc->readPC() + disp; 226 NNPC = NPC + 4; 227 }}, ',a'); 228 } 229 //Branch Never 230 0x0: decode A 231 { 232 0x0: fbn(22, {{ 233 NNPC = NNPC;//Don't do anything 234 }}); 235 0x1: fbn(22, {{ 236 NNPC = NPC + 8; 237 NPC = NPC + 4; 238 }}, ',a'); 239 } 240 default: fbfcc(22, {{ 241 if(passesFpCondition(Fsr<11:10>, COND2)) 242 NNPC = xc->readPC() + disp; 243 else 244 handle_annul 245 }}); 246 } 247 } 248 } 249 0x1: BranchN::call(30, {{ 250 if (Pstate<3:>) 251 R15 = (xc->readPC())<31:0>; 252 else 253 R15 = xc->readPC(); 254 NNPC = R15 + disp; 255 }}); 256 0x2: decode OP3 { 257 format IntOp { 258 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}}); 259 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}}); 260 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}}); 261 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}}); 262 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}}); 263 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}}); 264 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}}); 265 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}}); 266 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}}); 267 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}}); 268 0x0A: umul({{ 269 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>; 270 Y = Rd<63:32>; 271 }}); 272 0x0B: smul({{ 273 Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 274 Y = Rd.sdw<63:32>; 275 }}); 276 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}}); 277 0x0D: udivx({{ 278 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 279 else Rd.udw = Rs1.udw / Rs2_or_imm13; 280 }}); 281 0x0E: udiv({{ 282 if(Rs2_or_imm13 == 0) fault = new DivisionByZero; 283 else 284 { 285 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13; 286 if(Rd.udw >> 32 != 0) 287 Rd.udw = 0xFFFFFFFF; 288 } 289 }}); 290 0x0F: sdiv({{ 291 if(Rs2_or_imm13.sdw == 0) 292 fault = new DivisionByZero; 293 else 294 { 295 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw; 296 if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max()) 297 Rd.udw = 0x7FFFFFFF; 298 else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min()) 299 Rd.udw = ULL(0xFFFFFFFF80000000); 300 } 301 }}); 302 } 303 format IntOpCc { 304 0x10: addcc({{ 305 int64_t resTemp, val2 = Rs2_or_imm13; 306 Rd = resTemp = Rs1 + val2;}}, 307 {{(Rs1<31:0> + val2<31:0>)<32:>}}, 308 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 309 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}}, 310 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 311 ); 312 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}}); 313 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}}); 314 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}}); 315 0x14: subcc({{ 316 int64_t val2 = Rs2_or_imm13; 317 Rd = Rs1 - val2;}}, 318 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}}, 319 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}}, 320 {{(~(Rs1<63:1> + (~val2)<63:1> + 321 (Rs1 | ~val2)<0:>))<63:>}}, 322 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}} 323 ); 324 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}}); 325 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}}); 326 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}}); 327 0x18: addccc({{ 328 int64_t resTemp, val2 = Rs2_or_imm13; 329 int64_t carryin = Ccr<0:0>; 330 Rd = resTemp = Rs1 + val2 + carryin;}}, 331 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}}, 332 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}}, 333 {{((Rs1 & val2) | (~resTemp & (Rs1 | val2)))<63:>}}, 334 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 335 ); 336 0x1A: IntOpCcRes::umulcc({{ 337 uint64_t resTemp; 338 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>; 339 Y = resTemp<63:32>;}}); 340 0x1B: IntOpCcRes::smulcc({{ 341 int64_t resTemp; 342 Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>); 343 Y = resTemp<63:32>;}}); 344 0x1C: subccc({{ 345 int64_t resTemp, val2 = Rs2_or_imm13; 346 int64_t carryin = Ccr<0:0>; 347 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}}, 348 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<31:>}}, 349 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}}, 350 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<63:>}}, 351 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}} 352 ); 353 0x1D: IntOpCcRes::udivxcc({{ 354 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero; 355 else Rd = Rs1.udw / Rs2_or_imm13.udw;}}); 356 0x1E: udivcc({{ 357 uint32_t resTemp, val2 = Rs2_or_imm13.udw; 358 int32_t overflow = 0; 359 if(val2 == 0) fault = new DivisionByZero; 360 else 361 { 362 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2; 363 overflow = (resTemp<63:32> != 0); 364 if(overflow) Rd = resTemp = 0xFFFFFFFF; 365 else Rd = resTemp; 366 } }}, 367 {{0}}, 368 {{overflow}}, 369 {{0}}, 370 {{0}} 371 ); 372 0x1F: sdivcc({{ 373 int64_t val2 = Rs2_or_imm13.sdw<31:0>; 374 bool overflow = false, underflow = false; 375 if(val2 == 0) fault = new DivisionByZero; 376 else 377 { 378 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2; 379 overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max()); 380 underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min()); 381 if(overflow) Rd = 0x7FFFFFFF; 382 else if(underflow) Rd = ULL(0xFFFFFFFF80000000); 383 } }}, 384 {{0}}, 385 {{overflow || underflow}}, 386 {{0}}, 387 {{0}} 388 ); 389 0x20: taddcc({{ 390 int64_t resTemp, val2 = Rs2_or_imm13; 391 Rd = resTemp = Rs1 + val2; 392 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 393 {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, 394 {{overflow}}, 395 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 396 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 397 ); 398 0x21: tsubcc({{ 399 int64_t resTemp, val2 = Rs2_or_imm13; 400 Rd = resTemp = Rs1 + val2; 401 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}}, 402 {{(Rs1<31:0> + val2<31:0>)<32:0>}}, 403 {{overflow}}, 404 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 405 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 406 ); 407 0x22: taddcctv({{ 408 int64_t val2 = Rs2_or_imm13; 409 Rd = Rs1 + val2; 410 int32_t overflow = Rs1<1:0> || val2<1:0> || 411 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>); 412 if(overflow) fault = new TagOverflow;}}, 413 {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, 414 {{overflow}}, 415 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 416 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}} 417 ); 418 0x23: tsubcctv({{ 419 int64_t resTemp, val2 = Rs2_or_imm13; 420 Rd = resTemp = Rs1 + val2; 421 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>); 422 if(overflow) fault = new TagOverflow;}}, 423 {{((Rs1<31:0> + val2<31:0>)<32:0>)}}, 424 {{overflow}}, 425 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}}, 426 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}} 427 ); 428 0x24: mulscc({{ 429 int64_t resTemp, multiplicand = Rs2_or_imm13; 430 int32_t multiplier = Rs1<31:0>; 431 int32_t savedLSB = Rs1<0:>; 432 multiplier = multiplier<31:1> | 433 ((Ccr<3:3> ^ Ccr<1:1>) << 32); 434 if(!Y<0:>) 435 multiplicand = 0; 436 Rd = resTemp = multiplicand + multiplier; 437 Y = Y<31:1> | (savedLSB << 31);}}, 438 {{((multiplicand<31:0> + multiplier<31:0>)<32:0>)}}, 439 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}}, 440 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}}, 441 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}} 442 ); 443 } 444 format IntOp 445 { 446 0x25: decode X { 447 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); 448 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); 449 } 450 0x26: decode X { 451 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}}); 452 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}}); 453 } 454 0x27: decode X { 455 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); 456 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}}); 457 } 458 0x28: decode RS1 { 459 0x00: NoPriv::rdy({{Rd = Y<31:0>;}}); 460 //1 should cause an illegal instruction exception 461 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 462 0x03: NoPriv::rdasi({{Rd = Asi;}}); 463 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); 464 0x05: NoPriv::rdpc({{ 465 if(Pstate<3:>) 466 Rd = (xc->readPC())<31:0>; 467 else 468 Rd = xc->readPC();}}); 469 0x06: NoPriv::rdfprs({{ 470 //Wait for all fpops to finish. 471 Rd = Fprs; 472 }}); 473 //7-14 should cause an illegal instruction exception 474 0x0F: decode I { 475 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp); 476 0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp); 477 } 478 0x10: Priv::rdpcr({{Rd = Pcr;}}); 479 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}}); 480 //0x12 should cause an illegal instruction exception 481 0x13: NoPriv::rdgsr({{ 482 fault = checkFpEnableFault(xc); 483 if (fault) 484 return fault; 485 Rd = Gsr; 486 }}); 487 //0x14-0x15 should cause an illegal instruction exception 488 0x16: Priv::rdsoftint({{Rd = Softint;}}); 489 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}}); 490 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}}); 491 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}}); 492 0x1A: Priv::rdstrand_sts_reg({{ 493 if(Pstate<2:> && !Hpstate<2:>) 494 Rd = StrandStsReg<0:>; 495 else 496 Rd = StrandStsReg; 497 }}); 498 //0x1A is supposed to be reserved, but it reads the strand 499 //status register. 500 //0x1B-0x1F should cause an illegal instruction exception 501 } 502 0x29: decode RS1 { 503 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}}); 504 0x01: HPriv::rdhprhtstate({{ 505 if(Tl == 0) 506 return new IllegalInstruction; 507 Rd = Htstate; 508 }}); 509 //0x02 should cause an illegal instruction exception 510 0x03: HPriv::rdhprhintp({{Rd = Hintp;}}); 511 //0x04 should cause an illegal instruction exception 512 0x05: HPriv::rdhprhtba({{Rd = Htba;}}); 513 0x06: HPriv::rdhprhver({{Rd = Hver;}}); 514 //0x07-0x1E should cause an illegal instruction exception 515 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}}); 516 } 517 0x2A: decode RS1 { 518 0x00: Priv::rdprtpc({{ 519 if(Tl == 0) 520 return new IllegalInstruction; 521 Rd = Tpc; 522 }}); 523 0x01: Priv::rdprtnpc({{ 524 if(Tl == 0) 525 return new IllegalInstruction; 526 Rd = Tnpc; 527 }}); 528 0x02: Priv::rdprtstate({{ 529 if(Tl == 0) 530 return new IllegalInstruction; 531 Rd = Tstate; 532 }}); 533 0x03: Priv::rdprtt({{ 534 if(Tl == 0) 535 return new IllegalInstruction; 536 Rd = Tt; 537 }}); 538 0x04: Priv::rdprtick({{Rd = Tick;}}); 539 0x05: Priv::rdprtba({{Rd = Tba;}}); 540 0x06: Priv::rdprpstate({{Rd = Pstate;}}); 541 0x07: Priv::rdprtl({{Rd = Tl;}}); 542 0x08: Priv::rdprpil({{Rd = Pil;}}); 543 0x09: Priv::rdprcwp({{Rd = Cwp;}}); 544 0x0A: Priv::rdprcansave({{Rd = Cansave;}}); 545 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}}); 546 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}}); 547 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}}); 548 0x0E: Priv::rdprwstate({{Rd = Wstate;}}); 549 //0x0F should cause an illegal instruction exception 550 0x10: Priv::rdprgl({{Rd = Gl;}}); 551 //0x11-0x1F should cause an illegal instruction exception 552 } 553 0x2B: BasicOperate::flushw({{ 554 if(NWindows - 2 - Cansave != 0) 555 { 556 if(Otherwin) 557 fault = new SpillNOther(4*Wstate<5:3>); 558 else 559 fault = new SpillNNormal(4*Wstate<2:0>); 560 } 561 }}); 562 0x2C: decode MOVCC3 563 { 564 0x0: Trap::movccfcc({{fault = new FpDisabled;}}); 565 0x1: decode CC 566 { 567 0x0: movcci({{ 568 if(passesCondition(Ccr<3:0>, COND4)) 569 Rd = Rs2_or_imm11; 570 else 571 Rd = Rd; 572 }}); 573 0x2: movccx({{ 574 if(passesCondition(Ccr<7:4>, COND4)) 575 Rd = Rs2_or_imm11; 576 else 577 Rd = Rd; 578 }}); 579 } 580 } 581 0x2D: sdivx({{ 582 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero; 583 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw; 584 }}); 585 0x2E: Trap::popc({{fault = new IllegalInstruction;}}); 586 0x2F: decode RCOND3 587 { 588 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}}); 589 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}}); 590 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}}); 591 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}}); 592 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}}); 593 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}}); 594 } 595 0x30: decode RD { 596 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}}); 597 //0x01 should cause an illegal instruction exception 598 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}}); 599 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}}); 600 //0x04-0x05 should cause an illegal instruction exception 601 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}}); 602 //0x07-0x0E should cause an illegal instruction exception 603 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}}); 604 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}}); 605 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}}); 606 //0x12 should cause an illegal instruction exception 607 0x13: NoPriv::wrgsr({{ 608 if(Fprs<2:> == 0 || Pstate<4:> == 0) 609 return new FpDisabled; 610 Gsr = Rs1 ^ Rs2_or_imm13; 611 }}); 612 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}}); 613 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}}); 614 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}}); 615 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}}); 616 0x18: NoPriv::wrstick({{ 617 if(!Hpstate<2:>) 618 return new IllegalInstruction; 619 Stick = Rs1 ^ Rs2_or_imm13; 620 }}); 621 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}}); 622 0x1A: Priv::wrstrand_sts_reg({{ |
623 StrandStsReg = Rs1 ^ Rs2_or_imm13; 624 }}); 625 //0x1A is supposed to be reserved, but it writes the strand 626 //status register. 627 //0x1B-0x1F should cause an illegal instruction exception 628 } 629 0x31: decode FCN { 630 0x0: Priv::saved({{ 631 assert(Cansave < NWindows - 2); 632 assert(Otherwin || Canrestore); 633 Cansave = Cansave + 1; 634 if(Otherwin == 0) 635 Canrestore = Canrestore - 1; 636 else 637 Otherwin = Otherwin - 1; 638 }}); 639 0x1: Priv::restored({{ 640 assert(Cansave || Otherwin); 641 assert(Canrestore < NWindows - 2); 642 Canrestore = Canrestore + 1; 643 if(Otherwin == 0) 644 Cansave = Cansave - 1; 645 else 646 Otherwin = Otherwin - 1; 647 648 if(Cleanwin < NWindows - 1) 649 Cleanwin = Cleanwin + 1; 650 }}); 651 } 652 0x32: decode RD { 653 0x00: Priv::wrprtpc({{ 654 if(Tl == 0) 655 return new IllegalInstruction; 656 else 657 Tpc = Rs1 ^ Rs2_or_imm13; 658 }}); 659 0x01: Priv::wrprtnpc({{ 660 if(Tl == 0) 661 return new IllegalInstruction; 662 else 663 Tnpc = Rs1 ^ Rs2_or_imm13; 664 }}); 665 0x02: Priv::wrprtstate({{ 666 if(Tl == 0) 667 return new IllegalInstruction; 668 else 669 Tstate = Rs1 ^ Rs2_or_imm13; 670 }}); 671 0x03: Priv::wrprtt({{ 672 if(Tl == 0) 673 return new IllegalInstruction; 674 else 675 Tt = Rs1 ^ Rs2_or_imm13; 676 }}); 677 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); 678 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 679 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 680 0x07: Priv::wrprtl({{ 681 if(Pstate<2:> && !Hpstate<2:>) 682 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL); 683 else 684 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL); 685 }}); 686 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}}); 687 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}}); 688 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}}); 689 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}}); 690 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}}); 691 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}}); 692 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}}); 693 //0x0F should cause an illegal instruction exception 694 0x10: Priv::wrprgl({{ 695 if(Pstate<2:> && !Hpstate<2:>) 696 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL); 697 else 698 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL); 699 }}); 700 //0x11-0x1F should cause an illegal instruction exception 701 } 702 0x33: decode RD { 703 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}}); 704 0x01: HPriv::wrhprhtstate({{ 705 if(Tl == 0) 706 return new IllegalInstruction; 707 Htstate = Rs1 ^ Rs2_or_imm13; 708 }}); 709 //0x02 should cause an illegal instruction exception 710 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}}); 711 //0x04 should cause an illegal instruction exception 712 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); 713 //0x06-0x01D should cause an illegal instruction exception 714 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}}); 715 } 716 0x34: decode OPF{ 717 format FpBasic{ 718 0x01: fmovs({{ 719 Frds.uw = Frs2s.uw; 720 //fsr.ftt = fsr.cexc = 0 721 Fsr &= ~(7 << 14); 722 Fsr &= ~(0x1F); 723 }}); 724 0x02: fmovd({{ 725 Frd.udw = Frs2.udw; 726 //fsr.ftt = fsr.cexc = 0 727 Fsr &= ~(7 << 14); 728 Fsr &= ~(0x1F); 729 }}); 730 0x03: FpUnimpl::fmovq(); 731 0x05: fnegs({{ 732 Frds.uw = Frs2s.uw ^ (1UL << 31); 733 //fsr.ftt = fsr.cexc = 0 734 Fsr &= ~(7 << 14); 735 Fsr &= ~(0x1F); 736 }}); 737 0x06: fnegd({{ 738 Frd.udw = Frs2.udw ^ (1ULL << 63); 739 //fsr.ftt = fsr.cexc = 0 740 Fsr &= ~(7 << 14); 741 Fsr &= ~(0x1F); 742 }}); 743 0x07: FpUnimpl::fnegq(); 744 0x09: fabss({{ 745 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw; 746 //fsr.ftt = fsr.cexc = 0 747 Fsr &= ~(7 << 14); 748 Fsr &= ~(0x1F); 749 }}); 750 0x0A: fabsd({{ 751 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw; 752 //fsr.ftt = fsr.cexc = 0 753 Fsr &= ~(7 << 14); 754 Fsr &= ~(0x1F); 755 }}); 756 0x0B: FpUnimpl::fabsq(); 757 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}}); 758 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}}); 759 0x2B: FpUnimpl::fsqrtq(); 760 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}}); 761 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}}); 762 0x43: FpUnimpl::faddq(); 763 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}}); 764 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df; }}); 765 0x47: FpUnimpl::fsubq(); 766 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}}); 767 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}}); 768 0x4B: FpUnimpl::fmulq(); 769 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}}); 770 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}}); 771 0x4F: FpUnimpl::fdivq(); 772 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}}); 773 0x6E: FpUnimpl::fdmulq(); 774 0x81: fstox({{ 775 Frd.sdw = static_cast<int64_t>(Frs2s.sf); 776 }}); 777 0x82: fdtox({{ 778 Frd.sdw = static_cast<int64_t>(Frs2.df); 779 }}); 780 0x83: FpUnimpl::fqtox(); 781 0x84: fxtos({{ 782 Frds.sf = static_cast<float>(Frs2.sdw); 783 }}); 784 0x88: fxtod({{ 785 Frd.df = static_cast<double>(Frs2.sdw); 786 }}); 787 0x8C: FpUnimpl::fxtoq(); 788 0xC4: fitos({{ 789 Frds.sf = static_cast<float>(Frs2s.sw); 790 }}); 791 0xC6: fdtos({{Frds.sf = Frs2.df;}}); 792 0xC7: FpUnimpl::fqtos(); 793 0xC8: fitod({{ 794 Frd.df = static_cast<double>(Frs2s.sw); 795 }}); 796 0xC9: fstod({{Frd.df = Frs2s.sf;}}); 797 0xCB: FpUnimpl::fqtod(); 798 0xCC: FpUnimpl::fitoq(); 799 0xCD: FpUnimpl::fstoq(); 800 0xCE: FpUnimpl::fdtoq(); 801 0xD1: fstoi({{ 802 Frds.sw = static_cast<int32_t>(Frs2s.sf); 803 float t = Frds.sw; 804 if (t != Frs2s.sf) 805 Fsr = insertBits(Fsr, 4,0, 0x01); 806 }}); 807 0xD2: fdtoi({{ 808 Frds.sw = static_cast<int32_t>(Frs2.df); 809 double t = Frds.sw; 810 if (t != Frs2.df) 811 Fsr = insertBits(Fsr, 4,0, 0x01); 812 }}); 813 0xD3: FpUnimpl::fqtoi(); 814 default: FailUnimpl::fpop1(); 815 } 816 } 817 0x35: decode OPF{ 818 format FpBasic{ 819 0x51: fcmps({{ 820 uint8_t fcc; 821 if(isnan(Frs1s) || isnan(Frs2s)) 822 fcc = 3; 823 else if(Frs1s < Frs2s) 824 fcc = 1; 825 else if(Frs1s > Frs2s) 826 fcc = 2; 827 else 828 fcc = 0; 829 uint8_t firstbit = 10; 830 if(FCMPCC) 831 firstbit = FCMPCC * 2 + 30; 832 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 833 }}); 834 0x52: fcmpd({{ 835 uint8_t fcc; 836 if(isnan(Frs1) || isnan(Frs2)) 837 fcc = 3; 838 else if(Frs1 < Frs2) 839 fcc = 1; 840 else if(Frs1 > Frs2) 841 fcc = 2; 842 else 843 fcc = 0; 844 uint8_t firstbit = 10; 845 if(FCMPCC) 846 firstbit = FCMPCC * 2 + 30; 847 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 848 }}); 849 0x53: FpUnimpl::fcmpq(); 850 0x55: fcmpes({{ 851 uint8_t fcc = 0; 852 if(isnan(Frs1s) || isnan(Frs2s)) 853 fault = new FpExceptionIEEE754; 854 if(Frs1s < Frs2s) 855 fcc = 1; 856 else if(Frs1s > Frs2s) 857 fcc = 2; 858 uint8_t firstbit = 10; 859 if(FCMPCC) 860 firstbit = FCMPCC * 2 + 30; 861 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 862 }}); 863 0x56: fcmped({{ 864 uint8_t fcc = 0; 865 if(isnan(Frs1) || isnan(Frs2)) 866 fault = new FpExceptionIEEE754; 867 if(Frs1 < Frs2) 868 fcc = 1; 869 else if(Frs1 > Frs2) 870 fcc = 2; 871 uint8_t firstbit = 10; 872 if(FCMPCC) 873 firstbit = FCMPCC * 2 + 30; 874 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc); 875 }}); 876 0x57: FpUnimpl::fcmpeq(); 877 default: FailUnimpl::fpop2(); 878 } 879 } 880 //This used to be just impdep1, but now it's a whole bunch 881 //of instructions 882 0x36: decode OPF{ 883 0x00: FailUnimpl::edge8(); 884 0x01: FailUnimpl::edge8n(); 885 0x02: FailUnimpl::edge8l(); 886 0x03: FailUnimpl::edge8ln(); 887 0x04: FailUnimpl::edge16(); 888 0x05: FailUnimpl::edge16n(); 889 0x06: FailUnimpl::edge16l(); 890 0x07: FailUnimpl::edge16ln(); 891 0x08: FailUnimpl::edge32(); 892 0x09: FailUnimpl::edge32n(); 893 0x0A: FailUnimpl::edge32l(); 894 0x0B: FailUnimpl::edge32ln(); 895 0x10: FailUnimpl::array8(); 896 0x12: FailUnimpl::array16(); 897 0x14: FailUnimpl::array32(); 898 0x18: BasicOperate::alignaddr({{ 899 uint64_t sum = Rs1 + Rs2; 900 Rd = sum & ~7; 901 Gsr = (Gsr & ~7) | (sum & 7); 902 }}); 903 0x19: FailUnimpl::bmask(); 904 0x1A: BasicOperate::alignaddresslittle({{ 905 uint64_t sum = Rs1 + Rs2; 906 Rd = sum & ~7; 907 Gsr = (Gsr & ~7) | ((~sum + 1) & 7); 908 }}); 909 0x20: FailUnimpl::fcmple16(); 910 0x22: FailUnimpl::fcmpne16(); 911 0x24: FailUnimpl::fcmple32(); 912 0x26: FailUnimpl::fcmpne32(); 913 0x28: FailUnimpl::fcmpgt16(); 914 0x2A: FailUnimpl::fcmpeq16(); 915 0x2C: FailUnimpl::fcmpgt32(); 916 0x2E: FailUnimpl::fcmpeq32(); 917 0x31: FailUnimpl::fmul8x16(); 918 0x33: FailUnimpl::fmul8x16au(); 919 0x35: FailUnimpl::fmul8x16al(); 920 0x36: FailUnimpl::fmul8sux16(); 921 0x37: FailUnimpl::fmul8ulx16(); 922 0x38: FailUnimpl::fmuld8sux16(); 923 0x39: FailUnimpl::fmuld8ulx16(); 924 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}}); 925 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}}); 926 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}}); 927 0x3E: Trap::pdist({{fault = new IllegalInstruction;}}); 928 0x48: BasicOperate::faligndata({{ 929 uint64_t msbX = Frs1.udw; 930 uint64_t lsbX = Frs2.udw; 931 //Some special cases need to be split out, first 932 //because they're the most likely to be used, and 933 //second because otherwise, we end up shifting by 934 //greater than the width of the type being shifted, 935 //namely 64, which produces undefined results according 936 //to the C standard. 937 switch(Gsr<2:0>) 938 { 939 case 0: 940 Frd.udw = msbX; 941 break; 942 case 8: 943 Frd.udw = lsbX; 944 break; 945 default: 946 uint64_t msbShift = Gsr<2:0> * 8; 947 uint64_t lsbShift = (8 - Gsr<2:0>) * 8; 948 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift; 949 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift; 950 Frd.udw = ((msbX & msbMask) << msbShift) | 951 ((lsbX & lsbMask) >> lsbShift); 952 } 953 }}); 954 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}}); 955 0x4C: FailUnimpl::bshuffle(); 956 0x4D: FailUnimpl::fexpand(); 957 0x50: FailUnimpl::fpadd16(); 958 0x51: FailUnimpl::fpadd16s(); 959 0x52: FailUnimpl::fpadd32(); 960 0x53: FailUnimpl::fpadd32s(); 961 0x54: FailUnimpl::fpsub16(); 962 0x55: FailUnimpl::fpsub16s(); 963 0x56: FailUnimpl::fpsub32(); 964 0x57: FailUnimpl::fpsub32s(); 965 0x60: FpBasic::fzero({{Frd.df = 0;}}); 966 0x61: FpBasic::fzeros({{Frds.sf = 0;}}); 967 0x62: FailUnimpl::fnor(); 968 0x63: FailUnimpl::fnors(); 969 0x64: FailUnimpl::fandnot2(); 970 0x65: FailUnimpl::fandnot2s(); 971 0x66: FpBasic::fnot2({{ 972 Frd.df = (double)(~((uint64_t)Frs2.df)); 973 }}); 974 0x67: FpBasic::fnot2s({{ 975 Frds.sf = (float)(~((uint32_t)Frs2s.sf)); 976 }}); 977 0x68: FailUnimpl::fandnot1(); 978 0x69: FailUnimpl::fandnot1s(); 979 0x6A: FpBasic::fnot1({{ 980 Frd.df = (double)(~((uint64_t)Frs1.df)); 981 }}); 982 0x6B: FpBasic::fnot1s({{ 983 Frds.sf = (float)(~((uint32_t)Frs1s.sf)); 984 }}); 985 0x6C: FailUnimpl::fxor(); 986 0x6D: FailUnimpl::fxors(); 987 0x6E: FailUnimpl::fnand(); 988 0x6F: FailUnimpl::fnands(); 989 0x70: FailUnimpl::fand(); 990 0x71: FailUnimpl::fands(); 991 0x72: FailUnimpl::fxnor(); 992 0x73: FailUnimpl::fxnors(); 993 0x74: FpBasic::fsrc1({{Frd.udw = Frs1.udw;}}); 994 0x75: FpBasic::fsrc1s({{Frds.uw = Frs1s.uw;}}); 995 0x76: FailUnimpl::fornot2(); 996 0x77: FailUnimpl::fornot2s(); 997 0x78: FpBasic::fsrc2({{Frd.udw = Frs2.udw;}}); 998 0x79: FpBasic::fsrc2s({{Frds.uw = Frs2s.uw;}}); 999 0x7A: FailUnimpl::fornot1(); 1000 0x7B: FailUnimpl::fornot1s(); 1001 0x7C: FailUnimpl::for(); 1002 0x7D: FailUnimpl::fors(); 1003 0x7E: FpBasic::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}}); 1004 0x7F: FpBasic::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}}); 1005 0x80: Trap::shutdown({{fault = new IllegalInstruction;}}); 1006 0x81: FailUnimpl::siam(); 1007 } 1008 // M5 special opcodes use the reserved IMPDEP2A opcode space 1009 0x37: decode M5FUNC { 1010#if FULL_SYSTEM 1011 format BasicOperate { 1012 // we have 7 bits of space here to play with... 1013 0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0); 1014 }}, No_OpClass, IsNonSpeculative); 1015 0x50: m5readfile({{ 1016 O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2); 1017 }}, IsNonSpeculative); 1018 0x51: m5break({{PseudoInst::debugbreak(xc->tcBase()); 1019 }}, IsNonSpeculative); 1020 0x54: m5panic({{ 1021 panic("M5 panic instruction called at pc=%#x.", xc->readPC()); 1022 }}, No_OpClass, IsNonSpeculative); 1023 } 1024#endif 1025 default: Trap::impdep2({{fault = new IllegalInstruction;}}); 1026 } 1027 0x38: Branch::jmpl({{ 1028 Addr target = Rs1 + Rs2_or_imm13; 1029 if(target & 0x3) 1030 fault = new MemAddressNotAligned; 1031 else 1032 { 1033 if (Pstate<3:>) 1034 Rd = (xc->readPC())<31:0>; 1035 else 1036 Rd = xc->readPC(); 1037 NNPC = target; 1038 } 1039 }}); 1040 0x39: Branch::return({{ 1041 Addr target = Rs1 + Rs2_or_imm13; 1042 if(fault == NoFault) 1043 { 1044 //Check for fills which are higher priority than alignment 1045 //faults. 1046 if(Canrestore == 0) 1047 { 1048 if(Otherwin) 1049 fault = new FillNOther(4*Wstate<5:3>); 1050 else 1051 fault = new FillNNormal(4*Wstate<2:0>); 1052 } 1053 //Check for alignment faults 1054 else if(target & 0x3) 1055 fault = new MemAddressNotAligned; 1056 else 1057 { 1058 NNPC = target; 1059 Cwp = (Cwp - 1 + NWindows) % NWindows; 1060 Cansave = Cansave + 1; 1061 Canrestore = Canrestore - 1; 1062 } 1063 } 1064 }}); 1065 0x3A: decode CC 1066 { 1067 0x0: Trap::tcci({{ 1068 if(passesCondition(Ccr<3:0>, COND2)) 1069 { 1070 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 1071 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 1072 fault = new TrapInstruction(lTrapNum); 1073 } 1074 }}, IsSerializeAfter, IsNonSpeculative); 1075 0x2: Trap::tccx({{ 1076 if(passesCondition(Ccr<7:4>, COND2)) 1077 { 1078 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2); 1079 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum); 1080 fault = new TrapInstruction(lTrapNum); 1081 } 1082 }}, IsSerializeAfter, IsNonSpeculative); 1083 } 1084 0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier, 1085 MemWriteOp); 1086 0x3C: save({{ 1087 if(Cansave == 0) 1088 { 1089 if(Otherwin) 1090 fault = new SpillNOther(4*Wstate<5:3>); 1091 else 1092 fault = new SpillNNormal(4*Wstate<2:0>); 1093 } 1094 else if(Cleanwin - Canrestore == 0) 1095 { 1096 fault = new CleanWindow; 1097 } 1098 else 1099 { 1100 Cwp = (Cwp + 1) % NWindows; 1101 Rd_next = Rs1 + Rs2_or_imm13; 1102 Cansave = Cansave - 1; 1103 Canrestore = Canrestore + 1; 1104 } 1105 }}); 1106 0x3D: restore({{ 1107 if(Canrestore == 0) 1108 { 1109 if(Otherwin) 1110 fault = new FillNOther(4*Wstate<5:3>); 1111 else 1112 fault = new FillNNormal(4*Wstate<2:0>); 1113 } 1114 else 1115 { 1116 Cwp = (Cwp - 1 + NWindows) % NWindows; 1117 Rd_prev = Rs1 + Rs2_or_imm13; 1118 Cansave = Cansave + 1; 1119 Canrestore = Canrestore - 1; 1120 } 1121 }}); 1122 0x3E: decode FCN { 1123 0x0: Priv::done({{ 1124 if(Tl == 0) 1125 return new IllegalInstruction; 1126 1127 Cwp = Tstate<4:0>; 1128 Pstate = Tstate<20:8>; 1129 Asi = Tstate<31:24>; 1130 Ccr = Tstate<39:32>; 1131 Gl = Tstate<42:40>; 1132 Hpstate = Htstate; 1133 NPC = Tnpc; 1134 NNPC = Tnpc + 4; 1135 Tl = Tl - 1; 1136 }}); 1137 0x1: Priv::retry({{ 1138 if(Tl == 0) 1139 return new IllegalInstruction; 1140 Cwp = Tstate<4:0>; 1141 Pstate = Tstate<20:8>; 1142 Asi = Tstate<31:24>; 1143 Ccr = Tstate<39:32>; 1144 Gl = Tstate<42:40>; 1145 Hpstate = Htstate; 1146 NPC = Tpc; 1147 NNPC = Tnpc; 1148 Tl = Tl - 1; 1149 }}); 1150 } 1151 } 1152 } 1153 0x3: decode OP3 { 1154 format Load { 1155 0x00: lduw({{Rd = Mem.uw;}}); 1156 0x01: ldub({{Rd = Mem.ub;}}); 1157 0x02: lduh({{Rd = Mem.uhw;}}); 1158 0x03: ldtw({{ 1159 RdLow = (Mem.tuw).a; 1160 RdHigh = (Mem.tuw).b; 1161 }}); 1162 } 1163 format Store { 1164 0x04: stw({{Mem.uw = Rd.sw;}}); 1165 0x05: stb({{Mem.ub = Rd.sb;}}); 1166 0x06: sth({{Mem.uhw = Rd.shw;}}); 1167 0x07: sttw({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}}); 1168 } 1169 format Load { 1170 0x08: ldsw({{Rd = (int32_t)Mem.sw;}}); 1171 0x09: ldsb({{Rd = (int8_t)Mem.sb;}}); 1172 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}}); 1173 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}}); 1174 } 1175 0x0D: Swap::ldstub({{Mem.ub = 0xFF;}}, 1176 {{ 1177 uint8_t tmp = mem_data; 1178 Rd.ub = tmp; 1179 }}, MEM_SWAP); 1180 0x0E: Store::stx({{Mem.udw = Rd}}); 1181 0x0F: Swap::swap({{Mem.uw = Rd.uw}}, 1182 {{ 1183 uint32_t tmp = mem_data; 1184 Rd.uw = tmp; 1185 }}, MEM_SWAP); 1186 format LoadAlt { 1187 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}}); 1188 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}}); 1189 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}}); 1190 0x13: decode EXT_ASI { 1191 //ASI_LDTD_AIUP 1192 0x22: TwinLoad::ldtx_aiup( 1193 {{RdLow.udw = (Mem.tudw).a; 1194 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1195 //ASI_LDTD_AIUS 1196 0x23: TwinLoad::ldtx_aius( 1197 {{RdLow.udw = (Mem.tudw).a; 1198 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1199 //ASI_QUAD_LDD 1200 0x24: TwinLoad::ldtx_quad_ldd( 1201 {{RdLow.udw = (Mem.tudw).a; 1202 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1203 //ASI_LDTX_REAL 1204 0x26: TwinLoad::ldtx_real( 1205 {{RdLow.udw = (Mem.tudw).a; 1206 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1207 //ASI_LDTX_N 1208 0x27: TwinLoad::ldtx_n( 1209 {{RdLow.udw = (Mem.tudw).a; 1210 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1211 //ASI_LDTX_AIUP_L 1212 0x2A: TwinLoad::ldtx_aiup_l( 1213 {{RdLow.udw = (Mem.tudw).a; 1214 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1215 //ASI_LDTX_AIUS_L 1216 0x2B: TwinLoad::ldtx_aius_l( 1217 {{RdLow.udw = (Mem.tudw).a; 1218 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1219 //ASI_LDTX_L 1220 0x2C: TwinLoad::ldtx_l( 1221 {{RdLow.udw = (Mem.tudw).a; 1222 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1223 //ASI_LDTX_REAL_L 1224 0x2E: TwinLoad::ldtx_real_l( 1225 {{RdLow.udw = (Mem.tudw).a; 1226 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1227 //ASI_LDTX_N_L 1228 0x2F: TwinLoad::ldtx_n_l( 1229 {{RdLow.udw = (Mem.tudw).a; 1230 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1231 //ASI_LDTX_P 1232 0xE2: TwinLoad::ldtx_p( 1233 {{RdLow.udw = (Mem.tudw).a; 1234 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1235 //ASI_LDTX_S 1236 0xE3: TwinLoad::ldtx_s( 1237 {{RdLow.udw = (Mem.tudw).a; 1238 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1239 //ASI_LDTX_PL 1240 0xEA: TwinLoad::ldtx_pl( 1241 {{RdLow.udw = (Mem.tudw).a; 1242 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1243 //ASI_LDTX_SL 1244 0xEB: TwinLoad::ldtx_sl( 1245 {{RdLow.udw = (Mem.tudw).a; 1246 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}}); 1247 default: ldtwa({{ 1248 RdLow = (Mem.tuw).a; 1249 RdHigh = (Mem.tuw).b; 1250 }}, {{EXT_ASI}}); 1251 } 1252 } 1253 format StoreAlt { 1254 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}}); 1255 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}}); 1256 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}}); 1257 0x17: sttwa({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}}); 1258 } 1259 format LoadAlt { 1260 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}}); 1261 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}}); 1262 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}}); 1263 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}}); 1264 } 1265 0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}}, 1266 {{ 1267 uint8_t tmp = mem_data; 1268 Rd.ub = tmp; 1269 }}, {{EXT_ASI}}, MEM_SWAP); 1270 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}}); 1271 0x1F: SwapAlt::swapa({{Mem.uw = Rd.uw}}, 1272 {{ 1273 uint32_t tmp = mem_data; 1274 Rd.uw = tmp; 1275 }}, {{EXT_ASI}}, MEM_SWAP); 1276 1277 format Trap { 1278 0x20: Load::ldf({{Frds.uw = Mem.uw;}}); 1279 0x21: decode RD { 1280 0x0: Load::ldfsr({{fault = checkFpEnableFault(xc); 1281 if (fault) 1282 return fault; 1283 Fsr = Mem.uw | Fsr<63:32>;}}); 1284 0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc); 1285 if (fault) 1286 return fault; 1287 Fsr = Mem.udw;}}); 1288 default: FailUnimpl::ldfsrOther(); 1289 } 1290 0x22: ldqf({{fault = new FpDisabled;}}); 1291 0x23: Load::lddf({{Frd.udw = Mem.udw;}}); 1292 0x24: Store::stf({{Mem.uw = Frds.uw;}}); 1293 0x25: decode RD { 1294 0x0: Store::stfsr({{fault = checkFpEnableFault(xc); 1295 if (fault) 1296 return fault; 1297 Mem.uw = Fsr<31:0>; 1298 Fsr = insertBits(Fsr,16,14,0);}}); 1299 0x1: Store::stxfsr({{fault = checkFpEnableFault(xc); 1300 if (fault) 1301 return fault; 1302 Mem.udw = Fsr; 1303 Fsr = insertBits(Fsr,16,14,0);}}); 1304 default: FailUnimpl::stfsrOther(); 1305 } 1306 0x26: stqf({{fault = new FpDisabled;}}); 1307 0x27: Store::stdf({{Mem.udw = Frd.udw;}}); 1308 0x2D: Nop::prefetch({{ }}); 1309 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}}); 1310 0x32: ldqfa({{fault = new FpDisabled;}}); 1311 format LoadAlt { 1312 0x33: decode EXT_ASI { 1313 //ASI_NUCLEUS 1314 0x04: FailUnimpl::lddfa_n(); 1315 //ASI_NUCLEUS_LITTLE 1316 0x0C: FailUnimpl::lddfa_nl(); 1317 //ASI_AS_IF_USER_PRIMARY 1318 0x10: FailUnimpl::lddfa_aiup(); 1319 //ASI_AS_IF_USER_PRIMARY_LITTLE 1320 0x18: FailUnimpl::lddfa_aiupl(); 1321 //ASI_AS_IF_USER_SECONDARY 1322 0x11: FailUnimpl::lddfa_aius(); 1323 //ASI_AS_IF_USER_SECONDARY_LITTLE 1324 0x19: FailUnimpl::lddfa_aiusl(); 1325 //ASI_REAL 1326 0x14: FailUnimpl::lddfa_real(); 1327 //ASI_REAL_LITTLE 1328 0x1C: FailUnimpl::lddfa_real_l(); 1329 //ASI_REAL_IO 1330 0x15: FailUnimpl::lddfa_real_io(); 1331 //ASI_REAL_IO_LITTLE 1332 0x1D: FailUnimpl::lddfa_real_io_l(); 1333 //ASI_PRIMARY 1334 0x80: FailUnimpl::lddfa_p(); 1335 //ASI_PRIMARY_LITTLE 1336 0x88: FailUnimpl::lddfa_pl(); 1337 //ASI_SECONDARY 1338 0x81: FailUnimpl::lddfa_s(); 1339 //ASI_SECONDARY_LITTLE 1340 0x89: FailUnimpl::lddfa_sl(); 1341 //ASI_PRIMARY_NO_FAULT 1342 0x82: FailUnimpl::lddfa_pnf(); 1343 //ASI_PRIMARY_NO_FAULT_LITTLE 1344 0x8A: FailUnimpl::lddfa_pnfl(); 1345 //ASI_SECONDARY_NO_FAULT 1346 0x83: FailUnimpl::lddfa_snf(); 1347 //ASI_SECONDARY_NO_FAULT_LITTLE 1348 0x8B: FailUnimpl::lddfa_snfl(); 1349 1350 format BlockLoad { 1351 // LDBLOCKF 1352 //ASI_BLOCK_AS_IF_USER_PRIMARY 1353 0x16: FailUnimpl::ldblockf_aiup(); 1354 //ASI_BLOCK_AS_IF_USER_SECONDARY 1355 0x17: FailUnimpl::ldblockf_aius(); 1356 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1357 0x1E: FailUnimpl::ldblockf_aiupl(); 1358 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1359 0x1F: FailUnimpl::ldblockf_aiusl(); 1360 //ASI_BLOCK_PRIMARY 1361 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}}); 1362 //ASI_BLOCK_SECONDARY 1363 0xF1: FailUnimpl::ldblockf_s(); 1364 //ASI_BLOCK_PRIMARY_LITTLE 1365 0xF8: FailUnimpl::ldblockf_pl(); 1366 //ASI_BLOCK_SECONDARY_LITTLE 1367 0xF9: FailUnimpl::ldblockf_sl(); 1368 } 1369 1370 //LDSHORTF 1371 //ASI_FL8_PRIMARY 1372 0xD0: FailUnimpl::ldshortf_8p(); 1373 //ASI_FL8_SECONDARY 1374 0xD1: FailUnimpl::ldshortf_8s(); 1375 //ASI_FL8_PRIMARY_LITTLE 1376 0xD8: FailUnimpl::ldshortf_8pl(); 1377 //ASI_FL8_SECONDARY_LITTLE 1378 0xD9: FailUnimpl::ldshortf_8sl(); 1379 //ASI_FL16_PRIMARY 1380 0xD2: FailUnimpl::ldshortf_16p(); 1381 //ASI_FL16_SECONDARY 1382 0xD3: FailUnimpl::ldshortf_16s(); 1383 //ASI_FL16_PRIMARY_LITTLE 1384 0xDA: FailUnimpl::ldshortf_16pl(); 1385 //ASI_FL16_SECONDARY_LITTLE 1386 0xDB: FailUnimpl::ldshortf_16sl(); 1387 //Not an ASI which is legal with lddfa 1388 default: Trap::lddfa_bad_asi( 1389 {{fault = new DataAccessException;}}); 1390 } 1391 } 1392 0x34: Store::stfa({{Mem.uw = Frds.uw;}}); 1393 0x36: stqfa({{fault = new FpDisabled;}}); 1394 format StoreAlt { 1395 0x37: decode EXT_ASI { 1396 //ASI_NUCLEUS 1397 0x04: FailUnimpl::stdfa_n(); 1398 //ASI_NUCLEUS_LITTLE 1399 0x0C: FailUnimpl::stdfa_nl(); 1400 //ASI_AS_IF_USER_PRIMARY 1401 0x10: FailUnimpl::stdfa_aiup(); 1402 //ASI_AS_IF_USER_PRIMARY_LITTLE 1403 0x18: FailUnimpl::stdfa_aiupl(); 1404 //ASI_AS_IF_USER_SECONDARY 1405 0x11: FailUnimpl::stdfa_aius(); 1406 //ASI_AS_IF_USER_SECONDARY_LITTLE 1407 0x19: FailUnimpl::stdfa_aiusl(); 1408 //ASI_REAL 1409 0x14: FailUnimpl::stdfa_real(); 1410 //ASI_REAL_LITTLE 1411 0x1C: FailUnimpl::stdfa_real_l(); 1412 //ASI_REAL_IO 1413 0x15: FailUnimpl::stdfa_real_io(); 1414 //ASI_REAL_IO_LITTLE 1415 0x1D: FailUnimpl::stdfa_real_io_l(); 1416 //ASI_PRIMARY 1417 0x80: FailUnimpl::stdfa_p(); 1418 //ASI_PRIMARY_LITTLE 1419 0x88: FailUnimpl::stdfa_pl(); 1420 //ASI_SECONDARY 1421 0x81: FailUnimpl::stdfa_s(); 1422 //ASI_SECONDARY_LITTLE 1423 0x89: FailUnimpl::stdfa_sl(); 1424 //ASI_PRIMARY_NO_FAULT 1425 0x82: FailUnimpl::stdfa_pnf(); 1426 //ASI_PRIMARY_NO_FAULT_LITTLE 1427 0x8A: FailUnimpl::stdfa_pnfl(); 1428 //ASI_SECONDARY_NO_FAULT 1429 0x83: FailUnimpl::stdfa_snf(); 1430 //ASI_SECONDARY_NO_FAULT_LITTLE 1431 0x8B: FailUnimpl::stdfa_snfl(); 1432 1433 format BlockStore { 1434 // STBLOCKF 1435 //ASI_BLOCK_AS_IF_USER_PRIMARY 1436 0x16: FailUnimpl::stblockf_aiup(); 1437 //ASI_BLOCK_AS_IF_USER_SECONDARY 1438 0x17: FailUnimpl::stblockf_aius(); 1439 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE 1440 0x1E: FailUnimpl::stblockf_aiupl(); 1441 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 1442 0x1F: FailUnimpl::stblockf_aiusl(); 1443 //ASI_BLOCK_PRIMARY 1444 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}}); 1445 //ASI_BLOCK_SECONDARY 1446 0xF1: FailUnimpl::stblockf_s(); 1447 //ASI_BLOCK_PRIMARY_LITTLE 1448 0xF8: FailUnimpl::stblockf_pl(); 1449 //ASI_BLOCK_SECONDARY_LITTLE 1450 0xF9: FailUnimpl::stblockf_sl(); 1451 } 1452 1453 //STSHORTF 1454 //ASI_FL8_PRIMARY 1455 0xD0: FailUnimpl::stshortf_8p(); 1456 //ASI_FL8_SECONDARY 1457 0xD1: FailUnimpl::stshortf_8s(); 1458 //ASI_FL8_PRIMARY_LITTLE 1459 0xD8: FailUnimpl::stshortf_8pl(); 1460 //ASI_FL8_SECONDARY_LITTLE 1461 0xD9: FailUnimpl::stshortf_8sl(); 1462 //ASI_FL16_PRIMARY 1463 0xD2: FailUnimpl::stshortf_16p(); 1464 //ASI_FL16_SECONDARY 1465 0xD3: FailUnimpl::stshortf_16s(); 1466 //ASI_FL16_PRIMARY_LITTLE 1467 0xDA: FailUnimpl::stshortf_16pl(); 1468 //ASI_FL16_SECONDARY_LITTLE 1469 0xDB: FailUnimpl::stshortf_16sl(); 1470 //Not an ASI which is legal with lddfa 1471 default: Trap::stdfa_bad_asi( 1472 {{fault = new DataAccessException;}}); 1473 } 1474 } 1475 0x3C: CasAlt::casa({{ 1476 mem_data = htog(Rs2.uw); 1477 Mem.uw = Rd.uw;}}, 1478 {{ 1479 uint32_t tmp = mem_data; 1480 Rd.uw = tmp; 1481 }}, {{EXT_ASI}}, MEM_SWAP_COND); 1482 0x3D: Nop::prefetcha({{ }}); 1483 0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2); 1484 Mem.udw = Rd.udw; }}, 1485 {{ Rd.udw = mem_data; }}, {{EXT_ASI}}, MEM_SWAP_COND); 1486 } 1487 } 1488} |