1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 //bpcc
45 0x1: decode COND2
46 {
47 //Branch Always
48 0x8: bpa(19, annul_code={{
49 NPC = xc->readPC() + disp;
50 NNPC = NPC + 4;
49 SparcISA::PCState pc = PCS;
50 pc.npc(pc.pc() + disp);
51 pc.nnpc(pc.npc() + 4);
52 PCS = pc;
53 }});
54 //Branch Never
55 0x0: bpn(19, {{;}},
56 annul_code={{
55 NNPC = NPC + 8;
56 NPC = NPC + 4;
57 SparcISA::PCState pc = PCS;
58 pc.nnpc(pc.npc() + 8);
59 pc.npc(pc.npc() + 4);
60 PCS = pc;
61 }});
62 default: decode BPCC
63 {
64 0x0: bpcci(19, test={{passesCondition(Ccr<3:0>, COND2)}});
65 0x2: bpccx(19, test={{passesCondition(Ccr<7:4>, COND2)}});
66 }
67 }
68 //bicc
69 0x2: decode COND2
70 {
71 //Branch Always
72 0x8: ba(22, annul_code={{
69 NPC = xc->readPC() + disp;
70 NNPC = NPC + 4;
73 SparcISA::PCState pc = PCS;
74 pc.npc(pc.pc() + disp);
75 pc.nnpc(pc.npc() + 4);
76 PCS = pc;
77 }});
78 //Branch Never
79 0x0: bn(22, {{;}},
80 annul_code={{
75 NNPC = NPC + 8;
76 NPC = NPC + 4;
81 SparcISA::PCState pc = PCS;
82 pc.nnpc(pc.npc() + 8);
83 pc.npc(pc.npc() + 4);
84 PCS = pc;
85 }});
86 default: bicc(22, test={{passesCondition(Ccr<3:0>, COND2)}});
87 }
88 }
89 0x3: decode RCOND2
90 {
91 format BranchSplit
92 {

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100 }
101 //SETHI (or NOP if rd == 0 and imm == 0)
102 0x4: SetHi::sethi({{Rd.udw = imm;}});
103 //fbpfcc
104 0x5: decode COND2 {
105 format BranchN {
106 //Branch Always
107 0x8: fbpa(22, annul_code={{
100 NPC = xc->readPC() + disp;
101 NNPC = NPC + 4;
108 SparcISA::PCState pc = PCS;
109 pc.npc(pc.pc() + disp);
110 pc.nnpc(pc.npc() + 4);
111 PCS = pc;
112 }});
113 //Branch Never
114 0x0: fbpn(22, {{;}},
115 annul_code={{
106 NNPC = NPC + 8;
107 NPC = NPC + 4;
116 SparcISA::PCState pc = PCS;
117 pc.nnpc(pc.npc() + 8);
118 pc.npc(pc.npc() + 4);
119 PCS = pc;
120 }});
121 default: decode BPCC {
122 0x0: fbpfcc0(19, test=
123 {{passesFpCondition(Fsr<11:10>, COND2)}});
124 0x1: fbpfcc1(19, test=
125 {{passesFpCondition(Fsr<33:32>, COND2)}});
126 0x2: fbpfcc2(19, test=
127 {{passesFpCondition(Fsr<35:34>, COND2)}});
128 0x3: fbpfcc3(19, test=
129 {{passesFpCondition(Fsr<37:36>, COND2)}});
130 }
131 }
132 }
133 //fbfcc
134 0x6: decode COND2 {
135 format BranchN {
136 //Branch Always
137 0x8: fba(22, annul_code={{
126 NPC = xc->readPC() + disp;
127 NNPC = NPC + 4;
138 SparcISA::PCState pc = PCS;
139 pc.npc(pc.pc() + disp);
140 pc.nnpc(pc.npc() + 4);
141 PCS = pc;
142 }});
143 //Branch Never
144 0x0: fbn(22, {{;}},
145 annul_code={{
132 NNPC = NPC + 8;
133 NPC = NPC + 4;
146 SparcISA::PCState pc = PCS;
147 pc.nnpc(pc.npc() + 8);
148 pc.npc(pc.npc() + 4);
149 PCS = pc;
150 }});
151 default: fbfcc(22, test=
152 {{passesFpCondition(Fsr<11:10>, COND2)}});
153 }
154 }
155 }
156 0x1: BranchN::call(30, {{
157 SparcISA::PCState pc = PCS;
158 if (Pstate<3:>)
142 R15 = (xc->readPC())<31:0>;
159 R15 = (pc.pc())<31:0>;
160 else
144 R15 = xc->readPC();
145 NNPC = R15 + disp;
161 R15 = pc.pc();
162 pc.nnpc(R15 + disp);
163 PCS = pc;
164 }});
165 0x2: decode OP3 {
166 format IntOp {
167 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
168 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
169 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
170 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
171 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});

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329 }
330 0x28: decode RS1 {
331 0x00: NoPriv::rdy({{Rd = Y<31:0>;}});
332 //1 should cause an illegal instruction exception
333 0x02: NoPriv::rdccr({{Rd = Ccr;}});
334 0x03: NoPriv::rdasi({{Rd = Asi;}});
335 0x04: Priv::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
336 0x05: NoPriv::rdpc({{
337 SparcISA::PCState pc = PCS;
338 if(Pstate<3:>)
320 Rd = (xc->readPC())<31:0>;
339 Rd = (pc.pc())<31:0>;
340 else
322 Rd = xc->readPC();}});
341 Rd = pc.pc();
342 }});
343 0x06: NoPriv::rdfprs({{
344 //Wait for all fpops to finish.
345 Rd = Fprs;
346 }});
347 //7-14 should cause an illegal instruction exception
348 0x0F: decode I {
349 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp);
350 0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp);

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988 0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0);
989 }}, No_OpClass, IsNonSpeculative);
990 0x50: m5readfile({{
991 O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2);
992 }}, IsNonSpeculative);
993 0x51: m5break({{PseudoInst::debugbreak(xc->tcBase());
994 }}, IsNonSpeculative);
995 0x54: m5panic({{
976 panic("M5 panic instruction called at pc=%#x.", xc->readPC());
996 SparcISA::PCState pc = PCS;
997 panic("M5 panic instruction called at pc=%#x.", pc.pc());
998 }}, No_OpClass, IsNonSpeculative);
999 }
1000#endif
1001 default: Trap::impdep2({{fault = new IllegalInstruction;}});
1002 }
1003 0x38: Branch::jmpl({{
1004 Addr target = Rs1 + Rs2_or_imm13;
1005 if(target & 0x3)
1006 fault = new MemAddressNotAligned;
1007 else
1008 {
1009 SparcISA::PCState pc = PCS;
1010 if (Pstate<3:>)
989 Rd = (xc->readPC())<31:0>;
1011 Rd = (pc.pc())<31:0>;
1012 else
991 Rd = xc->readPC();
992 NNPC = target;
1013 Rd = pc.pc();
1014 pc.nnpc(target);
1015 PCS = pc;
1016 }
1017 }});
1018 0x39: Branch::return({{
1019 Addr target = Rs1 + Rs2_or_imm13;
1020 if(fault == NoFault)
1021 {
1022 //Check for fills which are higher priority than alignment
1023 //faults.

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1028 else
1029 fault = new FillNNormal(4*Wstate<2:0>);
1030 }
1031 //Check for alignment faults
1032 else if(target & 0x3)
1033 fault = new MemAddressNotAligned;
1034 else
1035 {
1013 NNPC = target;
1036 SparcISA::PCState pc = PCS;
1037 pc.nnpc(target);
1038 PCS = pc;
1039 Cwp = (Cwp - 1 + NWindows) % NWindows;
1040 Cansave = Cansave + 1;
1041 Canrestore = Canrestore - 1;
1042 }
1043 }
1044 }});
1045 0x3A: decode CC
1046 {

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1102 0x3E: decode FCN {
1103 0x0: Priv::done({{
1104 Cwp = Tstate<4:0>;
1105 Pstate = Tstate<20:8>;
1106 Asi = Tstate<31:24>;
1107 Ccr = Tstate<39:32>;
1108 Gl = Tstate<42:40>;
1109 Hpstate = Htstate;
1085 NPC = Tnpc;
1086 NNPC = Tnpc + 4;
1110 SparcISA::PCState pc = PCS;
1111 pc.npc(Tnpc);
1112 pc.nnpc(Tnpc + 4);
1113 PCS = pc;
1114 Tl = Tl - 1;
1115 }}, checkTl=true);
1116 0x1: Priv::retry({{
1117 Cwp = Tstate<4:0>;
1118 Pstate = Tstate<20:8>;
1119 Asi = Tstate<31:24>;
1120 Ccr = Tstate<39:32>;
1121 Gl = Tstate<42:40>;
1122 Hpstate = Htstate;
1096 NPC = Tpc;
1097 NNPC = Tnpc;
1123 SparcISA::PCState pc = PCS;
1124 pc.npc(Tpc);
1125 pc.nnpc(Tnpc);
1126 PCS = pc;
1127 Tl = Tl - 1;
1128 }}, checkTl=true);
1129 }
1130 }
1131 }
1132 0x3: decode OP3 {
1133 format Load {
1134 0x00: lduw({{Rd = Mem.uw;}});

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