40c40
< //Throw an illegal instruction acception
---
> // Throw an illegal instruction acception
44c44
< //bpcc
---
> // bpcc
47c47
< //Branch Always
---
> // Branch Always
54c54
< //Branch Never
---
> // Branch Never
68c68
< //bicc
---
> // bicc
71c71
< //Branch Always
---
> // Branch Always
78c78
< //Branch Never
---
> // Branch Never
101c101
< //SETHI (or NOP if rd == 0 and imm == 0)
---
> // SETHI (or NOP if rd == 0 and imm == 0)
103c103
< //fbpfcc
---
> // fbpfcc
106c106
< //Branch Always
---
> // Branch Always
113c113
< //Branch Never
---
> // Branch Never
133c133
< //fbfcc
---
> // fbfcc
136c136
< //Branch Always
---
> // Branch Always
143c143
< //Branch Never
---
> // Branch Never
187,188c187,190
< if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
< else Rd.udw = Rs1.udw / Rs2_or_imm13;
---
> if (Rs2_or_imm13 == 0)
> fault = new DivisionByZero;
> else
> Rd.udw = Rs1.udw / Rs2_or_imm13;
191,193c193,195
< if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
< else
< {
---
> if (Rs2_or_imm13 == 0) {
> fault = new DivisionByZero;
> } else {
195c197
< if(Rd.udw >> 32 != 0)
---
> if (Rd.udw >> 32 != 0)
200c202
< if(Rs2_or_imm13.sdw == 0)
---
> if (Rs2_or_imm13.sdw == 0) {
202,205c204,208
< else
< {
< Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
< if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max())
---
> } else {
> Rd.udw = ((int64_t)((Y << 32) |
> Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
> if ((int64_t)Rd.udw >=
> std::numeric_limits<int32_t>::max()) {
207c210,211
< else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min())
---
> } else if ((int64_t)Rd.udw <=
> std::numeric_limits<int32_t>::min()) {
208a213
> }
244,245c249,252
< if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
< else Rd = Rs1.udw / Rs2_or_imm13.udw;}});
---
> if (Rs2_or_imm13.udw == 0)
> fault = new DivisionByZero;
> else
> Rd = Rs1.udw / Rs2_or_imm13.udw;}});
250,252c257,259
< if(val2 == 0) fault = new DivisionByZero;
< else
< {
---
> if (val2 == 0) {
> fault = new DivisionByZero;
> } else {
255,256c262,265
< if(overflow) Rd = resTemp = 0xFFFFFFFF;
< else Rd = resTemp;
---
> if (overflow)
> Rd = resTemp = 0xFFFFFFFF;
> else
> Rd = resTemp;
262,264c271,273
< if(val2 == 0) fault = new DivisionByZero;
< else
< {
---
> if (val2 == 0) {
> fault = new DivisionByZero;
> } else {
268,269c277,280
< if(overflow) Rd = 0x7FFFFFFF;
< else if(underflow) Rd = ULL(0xFFFFFFFF80000000);
---
> if (overflow)
> Rd = 0x7FFFFFFF;
> else if (underflow)
> Rd = ULL(0xFFFFFFFF80000000);
291c302,303
< if(overflow) fault = new TagOverflow;
---
> if (overflow)
> fault = new TagOverflow;
298c310,311
< if(overflow) fault = new TagOverflow;
---
> if (overflow)
> fault = new TagOverflow;
303c316
< //Step 1
---
> // Step 1
305c318
< //Step 2
---
> // Step 2
308c321
< //Step 3
---
> // Step 3
312c325
< //Steps 4 & 5
---
> // Steps 4 & 5
332c345
< //1 should cause an illegal instruction exception
---
> // 1 should cause an illegal instruction exception
338c351
< if(Pstate<3:>)
---
> if (Pstate<3:>)
344c357
< //Wait for all fpops to finish.
---
> // Wait for all fpops to finish.
347c360
< //7-14 should cause an illegal instruction exception
---
> // 7-14 should cause an illegal instruction exception
354c367
< //0x12 should cause an illegal instruction exception
---
> // 0x12 should cause an illegal instruction exception
361c374
< //0x14-0x15 should cause an illegal instruction exception
---
> // 0x14-0x15 should cause an illegal instruction exception
367c380
< if(Pstate<2:> && !Hpstate<2:>)
---
> if (Pstate<2:> && !Hpstate<2:>)
372,374c385,387
< //0x1A is supposed to be reserved, but it reads the strand
< //status register.
< //0x1B-0x1F should cause an illegal instruction exception
---
> // 0x1A is supposed to be reserved, but it reads the strand
> // status register.
> // 0x1B-0x1F should cause an illegal instruction exception
379c392
< //0x02 should cause an illegal instruction exception
---
> // 0x02 should cause an illegal instruction exception
381c394
< //0x04 should cause an illegal instruction exception
---
> // 0x04 should cause an illegal instruction exception
384c397
< //0x07-0x1E should cause an illegal instruction exception
---
> // 0x07-0x1E should cause an illegal instruction exception
403c416
< //0x0F should cause an illegal instruction exception
---
> // 0x0F should cause an illegal instruction exception
405c418
< //0x11-0x1F should cause an illegal instruction exception
---
> // 0x11-0x1F should cause an illegal instruction exception
408,410c421,422
< if(NWindows - 2 - Cansave != 0)
< {
< if(Otherwin)
---
> if (NWindows - 2 - Cansave != 0) {
> if (Otherwin)
421c433
< if(passesCondition(Fsr<11:10>, COND4))
---
> if (passesCondition(Fsr<11:10>, COND4))
427c439
< if(passesCondition(Fsr<33:32>, COND4))
---
> if (passesCondition(Fsr<33:32>, COND4))
433c445
< if(passesCondition(Fsr<35:34>, COND4))
---
> if (passesCondition(Fsr<35:34>, COND4))
439c451
< if(passesCondition(Fsr<37:36>, COND4))
---
> if (passesCondition(Fsr<37:36>, COND4))
448c460
< if(passesCondition(Ccr<3:0>, COND4))
---
> if (passesCondition(Ccr<3:0>, COND4))
454c466
< if(passesCondition(Ccr<7:4>, COND4))
---
> if (passesCondition(Ccr<7:4>, COND4))
462,463c474,477
< if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
< else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
---
> if (Rs2_or_imm13.sdw == 0)
> fault = new DivisionByZero;
> else
> Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
477c491
< //0x01 should cause an illegal instruction exception
---
> // 0x01 should cause an illegal instruction exception
480c494
< //0x04-0x05 should cause an illegal instruction exception
---
> // 0x04-0x05 should cause an illegal instruction exception
482c496
< //0x07-0x0E should cause an illegal instruction exception
---
> // 0x07-0x0E should cause an illegal instruction exception
486c500
< //0x12 should cause an illegal instruction exception
---
> // 0x12 should cause an illegal instruction exception
488c502
< if(Fprs<2:> == 0 || Pstate<4:> == 0)
---
> if (Fprs<2:> == 0 || Pstate<4:> == 0)
497c511
< if(!Hpstate<2:>)
---
> if (!Hpstate<2:>)
505,507c519,521
< //0x1A is supposed to be reserved, but it writes the strand
< //status register.
< //0x1B-0x1F should cause an illegal instruction exception
---
> // 0x1A is supposed to be reserved, but it writes the strand
> // status register.
> // 0x1B-0x1F should cause an illegal instruction exception
514c528
< if(Otherwin == 0)
---
> if (Otherwin == 0)
523c537
< if(Otherwin == 0)
---
> if (Otherwin == 0)
528c542
< if(Cleanwin < NWindows - 1)
---
> if (Cleanwin < NWindows - 1)
545c559
< if(Pstate<2:> && !Hpstate<2:>)
---
> if (Pstate<2:> && !Hpstate<2:>)
557c571
< //0x0F should cause an illegal instruction exception
---
> // 0x0F should cause an illegal instruction exception
559c573
< if(Pstate<2:> && !Hpstate<2:>)
---
> if (Pstate<2:> && !Hpstate<2:>)
564c578
< //0x11-0x1F should cause an illegal instruction exception
---
> // 0x11-0x1F should cause an illegal instruction exception
570c584
< //0x02 should cause an illegal instruction exception
---
> // 0x02 should cause an illegal instruction exception
572c586
< //0x04 should cause an illegal instruction exception
---
> // 0x04 should cause an illegal instruction exception
574c588
< //0x06-0x01D should cause an illegal instruction exception
---
> // 0x06-0x01D should cause an illegal instruction exception
639c653
< if(passesFpCondition(Fsr<11:10>, COND4))
---
> if (passesFpCondition(Fsr<11:10>, COND4))
645c659
< if(passesFpCondition(Fsr<11:10>, COND4))
---
> if (passesFpCondition(Fsr<11:10>, COND4))
652c666
< if(Rs1 == 0)
---
> if (Rs1 == 0)
658c672
< if(Rs1 == 0)
---
> if (Rs1 == 0)
665c679
< if(passesFpCondition(Fsr<33:32>, COND4))
---
> if (passesFpCondition(Fsr<33:32>, COND4))
671c685
< if(passesFpCondition(Fsr<33:32>, COND4))
---
> if (passesFpCondition(Fsr<33:32>, COND4))
678c692
< if(Rs1 <= 0)
---
> if (Rs1 <= 0)
684c698
< if(Rs1 <= 0)
---
> if (Rs1 <= 0)
692c706
< if(isnan(Frs1s) || isnan(Frs2s))
---
> if (isnan(Frs1s) || isnan(Frs2s))
694c708
< else if(Frs1s < Frs2s)
---
> else if (Frs1s < Frs2s)
696c710
< else if(Frs1s > Frs2s)
---
> else if (Frs1s > Frs2s)
701c715
< if(FCMPCC)
---
> if (FCMPCC)
707c721
< if(isnan(Frs1) || isnan(Frs2))
---
> if (isnan(Frs1) || isnan(Frs2))
709c723
< else if(Frs1 < Frs2)
---
> else if (Frs1 < Frs2)
711c725
< else if(Frs1 > Frs2)
---
> else if (Frs1 > Frs2)
716c730
< if(FCMPCC)
---
> if (FCMPCC)
723c737
< if(isnan(Frs1s) || isnan(Frs2s))
---
> if (isnan(Frs1s) || isnan(Frs2s))
725c739
< if(Frs1s < Frs2s)
---
> if (Frs1s < Frs2s)
727c741
< else if(Frs1s > Frs2s)
---
> else if (Frs1s > Frs2s)
730c744
< if(FCMPCC)
---
> if (FCMPCC)
736c750
< if(isnan(Frs1) || isnan(Frs2))
---
> if (isnan(Frs1) || isnan(Frs2))
738c752
< if(Frs1 < Frs2)
---
> if (Frs1 < Frs2)
740c754
< else if(Frs1 > Frs2)
---
> else if (Frs1 > Frs2)
743c757
< if(FCMPCC)
---
> if (FCMPCC)
749c763
< if(Rs1 < 0)
---
> if (Rs1 < 0)
755c769
< if(Rs1 < 0)
---
> if (Rs1 < 0)
762c776
< if(passesFpCondition(Fsr<35:34>, COND4))
---
> if (passesFpCondition(Fsr<35:34>, COND4))
768c782
< if(passesFpCondition(Fsr<35:34>, COND4))
---
> if (passesFpCondition(Fsr<35:34>, COND4))
775c789
< if(Rs1 != 0)
---
> if (Rs1 != 0)
781c795
< if(Rs1 != 0)
---
> if (Rs1 != 0)
788c802
< if(passesFpCondition(Fsr<37:36>, COND4))
---
> if (passesFpCondition(Fsr<37:36>, COND4))
794c808
< if(passesFpCondition(Fsr<37:36>, COND4))
---
> if (passesFpCondition(Fsr<37:36>, COND4))
801c815
< if(Rs1 > 0)
---
> if (Rs1 > 0)
807c821
< if(Rs1 > 0)
---
> if (Rs1 > 0)
814c828
< if(Rs1 >= 0)
---
> if (Rs1 >= 0)
820c834
< if(Rs1 >= 0)
---
> if (Rs1 >= 0)
827c841
< if(passesCondition(Ccr<3:0>, COND4))
---
> if (passesCondition(Ccr<3:0>, COND4))
833c847
< if(passesCondition(Ccr<3:0>, COND4))
---
> if (passesCondition(Ccr<3:0>, COND4))
840c854
< if(passesCondition(Ccr<7:4>, COND4))
---
> if (passesCondition(Ccr<7:4>, COND4))
846c860
< if(passesCondition(Ccr<7:4>, COND4))
---
> if (passesCondition(Ccr<7:4>, COND4))
855,856c869,870
< //This used to be just impdep1, but now it's a whole bunch
< //of instructions
---
> // This used to be just impdep1, but now it's a whole bunch
> // of instructions
906,926c920,939
< //Some special cases need to be split out, first
< //because they're the most likely to be used, and
< //second because otherwise, we end up shifting by
< //greater than the width of the type being shifted,
< //namely 64, which produces undefined results according
< //to the C standard.
< switch(Gsr<2:0>)
< {
< case 0:
< Frd.udw = msbX;
< break;
< case 8:
< Frd.udw = lsbX;
< break;
< default:
< uint64_t msbShift = Gsr<2:0> * 8;
< uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
< uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
< uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
< Frd.udw = ((msbX & msbMask) << msbShift) |
< ((lsbX & lsbMask) >> lsbShift);
---
> // Some special cases need to be split out, first
> // because they're the most likely to be used, and
> // second because otherwise, we end up shifting by
> // greater than the width of the type being shifted,
> // namely 64, which produces undefined results
> // according to the C standard.
> switch (Gsr<2:0>) {
> case 0:
> Frd.udw = msbX;
> break;
> case 8:
> Frd.udw = lsbX;
> break;
> default:
> uint64_t msbShift = Gsr<2:0> * 8;
> uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
> uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
> uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
> Frd.udw = ((msbX & msbMask) << msbShift) |
> ((lsbX & lsbMask) >> lsbShift);
1005c1018
< if(target & 0x3)
---
> if (target & 0x3) {
1007,1008c1020
< else
< {
---
> } else {
1020,1026c1032,1036
< if(fault == NoFault)
< {
< //Check for fills which are higher priority than alignment
< //faults.
< if(Canrestore == 0)
< {
< if(Otherwin)
---
> if (fault == NoFault) {
> // Check for fills which are higher priority than alignment
> // faults.
> if (Canrestore == 0) {
> if (Otherwin)
1030,1032c1040
< }
< //Check for alignment faults
< else if(target & 0x3)
---
> } else if (target & 0x3) { // Check for alignment faults
1034,1035c1042
< else
< {
---
> } else {
1048,1049c1055
< if(passesCondition(Ccr<3:0>, COND2))
< {
---
> if (passesCondition(Ccr<3:0>, COND2)) {
1056,1057c1062
< if(passesCondition(Ccr<7:4>, COND2))
< {
---
> if (passesCondition(Ccr<7:4>, COND2)) {
1067,1069c1072,1073
< if(Cansave == 0)
< {
< if(Otherwin)
---
> if (Cansave == 0) {
> if (Otherwin)
1073,1075c1077
< }
< else if(Cleanwin - Canrestore == 0)
< {
---
> } else if (Cleanwin - Canrestore == 0) {
1077,1079c1079
< }
< else
< {
---
> } else {
1087,1089c1087,1088
< if(Canrestore == 0)
< {
< if(Otherwin)
---
> if (Canrestore == 0) {
> if (Otherwin)
1093,1095c1092
< }
< else
< {
---
> } else {
1147,1150c1144,1147
< //This temporary needs to be here so that the parser
< //will correctly identify this instruction as a store.
< //It's probably either the parenthesis or referencing
< //the member variable that throws confuses it.
---
> // This temporary needs to be here so that the parser
> // will correctly identify this instruction as a store.
> // It's probably either the parenthesis or referencing
> // the member variable that throws confuses it.
1179c1176
< //ASI_LDTD_AIUP
---
> // ASI_LDTD_AIUP
1183c1180
< //ASI_LDTD_AIUS
---
> // ASI_LDTD_AIUS
1187c1184
< //ASI_QUAD_LDD
---
> // ASI_QUAD_LDD
1191c1188
< //ASI_LDTX_REAL
---
> // ASI_LDTX_REAL
1195c1192
< //ASI_LDTX_N
---
> // ASI_LDTX_N
1199c1196
< //ASI_LDTX_AIUP_L
---
> // ASI_LDTX_AIUP_L
1203c1200
< //ASI_LDTX_AIUS_L
---
> // ASI_LDTX_AIUS_L
1207c1204
< //ASI_LDTX_L
---
> // ASI_LDTX_L
1211c1208
< //ASI_LDTX_REAL_L
---
> // ASI_LDTX_REAL_L
1215c1212
< //ASI_LDTX_N_L
---
> // ASI_LDTX_N_L
1219c1216
< //ASI_LDTX_P
---
> // ASI_LDTX_P
1223c1220
< //ASI_LDTX_S
---
> // ASI_LDTX_S
1227c1224
< //ASI_LDTX_PL
---
> // ASI_LDTX_PL
1231c1228
< //ASI_LDTX_SL
---
> // ASI_LDTX_SL
1245,1248c1242,1245
< //This temporary needs to be here so that the parser
< //will correctly identify this instruction as a store.
< //It's probably either the parenthesis or referencing
< //the member variable that throws confuses it.
---
> // This temporary needs to be here so that the parser
> // will correctly identify this instruction as a store.
> // It's probably either the parenthesis or referencing
> // the member variable that throws confuses it.
1307c1304
< //ASI_NUCLEUS
---
> // ASI_NUCLEUS
1309c1306
< //ASI_NUCLEUS_LITTLE
---
> // ASI_NUCLEUS_LITTLE
1311c1308
< //ASI_AS_IF_USER_PRIMARY
---
> // ASI_AS_IF_USER_PRIMARY
1313c1310
< //ASI_AS_IF_USER_PRIMARY_LITTLE
---
> // ASI_AS_IF_USER_PRIMARY_LITTLE
1315c1312
< //ASI_AS_IF_USER_SECONDARY
---
> // ASI_AS_IF_USER_SECONDARY
1317c1314
< //ASI_AS_IF_USER_SECONDARY_LITTLE
---
> // ASI_AS_IF_USER_SECONDARY_LITTLE
1319c1316
< //ASI_REAL
---
> // ASI_REAL
1321c1318
< //ASI_REAL_LITTLE
---
> // ASI_REAL_LITTLE
1323c1320
< //ASI_REAL_IO
---
> // ASI_REAL_IO
1325c1322
< //ASI_REAL_IO_LITTLE
---
> // ASI_REAL_IO_LITTLE
1327c1324
< //ASI_PRIMARY
---
> // ASI_PRIMARY
1329c1326
< //ASI_PRIMARY_LITTLE
---
> // ASI_PRIMARY_LITTLE
1331c1328
< //ASI_SECONDARY
---
> // ASI_SECONDARY
1333c1330
< //ASI_SECONDARY_LITTLE
---
> // ASI_SECONDARY_LITTLE
1335c1332
< //ASI_PRIMARY_NO_FAULT
---
> // ASI_PRIMARY_NO_FAULT
1337c1334
< //ASI_PRIMARY_NO_FAULT_LITTLE
---
> // ASI_PRIMARY_NO_FAULT_LITTLE
1339c1336
< //ASI_SECONDARY_NO_FAULT
---
> // ASI_SECONDARY_NO_FAULT
1341c1338
< //ASI_SECONDARY_NO_FAULT_LITTLE
---
> // ASI_SECONDARY_NO_FAULT_LITTLE
1346c1343
< //ASI_BLOCK_AS_IF_USER_PRIMARY
---
> // ASI_BLOCK_AS_IF_USER_PRIMARY
1348c1345
< //ASI_BLOCK_AS_IF_USER_SECONDARY
---
> // ASI_BLOCK_AS_IF_USER_SECONDARY
1350c1347
< //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
---
> // ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1352c1349
< //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
---
> // ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1354c1351
< //ASI_BLOCK_PRIMARY
---
> // ASI_BLOCK_PRIMARY
1356c1353
< //ASI_BLOCK_SECONDARY
---
> // ASI_BLOCK_SECONDARY
1358c1355
< //ASI_BLOCK_PRIMARY_LITTLE
---
> // ASI_BLOCK_PRIMARY_LITTLE
1360c1357
< //ASI_BLOCK_SECONDARY_LITTLE
---
> // ASI_BLOCK_SECONDARY_LITTLE
1364,1365c1361,1362
< //LDSHORTF
< //ASI_FL8_PRIMARY
---
> // LDSHORTF
> // ASI_FL8_PRIMARY
1367c1364
< //ASI_FL8_SECONDARY
---
> // ASI_FL8_SECONDARY
1369c1366
< //ASI_FL8_PRIMARY_LITTLE
---
> // ASI_FL8_PRIMARY_LITTLE
1371c1368
< //ASI_FL8_SECONDARY_LITTLE
---
> // ASI_FL8_SECONDARY_LITTLE
1373c1370
< //ASI_FL16_PRIMARY
---
> // ASI_FL16_PRIMARY
1375c1372
< //ASI_FL16_SECONDARY
---
> // ASI_FL16_SECONDARY
1377c1374
< //ASI_FL16_PRIMARY_LITTLE
---
> // ASI_FL16_PRIMARY_LITTLE
1379c1376
< //ASI_FL16_SECONDARY_LITTLE
---
> // ASI_FL16_SECONDARY_LITTLE
1381c1378
< //Not an ASI which is legal with lddfa
---
> // Not an ASI which is legal with lddfa
1390c1387
< //ASI_NUCLEUS
---
> // ASI_NUCLEUS
1392c1389
< //ASI_NUCLEUS_LITTLE
---
> // ASI_NUCLEUS_LITTLE
1394c1391
< //ASI_AS_IF_USER_PRIMARY
---
> // ASI_AS_IF_USER_PRIMARY
1396c1393
< //ASI_AS_IF_USER_PRIMARY_LITTLE
---
> // ASI_AS_IF_USER_PRIMARY_LITTLE
1398c1395
< //ASI_AS_IF_USER_SECONDARY
---
> // ASI_AS_IF_USER_SECONDARY
1400c1397
< //ASI_AS_IF_USER_SECONDARY_LITTLE
---
> // ASI_AS_IF_USER_SECONDARY_LITTLE
1402c1399
< //ASI_REAL
---
> // ASI_REAL
1404c1401
< //ASI_REAL_LITTLE
---
> // ASI_REAL_LITTLE
1406c1403
< //ASI_REAL_IO
---
> // ASI_REAL_IO
1408c1405
< //ASI_REAL_IO_LITTLE
---
> // ASI_REAL_IO_LITTLE
1410c1407
< //ASI_PRIMARY
---
> // ASI_PRIMARY
1412c1409
< //ASI_PRIMARY_LITTLE
---
> // ASI_PRIMARY_LITTLE
1414c1411
< //ASI_SECONDARY
---
> // ASI_SECONDARY
1416c1413
< //ASI_SECONDARY_LITTLE
---
> // ASI_SECONDARY_LITTLE
1418c1415
< //ASI_PRIMARY_NO_FAULT
---
> // ASI_PRIMARY_NO_FAULT
1420c1417
< //ASI_PRIMARY_NO_FAULT_LITTLE
---
> // ASI_PRIMARY_NO_FAULT_LITTLE
1422c1419
< //ASI_SECONDARY_NO_FAULT
---
> // ASI_SECONDARY_NO_FAULT
1424c1421
< //ASI_SECONDARY_NO_FAULT_LITTLE
---
> // ASI_SECONDARY_NO_FAULT_LITTLE
1429c1426
< //ASI_BLOCK_AS_IF_USER_PRIMARY
---
> // ASI_BLOCK_AS_IF_USER_PRIMARY
1431c1428
< //ASI_BLOCK_AS_IF_USER_SECONDARY
---
> // ASI_BLOCK_AS_IF_USER_SECONDARY
1433c1430
< //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
---
> // ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1435c1432
< //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
---
> // ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1437c1434
< //ASI_BLOCK_PRIMARY
---
> // ASI_BLOCK_PRIMARY
1439c1436
< //ASI_BLOCK_SECONDARY
---
> // ASI_BLOCK_SECONDARY
1441c1438
< //ASI_BLOCK_PRIMARY_LITTLE
---
> // ASI_BLOCK_PRIMARY_LITTLE
1443c1440
< //ASI_BLOCK_SECONDARY_LITTLE
---
> // ASI_BLOCK_SECONDARY_LITTLE
1447,1448c1444,1445
< //STSHORTF
< //ASI_FL8_PRIMARY
---
> // STSHORTF
> // ASI_FL8_PRIMARY
1450c1447
< //ASI_FL8_SECONDARY
---
> // ASI_FL8_SECONDARY
1452c1449
< //ASI_FL8_PRIMARY_LITTLE
---
> // ASI_FL8_PRIMARY_LITTLE
1454c1451
< //ASI_FL8_SECONDARY_LITTLE
---
> // ASI_FL8_SECONDARY_LITTLE
1456c1453
< //ASI_FL16_PRIMARY
---
> // ASI_FL16_PRIMARY
1458c1455
< //ASI_FL16_SECONDARY
---
> // ASI_FL16_SECONDARY
1460c1457
< //ASI_FL16_PRIMARY_LITTLE
---
> // ASI_FL16_PRIMARY_LITTLE
1462c1459
< //ASI_FL16_SECONDARY_LITTLE
---
> // ASI_FL16_SECONDARY_LITTLE
1464c1461
< //Not an ASI which is legal with lddfa
---
> // Not an ASI which is legal with lddfa
< //Throw an illegal instruction acception
---
> // Throw an illegal instruction acception
44c44
< //bpcc
---
> // bpcc
47c47
< //Branch Always
---
> // Branch Always
54c54
< //Branch Never
---
> // Branch Never
68c68
< //bicc
---
> // bicc
71c71
< //Branch Always
---
> // Branch Always
78c78
< //Branch Never
---
> // Branch Never
101c101
< //SETHI (or NOP if rd == 0 and imm == 0)
---
> // SETHI (or NOP if rd == 0 and imm == 0)
103c103
< //fbpfcc
---
> // fbpfcc
106c106
< //Branch Always
---
> // Branch Always
113c113
< //Branch Never
---
> // Branch Never
133c133
< //fbfcc
---
> // fbfcc
136c136
< //Branch Always
---
> // Branch Always
143c143
< //Branch Never
---
> // Branch Never
187,188c187,190
< if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
< else Rd.udw = Rs1.udw / Rs2_or_imm13;
---
> if (Rs2_or_imm13 == 0)
> fault = new DivisionByZero;
> else
> Rd.udw = Rs1.udw / Rs2_or_imm13;
191,193c193,195
< if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
< else
< {
---
> if (Rs2_or_imm13 == 0) {
> fault = new DivisionByZero;
> } else {
195c197
< if(Rd.udw >> 32 != 0)
---
> if (Rd.udw >> 32 != 0)
200c202
< if(Rs2_or_imm13.sdw == 0)
---
> if (Rs2_or_imm13.sdw == 0) {
202,205c204,208
< else
< {
< Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
< if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max())
---
> } else {
> Rd.udw = ((int64_t)((Y << 32) |
> Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
> if ((int64_t)Rd.udw >=
> std::numeric_limits<int32_t>::max()) {
207c210,211
< else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min())
---
> } else if ((int64_t)Rd.udw <=
> std::numeric_limits<int32_t>::min()) {
208a213
> }
244,245c249,252
< if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
< else Rd = Rs1.udw / Rs2_or_imm13.udw;}});
---
> if (Rs2_or_imm13.udw == 0)
> fault = new DivisionByZero;
> else
> Rd = Rs1.udw / Rs2_or_imm13.udw;}});
250,252c257,259
< if(val2 == 0) fault = new DivisionByZero;
< else
< {
---
> if (val2 == 0) {
> fault = new DivisionByZero;
> } else {
255,256c262,265
< if(overflow) Rd = resTemp = 0xFFFFFFFF;
< else Rd = resTemp;
---
> if (overflow)
> Rd = resTemp = 0xFFFFFFFF;
> else
> Rd = resTemp;
262,264c271,273
< if(val2 == 0) fault = new DivisionByZero;
< else
< {
---
> if (val2 == 0) {
> fault = new DivisionByZero;
> } else {
268,269c277,280
< if(overflow) Rd = 0x7FFFFFFF;
< else if(underflow) Rd = ULL(0xFFFFFFFF80000000);
---
> if (overflow)
> Rd = 0x7FFFFFFF;
> else if (underflow)
> Rd = ULL(0xFFFFFFFF80000000);
291c302,303
< if(overflow) fault = new TagOverflow;
---
> if (overflow)
> fault = new TagOverflow;
298c310,311
< if(overflow) fault = new TagOverflow;
---
> if (overflow)
> fault = new TagOverflow;
303c316
< //Step 1
---
> // Step 1
305c318
< //Step 2
---
> // Step 2
308c321
< //Step 3
---
> // Step 3
312c325
< //Steps 4 & 5
---
> // Steps 4 & 5
332c345
< //1 should cause an illegal instruction exception
---
> // 1 should cause an illegal instruction exception
338c351
< if(Pstate<3:>)
---
> if (Pstate<3:>)
344c357
< //Wait for all fpops to finish.
---
> // Wait for all fpops to finish.
347c360
< //7-14 should cause an illegal instruction exception
---
> // 7-14 should cause an illegal instruction exception
354c367
< //0x12 should cause an illegal instruction exception
---
> // 0x12 should cause an illegal instruction exception
361c374
< //0x14-0x15 should cause an illegal instruction exception
---
> // 0x14-0x15 should cause an illegal instruction exception
367c380
< if(Pstate<2:> && !Hpstate<2:>)
---
> if (Pstate<2:> && !Hpstate<2:>)
372,374c385,387
< //0x1A is supposed to be reserved, but it reads the strand
< //status register.
< //0x1B-0x1F should cause an illegal instruction exception
---
> // 0x1A is supposed to be reserved, but it reads the strand
> // status register.
> // 0x1B-0x1F should cause an illegal instruction exception
379c392
< //0x02 should cause an illegal instruction exception
---
> // 0x02 should cause an illegal instruction exception
381c394
< //0x04 should cause an illegal instruction exception
---
> // 0x04 should cause an illegal instruction exception
384c397
< //0x07-0x1E should cause an illegal instruction exception
---
> // 0x07-0x1E should cause an illegal instruction exception
403c416
< //0x0F should cause an illegal instruction exception
---
> // 0x0F should cause an illegal instruction exception
405c418
< //0x11-0x1F should cause an illegal instruction exception
---
> // 0x11-0x1F should cause an illegal instruction exception
408,410c421,422
< if(NWindows - 2 - Cansave != 0)
< {
< if(Otherwin)
---
> if (NWindows - 2 - Cansave != 0) {
> if (Otherwin)
421c433
< if(passesCondition(Fsr<11:10>, COND4))
---
> if (passesCondition(Fsr<11:10>, COND4))
427c439
< if(passesCondition(Fsr<33:32>, COND4))
---
> if (passesCondition(Fsr<33:32>, COND4))
433c445
< if(passesCondition(Fsr<35:34>, COND4))
---
> if (passesCondition(Fsr<35:34>, COND4))
439c451
< if(passesCondition(Fsr<37:36>, COND4))
---
> if (passesCondition(Fsr<37:36>, COND4))
448c460
< if(passesCondition(Ccr<3:0>, COND4))
---
> if (passesCondition(Ccr<3:0>, COND4))
454c466
< if(passesCondition(Ccr<7:4>, COND4))
---
> if (passesCondition(Ccr<7:4>, COND4))
462,463c474,477
< if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
< else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
---
> if (Rs2_or_imm13.sdw == 0)
> fault = new DivisionByZero;
> else
> Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
477c491
< //0x01 should cause an illegal instruction exception
---
> // 0x01 should cause an illegal instruction exception
480c494
< //0x04-0x05 should cause an illegal instruction exception
---
> // 0x04-0x05 should cause an illegal instruction exception
482c496
< //0x07-0x0E should cause an illegal instruction exception
---
> // 0x07-0x0E should cause an illegal instruction exception
486c500
< //0x12 should cause an illegal instruction exception
---
> // 0x12 should cause an illegal instruction exception
488c502
< if(Fprs<2:> == 0 || Pstate<4:> == 0)
---
> if (Fprs<2:> == 0 || Pstate<4:> == 0)
497c511
< if(!Hpstate<2:>)
---
> if (!Hpstate<2:>)
505,507c519,521
< //0x1A is supposed to be reserved, but it writes the strand
< //status register.
< //0x1B-0x1F should cause an illegal instruction exception
---
> // 0x1A is supposed to be reserved, but it writes the strand
> // status register.
> // 0x1B-0x1F should cause an illegal instruction exception
514c528
< if(Otherwin == 0)
---
> if (Otherwin == 0)
523c537
< if(Otherwin == 0)
---
> if (Otherwin == 0)
528c542
< if(Cleanwin < NWindows - 1)
---
> if (Cleanwin < NWindows - 1)
545c559
< if(Pstate<2:> && !Hpstate<2:>)
---
> if (Pstate<2:> && !Hpstate<2:>)
557c571
< //0x0F should cause an illegal instruction exception
---
> // 0x0F should cause an illegal instruction exception
559c573
< if(Pstate<2:> && !Hpstate<2:>)
---
> if (Pstate<2:> && !Hpstate<2:>)
564c578
< //0x11-0x1F should cause an illegal instruction exception
---
> // 0x11-0x1F should cause an illegal instruction exception
570c584
< //0x02 should cause an illegal instruction exception
---
> // 0x02 should cause an illegal instruction exception
572c586
< //0x04 should cause an illegal instruction exception
---
> // 0x04 should cause an illegal instruction exception
574c588
< //0x06-0x01D should cause an illegal instruction exception
---
> // 0x06-0x01D should cause an illegal instruction exception
639c653
< if(passesFpCondition(Fsr<11:10>, COND4))
---
> if (passesFpCondition(Fsr<11:10>, COND4))
645c659
< if(passesFpCondition(Fsr<11:10>, COND4))
---
> if (passesFpCondition(Fsr<11:10>, COND4))
652c666
< if(Rs1 == 0)
---
> if (Rs1 == 0)
658c672
< if(Rs1 == 0)
---
> if (Rs1 == 0)
665c679
< if(passesFpCondition(Fsr<33:32>, COND4))
---
> if (passesFpCondition(Fsr<33:32>, COND4))
671c685
< if(passesFpCondition(Fsr<33:32>, COND4))
---
> if (passesFpCondition(Fsr<33:32>, COND4))
678c692
< if(Rs1 <= 0)
---
> if (Rs1 <= 0)
684c698
< if(Rs1 <= 0)
---
> if (Rs1 <= 0)
692c706
< if(isnan(Frs1s) || isnan(Frs2s))
---
> if (isnan(Frs1s) || isnan(Frs2s))
694c708
< else if(Frs1s < Frs2s)
---
> else if (Frs1s < Frs2s)
696c710
< else if(Frs1s > Frs2s)
---
> else if (Frs1s > Frs2s)
701c715
< if(FCMPCC)
---
> if (FCMPCC)
707c721
< if(isnan(Frs1) || isnan(Frs2))
---
> if (isnan(Frs1) || isnan(Frs2))
709c723
< else if(Frs1 < Frs2)
---
> else if (Frs1 < Frs2)
711c725
< else if(Frs1 > Frs2)
---
> else if (Frs1 > Frs2)
716c730
< if(FCMPCC)
---
> if (FCMPCC)
723c737
< if(isnan(Frs1s) || isnan(Frs2s))
---
> if (isnan(Frs1s) || isnan(Frs2s))
725c739
< if(Frs1s < Frs2s)
---
> if (Frs1s < Frs2s)
727c741
< else if(Frs1s > Frs2s)
---
> else if (Frs1s > Frs2s)
730c744
< if(FCMPCC)
---
> if (FCMPCC)
736c750
< if(isnan(Frs1) || isnan(Frs2))
---
> if (isnan(Frs1) || isnan(Frs2))
738c752
< if(Frs1 < Frs2)
---
> if (Frs1 < Frs2)
740c754
< else if(Frs1 > Frs2)
---
> else if (Frs1 > Frs2)
743c757
< if(FCMPCC)
---
> if (FCMPCC)
749c763
< if(Rs1 < 0)
---
> if (Rs1 < 0)
755c769
< if(Rs1 < 0)
---
> if (Rs1 < 0)
762c776
< if(passesFpCondition(Fsr<35:34>, COND4))
---
> if (passesFpCondition(Fsr<35:34>, COND4))
768c782
< if(passesFpCondition(Fsr<35:34>, COND4))
---
> if (passesFpCondition(Fsr<35:34>, COND4))
775c789
< if(Rs1 != 0)
---
> if (Rs1 != 0)
781c795
< if(Rs1 != 0)
---
> if (Rs1 != 0)
788c802
< if(passesFpCondition(Fsr<37:36>, COND4))
---
> if (passesFpCondition(Fsr<37:36>, COND4))
794c808
< if(passesFpCondition(Fsr<37:36>, COND4))
---
> if (passesFpCondition(Fsr<37:36>, COND4))
801c815
< if(Rs1 > 0)
---
> if (Rs1 > 0)
807c821
< if(Rs1 > 0)
---
> if (Rs1 > 0)
814c828
< if(Rs1 >= 0)
---
> if (Rs1 >= 0)
820c834
< if(Rs1 >= 0)
---
> if (Rs1 >= 0)
827c841
< if(passesCondition(Ccr<3:0>, COND4))
---
> if (passesCondition(Ccr<3:0>, COND4))
833c847
< if(passesCondition(Ccr<3:0>, COND4))
---
> if (passesCondition(Ccr<3:0>, COND4))
840c854
< if(passesCondition(Ccr<7:4>, COND4))
---
> if (passesCondition(Ccr<7:4>, COND4))
846c860
< if(passesCondition(Ccr<7:4>, COND4))
---
> if (passesCondition(Ccr<7:4>, COND4))
855,856c869,870
< //This used to be just impdep1, but now it's a whole bunch
< //of instructions
---
> // This used to be just impdep1, but now it's a whole bunch
> // of instructions
906,926c920,939
< //Some special cases need to be split out, first
< //because they're the most likely to be used, and
< //second because otherwise, we end up shifting by
< //greater than the width of the type being shifted,
< //namely 64, which produces undefined results according
< //to the C standard.
< switch(Gsr<2:0>)
< {
< case 0:
< Frd.udw = msbX;
< break;
< case 8:
< Frd.udw = lsbX;
< break;
< default:
< uint64_t msbShift = Gsr<2:0> * 8;
< uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
< uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
< uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
< Frd.udw = ((msbX & msbMask) << msbShift) |
< ((lsbX & lsbMask) >> lsbShift);
---
> // Some special cases need to be split out, first
> // because they're the most likely to be used, and
> // second because otherwise, we end up shifting by
> // greater than the width of the type being shifted,
> // namely 64, which produces undefined results
> // according to the C standard.
> switch (Gsr<2:0>) {
> case 0:
> Frd.udw = msbX;
> break;
> case 8:
> Frd.udw = lsbX;
> break;
> default:
> uint64_t msbShift = Gsr<2:0> * 8;
> uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
> uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
> uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
> Frd.udw = ((msbX & msbMask) << msbShift) |
> ((lsbX & lsbMask) >> lsbShift);
1005c1018
< if(target & 0x3)
---
> if (target & 0x3) {
1007,1008c1020
< else
< {
---
> } else {
1020,1026c1032,1036
< if(fault == NoFault)
< {
< //Check for fills which are higher priority than alignment
< //faults.
< if(Canrestore == 0)
< {
< if(Otherwin)
---
> if (fault == NoFault) {
> // Check for fills which are higher priority than alignment
> // faults.
> if (Canrestore == 0) {
> if (Otherwin)
1030,1032c1040
< }
< //Check for alignment faults
< else if(target & 0x3)
---
> } else if (target & 0x3) { // Check for alignment faults
1034,1035c1042
< else
< {
---
> } else {
1048,1049c1055
< if(passesCondition(Ccr<3:0>, COND2))
< {
---
> if (passesCondition(Ccr<3:0>, COND2)) {
1056,1057c1062
< if(passesCondition(Ccr<7:4>, COND2))
< {
---
> if (passesCondition(Ccr<7:4>, COND2)) {
1067,1069c1072,1073
< if(Cansave == 0)
< {
< if(Otherwin)
---
> if (Cansave == 0) {
> if (Otherwin)
1073,1075c1077
< }
< else if(Cleanwin - Canrestore == 0)
< {
---
> } else if (Cleanwin - Canrestore == 0) {
1077,1079c1079
< }
< else
< {
---
> } else {
1087,1089c1087,1088
< if(Canrestore == 0)
< {
< if(Otherwin)
---
> if (Canrestore == 0) {
> if (Otherwin)
1093,1095c1092
< }
< else
< {
---
> } else {
1147,1150c1144,1147
< //This temporary needs to be here so that the parser
< //will correctly identify this instruction as a store.
< //It's probably either the parenthesis or referencing
< //the member variable that throws confuses it.
---
> // This temporary needs to be here so that the parser
> // will correctly identify this instruction as a store.
> // It's probably either the parenthesis or referencing
> // the member variable that throws confuses it.
1179c1176
< //ASI_LDTD_AIUP
---
> // ASI_LDTD_AIUP
1183c1180
< //ASI_LDTD_AIUS
---
> // ASI_LDTD_AIUS
1187c1184
< //ASI_QUAD_LDD
---
> // ASI_QUAD_LDD
1191c1188
< //ASI_LDTX_REAL
---
> // ASI_LDTX_REAL
1195c1192
< //ASI_LDTX_N
---
> // ASI_LDTX_N
1199c1196
< //ASI_LDTX_AIUP_L
---
> // ASI_LDTX_AIUP_L
1203c1200
< //ASI_LDTX_AIUS_L
---
> // ASI_LDTX_AIUS_L
1207c1204
< //ASI_LDTX_L
---
> // ASI_LDTX_L
1211c1208
< //ASI_LDTX_REAL_L
---
> // ASI_LDTX_REAL_L
1215c1212
< //ASI_LDTX_N_L
---
> // ASI_LDTX_N_L
1219c1216
< //ASI_LDTX_P
---
> // ASI_LDTX_P
1223c1220
< //ASI_LDTX_S
---
> // ASI_LDTX_S
1227c1224
< //ASI_LDTX_PL
---
> // ASI_LDTX_PL
1231c1228
< //ASI_LDTX_SL
---
> // ASI_LDTX_SL
1245,1248c1242,1245
< //This temporary needs to be here so that the parser
< //will correctly identify this instruction as a store.
< //It's probably either the parenthesis or referencing
< //the member variable that throws confuses it.
---
> // This temporary needs to be here so that the parser
> // will correctly identify this instruction as a store.
> // It's probably either the parenthesis or referencing
> // the member variable that throws confuses it.
1307c1304
< //ASI_NUCLEUS
---
> // ASI_NUCLEUS
1309c1306
< //ASI_NUCLEUS_LITTLE
---
> // ASI_NUCLEUS_LITTLE
1311c1308
< //ASI_AS_IF_USER_PRIMARY
---
> // ASI_AS_IF_USER_PRIMARY
1313c1310
< //ASI_AS_IF_USER_PRIMARY_LITTLE
---
> // ASI_AS_IF_USER_PRIMARY_LITTLE
1315c1312
< //ASI_AS_IF_USER_SECONDARY
---
> // ASI_AS_IF_USER_SECONDARY
1317c1314
< //ASI_AS_IF_USER_SECONDARY_LITTLE
---
> // ASI_AS_IF_USER_SECONDARY_LITTLE
1319c1316
< //ASI_REAL
---
> // ASI_REAL
1321c1318
< //ASI_REAL_LITTLE
---
> // ASI_REAL_LITTLE
1323c1320
< //ASI_REAL_IO
---
> // ASI_REAL_IO
1325c1322
< //ASI_REAL_IO_LITTLE
---
> // ASI_REAL_IO_LITTLE
1327c1324
< //ASI_PRIMARY
---
> // ASI_PRIMARY
1329c1326
< //ASI_PRIMARY_LITTLE
---
> // ASI_PRIMARY_LITTLE
1331c1328
< //ASI_SECONDARY
---
> // ASI_SECONDARY
1333c1330
< //ASI_SECONDARY_LITTLE
---
> // ASI_SECONDARY_LITTLE
1335c1332
< //ASI_PRIMARY_NO_FAULT
---
> // ASI_PRIMARY_NO_FAULT
1337c1334
< //ASI_PRIMARY_NO_FAULT_LITTLE
---
> // ASI_PRIMARY_NO_FAULT_LITTLE
1339c1336
< //ASI_SECONDARY_NO_FAULT
---
> // ASI_SECONDARY_NO_FAULT
1341c1338
< //ASI_SECONDARY_NO_FAULT_LITTLE
---
> // ASI_SECONDARY_NO_FAULT_LITTLE
1346c1343
< //ASI_BLOCK_AS_IF_USER_PRIMARY
---
> // ASI_BLOCK_AS_IF_USER_PRIMARY
1348c1345
< //ASI_BLOCK_AS_IF_USER_SECONDARY
---
> // ASI_BLOCK_AS_IF_USER_SECONDARY
1350c1347
< //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
---
> // ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1352c1349
< //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
---
> // ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1354c1351
< //ASI_BLOCK_PRIMARY
---
> // ASI_BLOCK_PRIMARY
1356c1353
< //ASI_BLOCK_SECONDARY
---
> // ASI_BLOCK_SECONDARY
1358c1355
< //ASI_BLOCK_PRIMARY_LITTLE
---
> // ASI_BLOCK_PRIMARY_LITTLE
1360c1357
< //ASI_BLOCK_SECONDARY_LITTLE
---
> // ASI_BLOCK_SECONDARY_LITTLE
1364,1365c1361,1362
< //LDSHORTF
< //ASI_FL8_PRIMARY
---
> // LDSHORTF
> // ASI_FL8_PRIMARY
1367c1364
< //ASI_FL8_SECONDARY
---
> // ASI_FL8_SECONDARY
1369c1366
< //ASI_FL8_PRIMARY_LITTLE
---
> // ASI_FL8_PRIMARY_LITTLE
1371c1368
< //ASI_FL8_SECONDARY_LITTLE
---
> // ASI_FL8_SECONDARY_LITTLE
1373c1370
< //ASI_FL16_PRIMARY
---
> // ASI_FL16_PRIMARY
1375c1372
< //ASI_FL16_SECONDARY
---
> // ASI_FL16_SECONDARY
1377c1374
< //ASI_FL16_PRIMARY_LITTLE
---
> // ASI_FL16_PRIMARY_LITTLE
1379c1376
< //ASI_FL16_SECONDARY_LITTLE
---
> // ASI_FL16_SECONDARY_LITTLE
1381c1378
< //Not an ASI which is legal with lddfa
---
> // Not an ASI which is legal with lddfa
1390c1387
< //ASI_NUCLEUS
---
> // ASI_NUCLEUS
1392c1389
< //ASI_NUCLEUS_LITTLE
---
> // ASI_NUCLEUS_LITTLE
1394c1391
< //ASI_AS_IF_USER_PRIMARY
---
> // ASI_AS_IF_USER_PRIMARY
1396c1393
< //ASI_AS_IF_USER_PRIMARY_LITTLE
---
> // ASI_AS_IF_USER_PRIMARY_LITTLE
1398c1395
< //ASI_AS_IF_USER_SECONDARY
---
> // ASI_AS_IF_USER_SECONDARY
1400c1397
< //ASI_AS_IF_USER_SECONDARY_LITTLE
---
> // ASI_AS_IF_USER_SECONDARY_LITTLE
1402c1399
< //ASI_REAL
---
> // ASI_REAL
1404c1401
< //ASI_REAL_LITTLE
---
> // ASI_REAL_LITTLE
1406c1403
< //ASI_REAL_IO
---
> // ASI_REAL_IO
1408c1405
< //ASI_REAL_IO_LITTLE
---
> // ASI_REAL_IO_LITTLE
1410c1407
< //ASI_PRIMARY
---
> // ASI_PRIMARY
1412c1409
< //ASI_PRIMARY_LITTLE
---
> // ASI_PRIMARY_LITTLE
1414c1411
< //ASI_SECONDARY
---
> // ASI_SECONDARY
1416c1413
< //ASI_SECONDARY_LITTLE
---
> // ASI_SECONDARY_LITTLE
1418c1415
< //ASI_PRIMARY_NO_FAULT
---
> // ASI_PRIMARY_NO_FAULT
1420c1417
< //ASI_PRIMARY_NO_FAULT_LITTLE
---
> // ASI_PRIMARY_NO_FAULT_LITTLE
1422c1419
< //ASI_SECONDARY_NO_FAULT
---
> // ASI_SECONDARY_NO_FAULT
1424c1421
< //ASI_SECONDARY_NO_FAULT_LITTLE
---
> // ASI_SECONDARY_NO_FAULT_LITTLE
1429c1426
< //ASI_BLOCK_AS_IF_USER_PRIMARY
---
> // ASI_BLOCK_AS_IF_USER_PRIMARY
1431c1428
< //ASI_BLOCK_AS_IF_USER_SECONDARY
---
> // ASI_BLOCK_AS_IF_USER_SECONDARY
1433c1430
< //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
---
> // ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1435c1432
< //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
---
> // ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1437c1434
< //ASI_BLOCK_PRIMARY
---
> // ASI_BLOCK_PRIMARY
1439c1436
< //ASI_BLOCK_SECONDARY
---
> // ASI_BLOCK_SECONDARY
1441c1438
< //ASI_BLOCK_PRIMARY_LITTLE
---
> // ASI_BLOCK_PRIMARY_LITTLE
1443c1440
< //ASI_BLOCK_SECONDARY_LITTLE
---
> // ASI_BLOCK_SECONDARY_LITTLE
1447,1448c1444,1445
< //STSHORTF
< //ASI_FL8_PRIMARY
---
> // STSHORTF
> // ASI_FL8_PRIMARY
1450c1447
< //ASI_FL8_SECONDARY
---
> // ASI_FL8_SECONDARY
1452c1449
< //ASI_FL8_PRIMARY_LITTLE
---
> // ASI_FL8_PRIMARY_LITTLE
1454c1451
< //ASI_FL8_SECONDARY_LITTLE
---
> // ASI_FL8_SECONDARY_LITTLE
1456c1453
< //ASI_FL16_PRIMARY
---
> // ASI_FL16_PRIMARY
1458c1455
< //ASI_FL16_SECONDARY
---
> // ASI_FL16_SECONDARY
1460c1457
< //ASI_FL16_PRIMARY_LITTLE
---
> // ASI_FL16_PRIMARY_LITTLE
1462c1459
< //ASI_FL16_SECONDARY_LITTLE
---
> // ASI_FL16_SECONDARY_LITTLE
1464c1461
< //Not an ASI which is legal with lddfa
---
> // Not an ASI which is legal with lddfa