475,476c475,476
< 0x0: Nop::stbar({{/*stuff*/}});
< 0x1: Nop::membar({{/*stuff*/}});
---
> 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp);
> 0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp);
1171,1174c1171,1175
< 0x0D: LoadStore::ldstub(
< {{uReg0 = Mem.ub;}},
< {{Rd.ub = uReg0;
< Mem.ub = 0xFF;}});
---
> 0x0D: Swap::ldstub({{Mem.ub = 0xFF;}},
> {{
> uint8_t tmp = mem_data;
> Rd.ub = tmp;
> }}, MEM_SWAP);
1176,1179c1177,1181
< 0x0F: LoadStore::swap(
< {{ uReg0 = Mem.uw}},
< {{ Mem.uw = Rd.uw;
< Rd.uw = uReg0;}});
---
> 0x0F: Swap::swap({{Mem.uw = Rd.uw}},
> {{
> uint32_t tmp = mem_data;
> Rd.uw = tmp;
> }}, MEM_SWAP);
1187c1189,1190
< {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
---
> {{RdLow.udw = (Mem.tudw).a;
> RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1190c1193,1194
< {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
---
> {{RdLow.udw = (Mem.tudw).a;
> RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1193c1197,1198
< {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
---
> {{RdLow.udw = (Mem.tudw).a;
> RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1196,1202c1201,1218
< {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
< //ASI_LDTX_N
< 0x27: TwinLoad::ldtx_n(
< {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
< //ASI_LDTX_L
< 0x2C: TwinLoad::ldtx_l(
< {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
---
> {{RdLow.udw = (Mem.tudw).a;
> RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
> //ASI_LDTX_N
> 0x27: TwinLoad::ldtx_n(
> {{RdLow.udw = (Mem.tudw).a;
> RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
> //ASI_LDTX_AIUP_L
> 0x2A: TwinLoad::ldtx_aiup_l(
> {{RdLow.udw = (Mem.tudw).a;
> RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
> //ASI_LDTX_AIUS_L
> 0x2B: TwinLoad::ldtx_aius_l(
> {{RdLow.udw = (Mem.tudw).a;
> RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
> //ASI_LDTX_L
> 0x2C: TwinLoad::ldtx_l(
> {{RdLow.udw = (Mem.tudw).a;
> RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1205c1221,1222
< {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
---
> {{RdLow.udw = (Mem.tudw).a;
> RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1208c1225,1226
< {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
---
> {{RdLow.udw = (Mem.tudw).a;
> RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1211c1229,1230
< {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
---
> {{RdLow.udw = (Mem.tudw).a;
> RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1214c1233,1242
< {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
---
> {{RdLow.udw = (Mem.tudw).a;
> RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
> //ASI_LDTX_PL
> 0xEA: TwinLoad::ldtx_pl(
> {{RdLow.udw = (Mem.tudw).a;
> RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
> //ASI_LDTX_SL
> 0xEB: TwinLoad::ldtx_sl(
> {{RdLow.udw = (Mem.tudw).a;
> RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1234,1237c1262,1266
< 0x1D: LoadStoreAlt::ldstuba(
< {{uReg0 = Mem.ub;}},
< {{Rd.ub = uReg0;
< Mem.ub = 0xFF;}}, {{EXT_ASI}});
---
> 0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}},
> {{
> uint8_t tmp = mem_data;
> Rd.ub = tmp;
> }}, {{EXT_ASI}}, MEM_SWAP);
1239,1242c1268,1273
< 0x1F: LoadStoreAlt::swapa(
< {{ uReg0 = Mem.uw}},
< {{ Mem.uw = Rd.uw;
< Rd.uw = uReg0;}}, {{EXT_ASI}});
---
> 0x1F: SwapAlt::swapa({{Mem.uw = Rd.uw}},
> {{
> uint32_t tmp = mem_data;
> Rd.uw = tmp;
> }}, {{EXT_ASI}}, MEM_SWAP);
>
1441,1447c1472,1478
< 0x3C: Cas::casa(
< {{uReg0 = Mem.uw;}},
< {{if(Rs2.uw == uReg0)
< Mem.uw = Rd.uw;
< else
< storeCond = false;
< Rd.uw = uReg0;}}, {{EXT_ASI}});
---
> 0x3C: CasAlt::casa({{
> mem_data = htog(Rs2.uw);
> Mem.uw = Rd.uw;}},
> {{
> uint32_t tmp = mem_data;
> Rd.uw = tmp;
> }}, {{EXT_ASI}}, MEM_SWAP_COND);
1449,1455c1480,1482
< 0x3E: Cas::casxa(
< {{uReg0 = Mem.udw;}},
< {{if(Rs2 == uReg0)
< Mem.udw = Rd;
< else
< storeCond = false;
< Rd = uReg0;}}, {{EXT_ASI}});
---
> 0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2);
> Mem.udw = Rd.udw; }},
> {{ Rd.udw = mem_data; }}, {{EXT_ASI}}, MEM_SWAP_COND);