195c195
< Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
---
> Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
218c218
< if(Rd.udw<63:31> != 0)
---
> if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max())
220,221c220,221
< else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
< Rd.udw = 0xFFFFFFFF80000000ULL;
---
> else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min())
> Rd.udw = ULL(0xFFFFFFFF80000000);
255,256c255
< {{(Rs1<63:1> + val2<63:1> +
< ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
---
> {{((Rs1 & val2) | (~resTemp & (Rs1 | val2)))<63:>}},
265c264
< Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>;
---
> Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
271c270
< {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
---
> {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<31:>}},
273c272
< {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
---
> {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<63:>}},
302,303c301,302
< overflow = (Rd<63:31> != 0);
< underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF);
---
> overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max());
> underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min());
305c304
< else if(underflow) Rd = 0xFFFFFFFF80000000ULL;
---
> else if(underflow) Rd = ULL(0xFFFFFFFF80000000);
382c381
< 0x00: NoPriv::rdy({{Rd = Y;}});
---
> 0x00: NoPriv::rdy({{Rd = Y<31:0>;}});
532c531
< 0x00: NoPriv::wry({{Y = Rs1 ^ Rs2_or_imm13;}});
---
> 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}});
670c669
< 0x03: Trap::fmovq({{fault = new FpDisabled;}});
---
> 0x03: Trap::fmovq({{fault = new FpExceptionOther;}});
697,698c696,697
< 0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}});
< 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}});
---
> 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}});
> 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}});
866c865
< 0x75: BasicOperate::fsrc1s({{Frd.uw = Frs1.uw;}});
---
> 0x75: BasicOperate::fsrc1s({{Frds.uw = Frs1s.uw;}});
870c869
< 0x79: BasicOperate::fsrc2s({{Frd.uw = Frs2.uw;}});
---
> 0x79: BasicOperate::fsrc2s({{Frds.uw = Frs2s.uw;}});
888c887
< (Rd = xc->readPC())<31:0>;
---
> Rd = (xc->readPC())<31:0>;
1040,1041c1039,1041
< {{Rd = Mem.ub;}},
< {{Mem.ub = 0xFF;}});
---
> {{uReg0 = Mem.ub;}},
> {{Rd.ub = uReg0;
> Mem.ub = 0xFF;}});
1044,1046c1044,1046
< {{uReg0 = Rd.uw;
< Rd.uw = Mem.uw;}},
< {{Mem.uw = uReg0;}});
---
> {{ uReg0 = Mem.uw}},
> {{ Mem.uw = Rd.uw;
> Rd.uw = uReg0;}});
1054c1054
< {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
---
> {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1057c1057
< {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
---
> {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1060c1060
< {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
---
> {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1063c1063
< {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
---
> {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1066c1066
< {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
---
> {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1069c1069
< {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
---
> {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1072c1072
< {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
---
> {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1075c1075
< {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
---
> {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1078c1078
< {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
---
> {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1081c1081
< {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
---
> {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1102,1103c1102,1104
< {{Rd = Mem.ub;}},
< {{Mem.ub = 0xFF}}, {{EXT_ASI}});
---
> {{uReg0 = Mem.ub;}},
> {{Rd.ub = uReg0;
> Mem.ub = 0xFF;}}, {{EXT_ASI}});
1106,1108c1107,1109
< {{uReg0 = Rd.uw;
< Rd.uw = Mem.uw;}},
< {{Mem.uw = uReg0;}}, {{EXT_ASI}});
---
> {{ uReg0 = Mem.uw}},
> {{ Mem.uw = Rd.uw;
> Rd.uw = uReg0;}}, {{EXT_ASI}});
1110c1111
< 0x20: Load::ldf({{Frd.uw = Mem.uw;}});
---
> 0x20: Load::ldf({{Frds.uw = Mem.uw;}});
1117c1118
< 0x24: Store::stf({{Mem.uw = Frd.uw;}});
---
> 0x24: Store::stf({{Mem.uw = Frds.uw;}});
1125c1126
< 0x30: LoadAlt::ldfa({{Frd.uw = Mem.uw;}}, {{EXT_ASI}});
---
> 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}});
1208c1209
< 0x34: Store::stfa({{Mem.uw = Frd.uw;}});
---
> 0x34: Store::stfa({{Mem.uw = Frds.uw;}});