1012c1012
< 0x03: ldd({{
---
> 0x03: ldtw({{
1022c1022
< 0x07: std({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
---
> 0x07: sttw({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
1042c1042
< 0x13: ldda({{
---
> 0x13: ldtwa({{
1052c1052
< 0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}});
---
> 0x17: sttwa({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}});
1107a1108,1119
> //ASI_LDTX_REAL
> 0x26: TwinLoad::ldtx_real(
> {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
> //ASI_LDTX_N
> 0x27: TwinLoad::ldtx_n(
> {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
> //ASI_LDTX_REAL_L
> 0x2E: TwinLoad::ldtx_real_l(
> {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
> //ASI_LDTX_N_L
> 0x2F: TwinLoad::ldtx_n_l(
> {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});