380c380,382
< 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
---
> 0x04: PrivCheck::rdtick(
> {{ Rd = xc->readMiscRegWithEffect(MISCREG_TICK);}},
> {{Tick<63:>}});
406,408c408,416
< 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
< 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}});
< 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
---
> 0x17: Priv::rdtick_cmpr({{
> Rd = xc->readMiscRegWithEffect(MISCREG_TICK_CMPR);
> }});
> 0x18: PrivCheck::rdstick({{
> Rd = xc->readMiscRegWithEffect(MISCREG_STICK);
> }}, {{Stick<63:>}});
> 0x19: Priv::rdstick_cmpr({{
> Rd = xc->readMiscRegWithEffect(MISCREG_STICK_CMPR);
> }});
432c440,442
< 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
---
> 0x1F: HPriv::rdhprhstick_cmpr({{
> Rd = xc->readMiscRegWithEffect(MISCREG_HSTICK_CMPR);
> }});
455c465,467
< 0x04: Priv::rdprtick({{Rd = Tick;}});
---
> 0x04: Priv::rdprtick({{
> Rd = xc->readMiscRegWithEffect(MISCREG_TICK);
> }});
545c557,559
< 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}});
---
> 0x17: Priv::wrtick_cmpr({{
> xc->setMiscRegWithEffect(MISCREG_TICK_CMPR, Rs1 ^ Rs2_or_imm13);
> }});
549c563
< Stick = Rs1 ^ Rs2_or_imm13;
---
> xc->setMiscRegWithEffect(MISCREG_STICK, Rs1 ^ Rs2_or_imm13);
551c565,567
< 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}});
---
> 0x19: Priv::wrstick_cmpr({{
> xc->setMiscRegWithEffect(MISCREG_STICK_CMPR, Rs1 ^ Rs2_or_imm13);
> }});
608c624,626
< 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
---
> 0x04: HPriv::wrprtick({{
> xc->setMiscRegWithEffect(MISCREG_TICK, Rs1 ^ Rs2_or_imm13);
> }});
645c663,665
< 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
---
> 0x1F: HPriv::wrhprhstick_cmpr({{
> xc->setMiscRegWithEffect(MISCREG_HSTICK_CMPR, Rs1 ^ Rs2_or_imm13);
> }});
1057,1060c1077,1080
< format LoadAlt {
< 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
< 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
< 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
---
> format Load {
> 0x10: lduwa({{Rd = Mem.uw;}});
> 0x11: lduba({{Rd = Mem.ub;}});
> 0x12: lduha({{Rd = Mem.uhw;}});
1065c1085
< }}, {{EXT_ASI}});
---
> }});
1067,1071c1087,1091
< format StoreAlt {
< 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
< 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
< 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
< 0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}});
---
> format Store {
> 0x14: stwa({{Mem.uw = Rd;}});
> 0x15: stba({{Mem.ub = Rd;}});
> 0x16: stha({{Mem.uhw = Rd;}});
> 0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}});
1073,1077c1093,1097
< format LoadAlt {
< 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
< 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}});
< 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}});
< 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}});
---
> format Load {
> 0x18: ldswa({{Rd = (int32_t)Mem.sw;}});
> 0x19: ldsba({{Rd = (int8_t)Mem.sb;}});
> 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}});
> 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}});
1079c1099
< 0x1D: LoadStoreAlt::ldstuba(
---
> 0x1D: LoadStore::ldstuba(
1081,1083c1101,1103
< {{Mem.ub = 0xFF}}, {{EXT_ASI}});
< 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}});
< 0x1F: LoadStoreAlt::swapa(
---
> {{Mem.ub = 0xFF}});
> 0x1E: Store::stxa({{Mem.udw = Rd}});
> 0x1F: LoadStore::swapa(
1086c1106
< {{Mem.uw = uReg0;}}, {{EXT_ASI}});
---
> {{Mem.uw = uReg0;}});
1103c1123
< 0x30: LoadAlt::ldfa({{Frd.uw = Mem.uw;}}, {{EXT_ASI}});
---
> 0x30: Load::ldfa({{Frd.uw = Mem.uw;}});
1155c1175
< 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}});
---
> 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}});
1238c1258
< 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}});
---
> 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}});
1275c1295
< Rd.uw = uReg0;}}, {{EXT_ASI}});
---
> Rd.uw = uReg0;}});
1283c1303
< Rd = uReg0;}}, {{EXT_ASI}});
---
> Rd = uReg0;}});