1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OP default Unknown::unknown()
37{
38 0x0: decode OP2
39 {
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 //bpcc
45 0x1: decode COND2
46 {
47 //Branch Always
48 0x8: decode A
49 {
50 0x0: bpa(19, {{
51 NNPC = xc->readPC() + disp;
52 }});
53 0x1: bpa(19, {{
54 NPC = xc->readPC() + disp;
55 NNPC = NPC + 4;
56 }}, ',a');
57 }
58 //Branch Never
59 0x0: decode A
60 {
61 0x0: bpn(19, {{
62 NNPC = NNPC;//Don't do anything
63 }});
64 0x1: bpn(19, {{
65 NNPC = NPC + 8;
66 NPC = NPC + 4;
67 }}, ',a');
68 }
69 default: decode BPCC
70 {
71 0x0: bpcci(19, {{
72 if(passesCondition(Ccr<3:0>, COND2))
73 NNPC = xc->readPC() + disp;
74 else
75 handle_annul
76 }});
77 0x2: bpccx(19, {{
78 if(passesCondition(Ccr<7:4>, COND2))
79 NNPC = xc->readPC() + disp;
80 else
81 handle_annul
82 }});
83 }
84 }
85 //bicc
86 0x2: decode COND2
87 {
88 //Branch Always
89 0x8: decode A
90 {
91 0x0: ba(22, {{
92 NNPC = xc->readPC() + disp;
93 }});
94 0x1: ba(22, {{
95 NPC = xc->readPC() + disp;
96 NNPC = NPC + 4;
97 }}, ',a');
98 }
99 //Branch Never
100 0x0: decode A
101 {
102 0x0: bn(22, {{
103 NNPC = NNPC;//Don't do anything
104 }});
105 0x1: bn(22, {{
106 NNPC = NPC + 8;
107 NPC = NPC + 4;
108 }}, ',a');
109 }
110 default: bicc(22, {{
111 if(passesCondition(Ccr<3:0>, COND2))
112 NNPC = xc->readPC() + disp;
113 else
114 handle_annul
115 }});
116 }
117 }
118 0x3: decode RCOND2
119 {
120 format BranchSplit
121 {
122 0x1: bpreq({{
123 if(Rs1.sdw == 0)
124 NNPC = xc->readPC() + disp;
125 else
126 handle_annul
127 }});
128 0x2: bprle({{
129 if(Rs1.sdw <= 0)
130 NNPC = xc->readPC() + disp;
131 else
132 handle_annul
133 }});
134 0x3: bprl({{
135 if(Rs1.sdw < 0)
136 NNPC = xc->readPC() + disp;
137 else
138 handle_annul
139 }});
140 0x5: bprne({{
141 if(Rs1.sdw != 0)
142 NNPC = xc->readPC() + disp;
143 else
144 handle_annul
145 }});
146 0x6: bprg({{
147 if(Rs1.sdw > 0)
148 NNPC = xc->readPC() + disp;
149 else
150 handle_annul
151 }});
152 0x7: bprge({{
153 if(Rs1.sdw >= 0)
154 NNPC = xc->readPC() + disp;
155 else
156 handle_annul
157 }});
158 }
159 }
160 //SETHI (or NOP if rd == 0 and imm == 0)
161 0x4: SetHi::sethi({{Rd.udw = imm;}});
162 //fbpfcc
163 0x5: decode COND2 {
164 format BranchN {
165 //Branch Always
166 0x8: decode A
167 {
168 0x0: fbpa(22, {{
169 NNPC = xc->readPC() + disp;
170 }});
171 0x1: fbpa(22, {{
172 NPC = xc->readPC() + disp;
173 NNPC = NPC + 4;
174 }}, ',a');
175 }
176 //Branch Never
177 0x0: decode A
178 {
179 0x0: fbpn(22, {{
180 NNPC = NNPC;//Don't do anything
181 }});
182 0x1: fbpn(22, {{
183 NNPC = NPC + 8;
184 NPC = NPC + 4;
185 }}, ',a');
186 }
187 default: decode BPCC {
188 0x0: fbpcc0(22, {{
189 if(passesFpCondition(Fsr<11:10>, COND2))
190 NNPC = xc->readPC() + disp;
191 else
192 handle_annul
193 }});
194 0x1: fbpcc1(22, {{
195 if(passesFpCondition(Fsr<33:32>, COND2))
196 NNPC = xc->readPC() + disp;
197 else
198 handle_annul
199 }});
200 0x2: fbpcc2(22, {{
201 if(passesFpCondition(Fsr<35:34>, COND2))
202 NNPC = xc->readPC() + disp;
203 else
204 handle_annul
205 }});
206 0x3: fbpcc3(22, {{
207 if(passesFpCondition(Fsr<37:36>, COND2))
208 NNPC = xc->readPC() + disp;
209 else
210 handle_annul
211 }});
212 }
213 }
214 }
215 //fbfcc
216 0x6: decode COND2 {
217 format BranchN {
218 //Branch Always
219 0x8: decode A
220 {
221 0x0: fba(22, {{
222 NNPC = xc->readPC() + disp;
223 }});
224 0x1: fba(22, {{
225 NPC = xc->readPC() + disp;
226 NNPC = NPC + 4;
227 }}, ',a');
228 }
229 //Branch Never
230 0x0: decode A
231 {
232 0x0: fbn(22, {{
233 NNPC = NNPC;//Don't do anything
234 }});
235 0x1: fbn(22, {{
236 NNPC = NPC + 8;
237 NPC = NPC + 4;
238 }}, ',a');
239 }
240 default: fbfcc(22, {{
241 if(passesFpCondition(Fsr<11:10>, COND2))
242 NNPC = xc->readPC() + disp;
243 else
244 handle_annul
245 }});
246 }
247 }
248 }
249 0x1: BranchN::call(30, {{
250 if (Pstate<3:>)
251 R15 = (xc->readPC())<31:0>;
252 else
253 R15 = xc->readPC();
254 NNPC = R15 + disp;
255 }});
256 0x2: decode OP3 {
257 format IntOp {
258 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
259 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
260 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
261 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
262 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
263 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}});
264 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}});
265 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
266 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
267 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
268 0x0A: umul({{
269 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
270 Y = Rd<63:32>;
271 }});
272 0x0B: smul({{
273 Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
274 Y = Rd.sdw<63:32>;
275 }});
276 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
277 0x0D: udivx({{
278 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
279 else Rd.udw = Rs1.udw / Rs2_or_imm13;
280 }});
281 0x0E: udiv({{
282 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
283 else
284 {
285 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
286 if(Rd.udw >> 32 != 0)
287 Rd.udw = 0xFFFFFFFF;
288 }
289 }});
290 0x0F: sdiv({{
291 if(Rs2_or_imm13.sdw == 0)
292 fault = new DivisionByZero;
293 else
294 {
295 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
296 if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max())
297 Rd.udw = 0x7FFFFFFF;
298 else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min())
299 Rd.udw = ULL(0xFFFFFFFF80000000);
300 }
301 }});
302 }
303 format IntOpCc {
304 0x10: addcc({{
305 int64_t resTemp, val2 = Rs2_or_imm13;
306 Rd = resTemp = Rs1 + val2;}},
307 {{(Rs1<31:0> + val2<31:0>)<32:>}},
308 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
309 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
310 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
311 );
312 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
313 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
314 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
315 0x14: subcc({{
316 int64_t val2 = Rs2_or_imm13;
317 Rd = Rs1 - val2;}},
318 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
319 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
320 {{(~(Rs1<63:1> + (~val2)<63:1> +
321 (Rs1 | ~val2)<0:>))<63:>}},
322 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
323 );
324 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
325 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
326 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
327 0x18: addccc({{
328 int64_t resTemp, val2 = Rs2_or_imm13;
329 int64_t carryin = Ccr<0:0>;
330 Rd = resTemp = Rs1 + val2 + carryin;}},
331 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
332 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
333 {{((Rs1 & val2) | (~resTemp & (Rs1 | val2)))<63:>}},
334 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
335 );
336 0x1A: IntOpCcRes::umulcc({{
337 uint64_t resTemp;
338 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
339 Y = resTemp<63:32>;}});
340 0x1B: IntOpCcRes::smulcc({{
341 int64_t resTemp;
342 Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
343 Y = resTemp<63:32>;}});
344 0x1C: subccc({{
345 int64_t resTemp, val2 = Rs2_or_imm13;
346 int64_t carryin = Ccr<0:0>;
347 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
348 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<31:>}},
349 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
350 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<63:>}},
351 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
352 );
353 0x1D: IntOpCcRes::udivxcc({{
354 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
355 else Rd = Rs1.udw / Rs2_or_imm13.udw;}});
356 0x1E: udivcc({{
357 uint32_t resTemp, val2 = Rs2_or_imm13.udw;
358 int32_t overflow = 0;
359 if(val2 == 0) fault = new DivisionByZero;
360 else
361 {
362 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
363 overflow = (resTemp<63:32> != 0);
364 if(overflow) Rd = resTemp = 0xFFFFFFFF;
365 else Rd = resTemp;
366 } }},
367 {{0}},
368 {{overflow}},
369 {{0}},
370 {{0}}
371 );
372 0x1F: sdivcc({{
373 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
374 bool overflow = false, underflow = false;
375 if(val2 == 0) fault = new DivisionByZero;
376 else
377 {
378 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
379 overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max());
380 underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min());
381 if(overflow) Rd = 0x7FFFFFFF;
382 else if(underflow) Rd = ULL(0xFFFFFFFF80000000);
383 } }},
384 {{0}},
385 {{overflow || underflow}},
386 {{0}},
387 {{0}}
388 );
389 0x20: taddcc({{
390 int64_t resTemp, val2 = Rs2_or_imm13;
391 Rd = resTemp = Rs1 + val2;
392 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
393 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
394 {{overflow}},
395 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
396 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
397 );
398 0x21: tsubcc({{
399 int64_t resTemp, val2 = Rs2_or_imm13;
400 Rd = resTemp = Rs1 + val2;
401 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
402 {{(Rs1<31:0> + val2<31:0>)<32:0>}},
403 {{overflow}},
404 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
405 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
406 );
407 0x22: taddcctv({{
408 int64_t val2 = Rs2_or_imm13;
409 Rd = Rs1 + val2;
410 int32_t overflow = Rs1<1:0> || val2<1:0> ||
411 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
412 if(overflow) fault = new TagOverflow;}},
413 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
414 {{overflow}},
415 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
416 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}}
417 );
418 0x23: tsubcctv({{
419 int64_t resTemp, val2 = Rs2_or_imm13;
420 Rd = resTemp = Rs1 + val2;
421 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
422 if(overflow) fault = new TagOverflow;}},
423 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
424 {{overflow}},
425 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
426 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
427 );
428 0x24: mulscc({{
429 int64_t resTemp, multiplicand = Rs2_or_imm13;
430 int32_t multiplier = Rs1<31:0>;
431 int32_t savedLSB = Rs1<0:>;
432 multiplier = multiplier<31:1> |
433 ((Ccr<3:3> ^ Ccr<1:1>) << 32);
434 if(!Y<0:>)
435 multiplicand = 0;
436 Rd = resTemp = multiplicand + multiplier;
437 Y = Y<31:1> | (savedLSB << 31);}},
438 {{((multiplicand<31:0> + multiplier<31:0>)<32:0>)}},
439 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
440 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
441 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
442 );
443 }
444 format IntOp
445 {
446 0x25: decode X {
447 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
448 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
449 }
450 0x26: decode X {
451 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
452 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
453 }
454 0x27: decode X {
455 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
456 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
457 }
458 0x28: decode RS1 {
459 0x00: NoPriv::rdy({{Rd = Y<31:0>;}});
460 //1 should cause an illegal instruction exception
461 0x02: NoPriv::rdccr({{Rd = Ccr;}});
462 0x03: NoPriv::rdasi({{Rd = Asi;}});
463 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
464 0x05: NoPriv::rdpc({{
465 if(Pstate<3:>)
466 Rd = (xc->readPC())<31:0>;
467 else
468 Rd = xc->readPC();}});
469 0x06: NoPriv::rdfprs({{
470 //Wait for all fpops to finish.
471 Rd = Fprs;
472 }});
473 //7-14 should cause an illegal instruction exception
474 0x0F: decode I {
475 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp);
476 0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp);
477 }
478 0x10: Priv::rdpcr({{Rd = Pcr;}});
479 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
480 //0x12 should cause an illegal instruction exception
481 0x13: NoPriv::rdgsr({{
482 fault = checkFpEnableFault(xc);
483 if (fault)
484 return fault;
485 Rd = Gsr;
486 }});
487 //0x14-0x15 should cause an illegal instruction exception
488 0x16: Priv::rdsoftint({{Rd = Softint;}});
489 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
490 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}});
491 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
492 0x1A: Priv::rdstrand_sts_reg({{
493 if(Pstate<2:> && !Hpstate<2:>)
494 Rd = StrandStsReg<0:>;
495 else
496 Rd = StrandStsReg;
497 }});
498 //0x1A is supposed to be reserved, but it reads the strand
499 //status register.
500 //0x1B-0x1F should cause an illegal instruction exception
501 }
502 0x29: decode RS1 {
503 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
504 0x01: HPriv::rdhprhtstate({{
505 if(Tl == 0)
506 return new IllegalInstruction;
507 Rd = Htstate;
508 }});
509 //0x02 should cause an illegal instruction exception
510 0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
511 //0x04 should cause an illegal instruction exception
512 0x05: HPriv::rdhprhtba({{Rd = Htba;}});
513 0x06: HPriv::rdhprhver({{Rd = Hver;}});
514 //0x07-0x1E should cause an illegal instruction exception
515 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
516 }
517 0x2A: decode RS1 {
518 0x00: Priv::rdprtpc({{
519 if(Tl == 0)
520 return new IllegalInstruction;
521 Rd = Tpc;
522 }});
523 0x01: Priv::rdprtnpc({{
524 if(Tl == 0)
525 return new IllegalInstruction;
526 Rd = Tnpc;
527 }});
528 0x02: Priv::rdprtstate({{
529 if(Tl == 0)
530 return new IllegalInstruction;
531 Rd = Tstate;
532 }});
533 0x03: Priv::rdprtt({{
534 if(Tl == 0)
535 return new IllegalInstruction;
536 Rd = Tt;
537 }});
538 0x04: Priv::rdprtick({{Rd = Tick;}});
539 0x05: Priv::rdprtba({{Rd = Tba;}});
540 0x06: Priv::rdprpstate({{Rd = Pstate;}});
541 0x07: Priv::rdprtl({{Rd = Tl;}});
542 0x08: Priv::rdprpil({{Rd = Pil;}});
543 0x09: Priv::rdprcwp({{Rd = Cwp;}});
544 0x0A: Priv::rdprcansave({{Rd = Cansave;}});
545 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});
546 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});
547 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}});
548 0x0E: Priv::rdprwstate({{Rd = Wstate;}});
549 //0x0F should cause an illegal instruction exception
550 0x10: Priv::rdprgl({{Rd = Gl;}});
551 //0x11-0x1F should cause an illegal instruction exception
552 }
553 0x2B: BasicOperate::flushw({{
554 if(NWindows - 2 - Cansave != 0)
555 {
556 if(Otherwin)
557 fault = new SpillNOther(4*Wstate<5:3>);
558 else
559 fault = new SpillNNormal(4*Wstate<2:0>);
560 }
561 }});
562 0x2C: decode MOVCC3
563 {
564 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
565 0x1: decode CC
566 {
567 0x0: movcci({{
568 if(passesCondition(Ccr<3:0>, COND4))
569 Rd = Rs2_or_imm11;
570 else
571 Rd = Rd;
572 }});
573 0x2: movccx({{
574 if(passesCondition(Ccr<7:4>, COND4))
575 Rd = Rs2_or_imm11;
576 else
577 Rd = Rd;
578 }});
579 }
580 }
581 0x2D: sdivx({{
582 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
583 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
584 }});
585 0x2E: Trap::popc({{fault = new IllegalInstruction;}});
586 0x2F: decode RCOND3
587 {
588 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
589 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
590 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
591 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
592 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
593 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
594 }
595 0x30: decode RD {
596 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}});
597 //0x01 should cause an illegal instruction exception
598 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
599 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
600 //0x04-0x05 should cause an illegal instruction exception
601 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
602 //0x07-0x0E should cause an illegal instruction exception
603 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
604 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
605 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
606 //0x12 should cause an illegal instruction exception
607 0x13: NoPriv::wrgsr({{
608 if(Fprs<2:> == 0 || Pstate<4:> == 0)
609 return new FpDisabled;
610 Gsr = Rs1 ^ Rs2_or_imm13;
611 }});
612 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
613 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});
614 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
615 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}});
616 0x18: NoPriv::wrstick({{
617 if(!Hpstate<2:>)
618 return new IllegalInstruction;
619 Stick = Rs1 ^ Rs2_or_imm13;
620 }});
621 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}});
622 0x1A: Priv::wrstrand_sts_reg({{
623 StrandStsReg = Rs1 ^ Rs2_or_imm13;
624 }});
625 //0x1A is supposed to be reserved, but it writes the strand
626 //status register.
627 //0x1B-0x1F should cause an illegal instruction exception
628 }
629 0x31: decode FCN {
630 0x0: Priv::saved({{
631 assert(Cansave < NWindows - 2);
632 assert(Otherwin || Canrestore);
633 Cansave = Cansave + 1;
634 if(Otherwin == 0)
635 Canrestore = Canrestore - 1;
636 else
637 Otherwin = Otherwin - 1;
638 }});
639 0x1: Priv::restored({{
640 assert(Cansave || Otherwin);
641 assert(Canrestore < NWindows - 2);
642 Canrestore = Canrestore + 1;
643 if(Otherwin == 0)
644 Cansave = Cansave - 1;
645 else
646 Otherwin = Otherwin - 1;
647
648 if(Cleanwin < NWindows - 1)
649 Cleanwin = Cleanwin + 1;
650 }});
651 }
652 0x32: decode RD {
653 0x00: Priv::wrprtpc({{
654 if(Tl == 0)
655 return new IllegalInstruction;
656 else
657 Tpc = Rs1 ^ Rs2_or_imm13;
658 }});
659 0x01: Priv::wrprtnpc({{
660 if(Tl == 0)
661 return new IllegalInstruction;
662 else
663 Tnpc = Rs1 ^ Rs2_or_imm13;
664 }});
665 0x02: Priv::wrprtstate({{
666 if(Tl == 0)
667 return new IllegalInstruction;
668 else
669 Tstate = Rs1 ^ Rs2_or_imm13;
670 }});
671 0x03: Priv::wrprtt({{
672 if(Tl == 0)
673 return new IllegalInstruction;
674 else
675 Tt = Rs1 ^ Rs2_or_imm13;
676 }});
677 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
678 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
679 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
680 0x07: Priv::wrprtl({{
681 if(Pstate<2:> && !Hpstate<2:>)
682 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
683 else
684 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);
685 }});
686 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
687 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
688 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
689 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
690 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
691 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
692 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
693 //0x0F should cause an illegal instruction exception
694 0x10: Priv::wrprgl({{
695 if(Pstate<2:> && !Hpstate<2:>)
696 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL);
697 else
698 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
699 }});
700 //0x11-0x1F should cause an illegal instruction exception
701 }
702 0x33: decode RD {
703 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
704 0x01: HPriv::wrhprhtstate({{
705 if(Tl == 0)
706 return new IllegalInstruction;
707 Htstate = Rs1 ^ Rs2_or_imm13;
708 }});
709 //0x02 should cause an illegal instruction exception
710 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
711 //0x04 should cause an illegal instruction exception
712 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
713 //0x06-0x01D should cause an illegal instruction exception
714 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
715 }
716 0x34: decode OPF{
717 format FpBasic{
718 0x01: fmovs({{
719 Frds.uw = Frs2s.uw;
720 //fsr.ftt = fsr.cexc = 0
721 Fsr &= ~(7 << 14);
722 Fsr &= ~(0x1F);
723 }});
724 0x02: fmovd({{
725 Frd.udw = Frs2.udw;
726 //fsr.ftt = fsr.cexc = 0
727 Fsr &= ~(7 << 14);
728 Fsr &= ~(0x1F);
729 }});
730 0x03: FpUnimpl::fmovq();
731 0x05: fnegs({{
732 Frds.uw = Frs2s.uw ^ (1UL << 31);
733 //fsr.ftt = fsr.cexc = 0
734 Fsr &= ~(7 << 14);
735 Fsr &= ~(0x1F);
736 }});
737 0x06: fnegd({{
738 Frd.udw = Frs2.udw ^ (1ULL << 63);
739 //fsr.ftt = fsr.cexc = 0
740 Fsr &= ~(7 << 14);
741 Fsr &= ~(0x1F);
742 }});
743 0x07: FpUnimpl::fnegq();
744 0x09: fabss({{
745 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;
746 //fsr.ftt = fsr.cexc = 0
747 Fsr &= ~(7 << 14);
748 Fsr &= ~(0x1F);
749 }});
750 0x0A: fabsd({{
751 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;
752 //fsr.ftt = fsr.cexc = 0
753 Fsr &= ~(7 << 14);
754 Fsr &= ~(0x1F);
755 }});
756 0x0B: FpUnimpl::fabsq();
757 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}});
758 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}});
759 0x2B: FpUnimpl::fsqrtq();
760 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
761 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
762 0x43: FpUnimpl::faddq();
763 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
764 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df; }});
765 0x47: FpUnimpl::fsubq();
766 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
767 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
768 0x4B: FpUnimpl::fmulq();
769 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
770 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
771 0x4F: FpUnimpl::fdivq();
772 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
773 0x6E: FpUnimpl::fdmulq();
774 0x81: fstox({{
775 Frd.sdw = static_cast<int64_t>(Frs2s.sf);
776 }});
777 0x82: fdtox({{
778 Frd.sdw = static_cast<int64_t>(Frs2.df);
779 }});
780 0x83: FpUnimpl::fqtox();
781 0x84: fxtos({{
782 Frds.sf = static_cast<float>(Frs2.sdw);
783 }});
784 0x88: fxtod({{
785 Frd.df = static_cast<double>(Frs2.sdw);
786 }});
787 0x8C: FpUnimpl::fxtoq();
788 0xC4: fitos({{
789 Frds.sf = static_cast<float>(Frs2s.sw);
790 }});
791 0xC6: fdtos({{Frds.sf = Frs2.df;}});
792 0xC7: FpUnimpl::fqtos();
793 0xC8: fitod({{
794 Frd.df = static_cast<double>(Frs2s.sw);
795 }});
796 0xC9: fstod({{Frd.df = Frs2s.sf;}});
797 0xCB: FpUnimpl::fqtod();
798 0xCC: FpUnimpl::fitoq();
799 0xCD: FpUnimpl::fstoq();
800 0xCE: FpUnimpl::fdtoq();
801 0xD1: fstoi({{
802 Frds.sw = static_cast<int32_t>(Frs2s.sf);
803 float t = Frds.sw;
804 if (t != Frs2s.sf)
805 Fsr = insertBits(Fsr, 4,0, 0x01);
806 }});
807 0xD2: fdtoi({{
808 Frds.sw = static_cast<int32_t>(Frs2.df);
809 double t = Frds.sw;
810 if (t != Frs2.df)
811 Fsr = insertBits(Fsr, 4,0, 0x01);
812 }});
813 0xD3: FpUnimpl::fqtoi();
814 default: FailUnimpl::fpop1();
815 }
816 }
817 0x35: decode OPF{
818 format FpBasic{
819 0x01: fmovs_fcc0({{
820 if(passesFpCondition(Fsr<11:10>, COND4))
821 Frds = Frs2s;
822 else
823 Frds = Frds;
824 }});
825 0x02: fmovd_fcc0({{
826 if(passesFpCondition(Fsr<11:10>, COND4))
827 Frd = Frs2;
828 else
829 Frd = Frd;
830 }});
831 0x03: FpUnimpl::fmovq_fcc0();
832 0x25: fmovrsz({{
833 if(Rs1 == 0)
834 Frds = Frs2s;
835 else
836 Frds = Frds;
837 }});
838 0x26: fmovrdz({{
839 if(Rs1 == 0)
840 Frd = Frs2;
841 else
842 Frd = Frd;
843 }});
844 0x27: FpUnimpl::fmovrqz();
845 0x41: fmovs_fcc1({{
846 if(passesFpCondition(Fsr<33:32>, COND4))
847 Frds = Frs2s;
848 else
849 Frds = Frds;
850 }});
851 0x42: fmovd_fcc1({{
852 if(passesFpCondition(Fsr<33:32>, COND4))
853 Frd = Frs2;
854 else
855 Frd = Frd;
856 }});
857 0x43: FpUnimpl::fmovq_fcc1();
858 0x45: fmovrslez({{
859 if(Rs1 <= 0)
860 Frds = Frs2s;
861 else
862 Frds = Frds;
863 }});
864 0x46: fmovrdlez({{
865 if(Rs1 <= 0)
866 Frd = Frs2;
867 else
868 Frd = Frd;
869 }});
870 0x47: FpUnimpl::fmovrqlez();
871 0x51: fcmps({{
872 uint8_t fcc;
873 if(isnan(Frs1s) || isnan(Frs2s))
874 fcc = 3;
875 else if(Frs1s < Frs2s)
876 fcc = 1;
877 else if(Frs1s > Frs2s)
878 fcc = 2;
879 else
880 fcc = 0;
881 uint8_t firstbit = 10;
882 if(FCMPCC)
883 firstbit = FCMPCC * 2 + 30;
884 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
885 }});
886 0x52: fcmpd({{
887 uint8_t fcc;
888 if(isnan(Frs1) || isnan(Frs2))
889 fcc = 3;
890 else if(Frs1 < Frs2)
891 fcc = 1;
892 else if(Frs1 > Frs2)
893 fcc = 2;
894 else
895 fcc = 0;
896 uint8_t firstbit = 10;
897 if(FCMPCC)
898 firstbit = FCMPCC * 2 + 30;
899 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
900 }});
901 0x53: FpUnimpl::fcmpq();
902 0x55: fcmpes({{
903 uint8_t fcc = 0;
904 if(isnan(Frs1s) || isnan(Frs2s))
905 fault = new FpExceptionIEEE754;
906 if(Frs1s < Frs2s)
907 fcc = 1;
908 else if(Frs1s > Frs2s)
909 fcc = 2;
910 uint8_t firstbit = 10;
911 if(FCMPCC)
912 firstbit = FCMPCC * 2 + 30;
913 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
914 }});
915 0x56: fcmped({{
916 uint8_t fcc = 0;
917 if(isnan(Frs1) || isnan(Frs2))
918 fault = new FpExceptionIEEE754;
919 if(Frs1 < Frs2)
920 fcc = 1;
921 else if(Frs1 > Frs2)
922 fcc = 2;
923 uint8_t firstbit = 10;
924 if(FCMPCC)
925 firstbit = FCMPCC * 2 + 30;
926 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
927 }});
928 0x57: FpUnimpl::fcmpeq();
929 0x65: fmovrslz({{
930 if(Rs1 < 0)
931 Frds = Frs2s;
932 else
933 Frds = Frds;
934 }});
935 0x66: fmovrdlz({{
936 if(Rs1 < 0)
937 Frd = Frs2;
938 else
939 Frd = Frd;
940 }});
941 0x67: FpUnimpl::fmovrqlz();
942 0x81: fmovs_fcc2({{
943 if(passesFpCondition(Fsr<35:34>, COND4))
944 Frds = Frs2s;
945 else
946 Frds = Frds;
947 }});
948 0x82: fmovd_fcc2({{
949 if(passesFpCondition(Fsr<35:34>, COND4))
950 Frd = Frs2;
951 else
952 Frd = Frd;
953 }});
954 0x83: FpUnimpl::fmovq_fcc2();
955 0xA5: fmovrsnz({{
956 if(Rs1 != 0)
957 Frds = Frs2s;
958 else
959 Frds = Frds;
960 }});
961 0xA6: fmovrdnz({{
962 if(Rs1 != 0)
963 Frd = Frs2;
964 else
965 Frd = Frd;
966 }});
967 0xA7: FpUnimpl::fmovrqnz();
968 0xC1: fmovs_fcc3({{
969 if(passesFpCondition(Fsr<37:36>, COND4))
970 Frds = Frs2s;
971 else
972 Frds = Frds;
973 }});
974 0xC2: fmovd_fcc3({{
975 if(passesFpCondition(Fsr<37:36>, COND4))
976 Frd = Frs2;
977 else
978 Frd = Frd;
979 }});
980 0xC3: FpUnimpl::fmovq_fcc3();
981 0xC5: fmovrsgz({{
982 if(Rs1 > 0)
983 Frds = Frs2s;
984 else
985 Frds = Frds;
986 }});
987 0xC6: fmovrdgz({{
988 if(Rs1 > 0)
989 Frd = Frs2;
990 else
991 Frd = Frd;
992 }});
993 0xC7: FpUnimpl::fmovrqgz();
994 0xE5: fmovrsgez({{
995 if(Rs1 >= 0)
996 Frds = Frs2s;
997 else
998 Frds = Frds;
999 }});
1000 0xE6: fmovrdgez({{
1001 if(Rs1 >= 0)
1002 Frd = Frs2;
1003 else
1004 Frd = Frd;
1005 }});
1006 0xE7: FpUnimpl::fmovrqgez();
1007 0x101: fmovs_icc({{
1008 if(passesCondition(Ccr<3:0>, COND4))
1009 Frds = Frs2s;
1010 else
1011 Frds = Frds;
1012 }});
1013 0x102: fmovd_icc({{
1014 if(passesCondition(Ccr<3:0>, COND4))
1015 Frd = Frs2;
1016 else
1017 Frd = Frd;
1018 }});
1019 0x103: FpUnimpl::fmovq_icc();
1020 0x181: fmovs_xcc({{
1021 if(passesCondition(Ccr<7:4>, COND4))
1022 Frds = Frs2s;
1023 else
1024 Frds = Frds;
1025 }});
1026 0x182: fmovd_xcc({{
1027 if(passesCondition(Ccr<7:4>, COND4))
1028 Frd = Frs2;
1029 else
1030 Frd = Frd;
1031 }});
1032 0x183: FpUnimpl::fmovq_xcc();
1033 default: FailUnimpl::fpop2();
1034 }
1035 }
1036 //This used to be just impdep1, but now it's a whole bunch
1037 //of instructions
1038 0x36: decode OPF{
1039 0x00: FailUnimpl::edge8();
1040 0x01: FailUnimpl::edge8n();
1041 0x02: FailUnimpl::edge8l();
1042 0x03: FailUnimpl::edge8ln();
1043 0x04: FailUnimpl::edge16();
1044 0x05: FailUnimpl::edge16n();
1045 0x06: FailUnimpl::edge16l();
1046 0x07: FailUnimpl::edge16ln();
1047 0x08: FailUnimpl::edge32();
1048 0x09: FailUnimpl::edge32n();
1049 0x0A: FailUnimpl::edge32l();
1050 0x0B: FailUnimpl::edge32ln();
1051 0x10: FailUnimpl::array8();
1052 0x12: FailUnimpl::array16();
1053 0x14: FailUnimpl::array32();
1054 0x18: BasicOperate::alignaddr({{
1055 uint64_t sum = Rs1 + Rs2;
1056 Rd = sum & ~7;
1057 Gsr = (Gsr & ~7) | (sum & 7);
1058 }});
1059 0x19: FailUnimpl::bmask();
1060 0x1A: BasicOperate::alignaddresslittle({{
1061 uint64_t sum = Rs1 + Rs2;
1062 Rd = sum & ~7;
1063 Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
1064 }});
1065 0x20: FailUnimpl::fcmple16();
1066 0x22: FailUnimpl::fcmpne16();
1067 0x24: FailUnimpl::fcmple32();
1068 0x26: FailUnimpl::fcmpne32();
1069 0x28: FailUnimpl::fcmpgt16();
1070 0x2A: FailUnimpl::fcmpeq16();
1071 0x2C: FailUnimpl::fcmpgt32();
1072 0x2E: FailUnimpl::fcmpeq32();
1073 0x31: FailUnimpl::fmul8x16();
1074 0x33: FailUnimpl::fmul8x16au();
1075 0x35: FailUnimpl::fmul8x16al();
1076 0x36: FailUnimpl::fmul8sux16();
1077 0x37: FailUnimpl::fmul8ulx16();
1078 0x38: FailUnimpl::fmuld8sux16();
1079 0x39: FailUnimpl::fmuld8ulx16();
1080 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
1081 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
1082 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
1083 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
1084 0x48: BasicOperate::faligndata({{
1085 uint64_t msbX = Frs1.udw;
1086 uint64_t lsbX = Frs2.udw;
1087 //Some special cases need to be split out, first
1088 //because they're the most likely to be used, and
1089 //second because otherwise, we end up shifting by
1090 //greater than the width of the type being shifted,
1091 //namely 64, which produces undefined results according
1092 //to the C standard.
1093 switch(Gsr<2:0>)
1094 {
1095 case 0:
1096 Frd.udw = msbX;
1097 break;
1098 case 8:
1099 Frd.udw = lsbX;
1100 break;
1101 default:
1102 uint64_t msbShift = Gsr<2:0> * 8;
1103 uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
1104 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
1105 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
1106 Frd.udw = ((msbX & msbMask) << msbShift) |
1107 ((lsbX & lsbMask) >> lsbShift);
1108 }
1109 }});
1110 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
1111 0x4C: FailUnimpl::bshuffle();
1112 0x4D: FailUnimpl::fexpand();
1113 0x50: FailUnimpl::fpadd16();
1114 0x51: FailUnimpl::fpadd16s();
1115 0x52: FailUnimpl::fpadd32();
1116 0x53: FailUnimpl::fpadd32s();
1117 0x54: FailUnimpl::fpsub16();
1118 0x55: FailUnimpl::fpsub16s();
1119 0x56: FailUnimpl::fpsub32();
1120 0x57: FailUnimpl::fpsub32s();
1121 0x60: FpBasic::fzero({{Frd.df = 0;}});
1122 0x61: FpBasic::fzeros({{Frds.sf = 0;}});
1123 0x62: FailUnimpl::fnor();
1124 0x63: FailUnimpl::fnors();
1125 0x64: FailUnimpl::fandnot2();
1126 0x65: FailUnimpl::fandnot2s();
1127 0x66: FpBasic::fnot2({{
1128 Frd.df = (double)(~((uint64_t)Frs2.df));
1129 }});
1130 0x67: FpBasic::fnot2s({{
1131 Frds.sf = (float)(~((uint32_t)Frs2s.sf));
1132 }});
1133 0x68: FailUnimpl::fandnot1();
1134 0x69: FailUnimpl::fandnot1s();
1135 0x6A: FpBasic::fnot1({{
1136 Frd.df = (double)(~((uint64_t)Frs1.df));
1137 }});
1138 0x6B: FpBasic::fnot1s({{
1139 Frds.sf = (float)(~((uint32_t)Frs1s.sf));
1140 }});
1141 0x6C: FailUnimpl::fxor();
1142 0x6D: FailUnimpl::fxors();
1143 0x6E: FailUnimpl::fnand();
1144 0x6F: FailUnimpl::fnands();
1145 0x70: FailUnimpl::fand();
1146 0x71: FailUnimpl::fands();
1147 0x72: FailUnimpl::fxnor();
1148 0x73: FailUnimpl::fxnors();
1149 0x74: FpBasic::fsrc1({{Frd.udw = Frs1.udw;}});
1150 0x75: FpBasic::fsrc1s({{Frds.uw = Frs1s.uw;}});
1151 0x76: FailUnimpl::fornot2();
1152 0x77: FailUnimpl::fornot2s();
1153 0x78: FpBasic::fsrc2({{Frd.udw = Frs2.udw;}});
1154 0x79: FpBasic::fsrc2s({{Frds.uw = Frs2s.uw;}});
1155 0x7A: FailUnimpl::fornot1();
1156 0x7B: FailUnimpl::fornot1s();
1157 0x7C: FailUnimpl::for();
1158 0x7D: FailUnimpl::fors();
1159 0x7E: FpBasic::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}});
1160 0x7F: FpBasic::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}});
1161 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
1162 0x81: FailUnimpl::siam();
1163 }
1164 // M5 special opcodes use the reserved IMPDEP2A opcode space
1165 0x37: decode M5FUNC {
1166#if FULL_SYSTEM
1167 format BasicOperate {
1168 // we have 7 bits of space here to play with...
1169 0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0);
1170 }}, No_OpClass, IsNonSpeculative);
1171 0x50: m5readfile({{
1172 O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2);
1173 }}, IsNonSpeculative);
1174 0x51: m5break({{PseudoInst::debugbreak(xc->tcBase());
1175 }}, IsNonSpeculative);
1176 0x54: m5panic({{
1177 panic("M5 panic instruction called at pc=%#x.", xc->readPC());
1178 }}, No_OpClass, IsNonSpeculative);
1179 }
1180#endif
1181 default: Trap::impdep2({{fault = new IllegalInstruction;}});
1182 }
1183 0x38: Branch::jmpl({{
1184 Addr target = Rs1 + Rs2_or_imm13;
1185 if(target & 0x3)
1186 fault = new MemAddressNotAligned;
1187 else
1188 {
1189 if (Pstate<3:>)
1190 Rd = (xc->readPC())<31:0>;
1191 else
1192 Rd = xc->readPC();
1193 NNPC = target;
1194 }
1195 }});
1196 0x39: Branch::return({{
1197 Addr target = Rs1 + Rs2_or_imm13;
1198 if(fault == NoFault)
1199 {
1200 //Check for fills which are higher priority than alignment
1201 //faults.
1202 if(Canrestore == 0)
1203 {
1204 if(Otherwin)
1205 fault = new FillNOther(4*Wstate<5:3>);
1206 else
1207 fault = new FillNNormal(4*Wstate<2:0>);
1208 }
1209 //Check for alignment faults
1210 else if(target & 0x3)
1211 fault = new MemAddressNotAligned;
1212 else
1213 {
1214 NNPC = target;
1215 Cwp = (Cwp - 1 + NWindows) % NWindows;
1216 Cansave = Cansave + 1;
1217 Canrestore = Canrestore - 1;
1218 }
1219 }
1220 }});
1221 0x3A: decode CC
1222 {
1223 0x0: Trap::tcci({{
1224 if(passesCondition(Ccr<3:0>, COND2))
1225 {
1226 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
1227 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
1228 fault = new TrapInstruction(lTrapNum);
1229 }
1230 }}, IsSerializeAfter, IsNonSpeculative);
1231 0x2: Trap::tccx({{
1232 if(passesCondition(Ccr<7:4>, COND2))
1233 {
1234 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
1235 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
1236 fault = new TrapInstruction(lTrapNum);
1237 }
1238 }}, IsSerializeAfter, IsNonSpeculative);
1239 }
1240 0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier,
1241 MemWriteOp);
1242 0x3C: save({{
1243 if(Cansave == 0)
1244 {
1245 if(Otherwin)
1246 fault = new SpillNOther(4*Wstate<5:3>);
1247 else
1248 fault = new SpillNNormal(4*Wstate<2:0>);
1249 }
1250 else if(Cleanwin - Canrestore == 0)
1251 {
1252 fault = new CleanWindow;
1253 }
1254 else
1255 {
1256 Cwp = (Cwp + 1) % NWindows;
1257 Rd_next = Rs1 + Rs2_or_imm13;
1258 Cansave = Cansave - 1;
1259 Canrestore = Canrestore + 1;
1260 }
1261 }});
1262 0x3D: restore({{
1263 if(Canrestore == 0)
1264 {
1265 if(Otherwin)
1266 fault = new FillNOther(4*Wstate<5:3>);
1267 else
1268 fault = new FillNNormal(4*Wstate<2:0>);
1269 }
1270 else
1271 {
1272 Cwp = (Cwp - 1 + NWindows) % NWindows;
1273 Rd_prev = Rs1 + Rs2_or_imm13;
1274 Cansave = Cansave + 1;
1275 Canrestore = Canrestore - 1;
1276 }
1277 }});
1278 0x3E: decode FCN {
1279 0x0: Priv::done({{
1280 if(Tl == 0)
1281 return new IllegalInstruction;
1282
1283 Cwp = Tstate<4:0>;
1284 Pstate = Tstate<20:8>;
1285 Asi = Tstate<31:24>;
1286 Ccr = Tstate<39:32>;
1287 Gl = Tstate<42:40>;
1288 Hpstate = Htstate;
1289 NPC = Tnpc;
1290 NNPC = Tnpc + 4;
1291 Tl = Tl - 1;
1292 }});
1293 0x1: Priv::retry({{
1294 if(Tl == 0)
1295 return new IllegalInstruction;
1296 Cwp = Tstate<4:0>;
1297 Pstate = Tstate<20:8>;
1298 Asi = Tstate<31:24>;
1299 Ccr = Tstate<39:32>;
1300 Gl = Tstate<42:40>;
1301 Hpstate = Htstate;
1302 NPC = Tpc;
1303 NNPC = Tnpc;
1304 Tl = Tl - 1;
1305 }});
1306 }
1307 }
1308 }
1309 0x3: decode OP3 {
1310 format Load {
1311 0x00: lduw({{Rd = Mem.uw;}});
1312 0x01: ldub({{Rd = Mem.ub;}});
1313 0x02: lduh({{Rd = Mem.uhw;}});
1314 0x03: ldtw({{
1315 RdLow = (Mem.tuw).a;
1316 RdHigh = (Mem.tuw).b;
1317 }});
1318 }
1319 format Store {
1320 0x04: stw({{Mem.uw = Rd.sw;}});
1321 0x05: stb({{Mem.ub = Rd.sb;}});
1322 0x06: sth({{Mem.uhw = Rd.shw;}});
| 1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OP default Unknown::unknown()
37{
38 0x0: decode OP2
39 {
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 //bpcc
45 0x1: decode COND2
46 {
47 //Branch Always
48 0x8: decode A
49 {
50 0x0: bpa(19, {{
51 NNPC = xc->readPC() + disp;
52 }});
53 0x1: bpa(19, {{
54 NPC = xc->readPC() + disp;
55 NNPC = NPC + 4;
56 }}, ',a');
57 }
58 //Branch Never
59 0x0: decode A
60 {
61 0x0: bpn(19, {{
62 NNPC = NNPC;//Don't do anything
63 }});
64 0x1: bpn(19, {{
65 NNPC = NPC + 8;
66 NPC = NPC + 4;
67 }}, ',a');
68 }
69 default: decode BPCC
70 {
71 0x0: bpcci(19, {{
72 if(passesCondition(Ccr<3:0>, COND2))
73 NNPC = xc->readPC() + disp;
74 else
75 handle_annul
76 }});
77 0x2: bpccx(19, {{
78 if(passesCondition(Ccr<7:4>, COND2))
79 NNPC = xc->readPC() + disp;
80 else
81 handle_annul
82 }});
83 }
84 }
85 //bicc
86 0x2: decode COND2
87 {
88 //Branch Always
89 0x8: decode A
90 {
91 0x0: ba(22, {{
92 NNPC = xc->readPC() + disp;
93 }});
94 0x1: ba(22, {{
95 NPC = xc->readPC() + disp;
96 NNPC = NPC + 4;
97 }}, ',a');
98 }
99 //Branch Never
100 0x0: decode A
101 {
102 0x0: bn(22, {{
103 NNPC = NNPC;//Don't do anything
104 }});
105 0x1: bn(22, {{
106 NNPC = NPC + 8;
107 NPC = NPC + 4;
108 }}, ',a');
109 }
110 default: bicc(22, {{
111 if(passesCondition(Ccr<3:0>, COND2))
112 NNPC = xc->readPC() + disp;
113 else
114 handle_annul
115 }});
116 }
117 }
118 0x3: decode RCOND2
119 {
120 format BranchSplit
121 {
122 0x1: bpreq({{
123 if(Rs1.sdw == 0)
124 NNPC = xc->readPC() + disp;
125 else
126 handle_annul
127 }});
128 0x2: bprle({{
129 if(Rs1.sdw <= 0)
130 NNPC = xc->readPC() + disp;
131 else
132 handle_annul
133 }});
134 0x3: bprl({{
135 if(Rs1.sdw < 0)
136 NNPC = xc->readPC() + disp;
137 else
138 handle_annul
139 }});
140 0x5: bprne({{
141 if(Rs1.sdw != 0)
142 NNPC = xc->readPC() + disp;
143 else
144 handle_annul
145 }});
146 0x6: bprg({{
147 if(Rs1.sdw > 0)
148 NNPC = xc->readPC() + disp;
149 else
150 handle_annul
151 }});
152 0x7: bprge({{
153 if(Rs1.sdw >= 0)
154 NNPC = xc->readPC() + disp;
155 else
156 handle_annul
157 }});
158 }
159 }
160 //SETHI (or NOP if rd == 0 and imm == 0)
161 0x4: SetHi::sethi({{Rd.udw = imm;}});
162 //fbpfcc
163 0x5: decode COND2 {
164 format BranchN {
165 //Branch Always
166 0x8: decode A
167 {
168 0x0: fbpa(22, {{
169 NNPC = xc->readPC() + disp;
170 }});
171 0x1: fbpa(22, {{
172 NPC = xc->readPC() + disp;
173 NNPC = NPC + 4;
174 }}, ',a');
175 }
176 //Branch Never
177 0x0: decode A
178 {
179 0x0: fbpn(22, {{
180 NNPC = NNPC;//Don't do anything
181 }});
182 0x1: fbpn(22, {{
183 NNPC = NPC + 8;
184 NPC = NPC + 4;
185 }}, ',a');
186 }
187 default: decode BPCC {
188 0x0: fbpcc0(22, {{
189 if(passesFpCondition(Fsr<11:10>, COND2))
190 NNPC = xc->readPC() + disp;
191 else
192 handle_annul
193 }});
194 0x1: fbpcc1(22, {{
195 if(passesFpCondition(Fsr<33:32>, COND2))
196 NNPC = xc->readPC() + disp;
197 else
198 handle_annul
199 }});
200 0x2: fbpcc2(22, {{
201 if(passesFpCondition(Fsr<35:34>, COND2))
202 NNPC = xc->readPC() + disp;
203 else
204 handle_annul
205 }});
206 0x3: fbpcc3(22, {{
207 if(passesFpCondition(Fsr<37:36>, COND2))
208 NNPC = xc->readPC() + disp;
209 else
210 handle_annul
211 }});
212 }
213 }
214 }
215 //fbfcc
216 0x6: decode COND2 {
217 format BranchN {
218 //Branch Always
219 0x8: decode A
220 {
221 0x0: fba(22, {{
222 NNPC = xc->readPC() + disp;
223 }});
224 0x1: fba(22, {{
225 NPC = xc->readPC() + disp;
226 NNPC = NPC + 4;
227 }}, ',a');
228 }
229 //Branch Never
230 0x0: decode A
231 {
232 0x0: fbn(22, {{
233 NNPC = NNPC;//Don't do anything
234 }});
235 0x1: fbn(22, {{
236 NNPC = NPC + 8;
237 NPC = NPC + 4;
238 }}, ',a');
239 }
240 default: fbfcc(22, {{
241 if(passesFpCondition(Fsr<11:10>, COND2))
242 NNPC = xc->readPC() + disp;
243 else
244 handle_annul
245 }});
246 }
247 }
248 }
249 0x1: BranchN::call(30, {{
250 if (Pstate<3:>)
251 R15 = (xc->readPC())<31:0>;
252 else
253 R15 = xc->readPC();
254 NNPC = R15 + disp;
255 }});
256 0x2: decode OP3 {
257 format IntOp {
258 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
259 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
260 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
261 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
262 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
263 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}});
264 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}});
265 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
266 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
267 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
268 0x0A: umul({{
269 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
270 Y = Rd<63:32>;
271 }});
272 0x0B: smul({{
273 Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
274 Y = Rd.sdw<63:32>;
275 }});
276 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
277 0x0D: udivx({{
278 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
279 else Rd.udw = Rs1.udw / Rs2_or_imm13;
280 }});
281 0x0E: udiv({{
282 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
283 else
284 {
285 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
286 if(Rd.udw >> 32 != 0)
287 Rd.udw = 0xFFFFFFFF;
288 }
289 }});
290 0x0F: sdiv({{
291 if(Rs2_or_imm13.sdw == 0)
292 fault = new DivisionByZero;
293 else
294 {
295 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
296 if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max())
297 Rd.udw = 0x7FFFFFFF;
298 else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min())
299 Rd.udw = ULL(0xFFFFFFFF80000000);
300 }
301 }});
302 }
303 format IntOpCc {
304 0x10: addcc({{
305 int64_t resTemp, val2 = Rs2_or_imm13;
306 Rd = resTemp = Rs1 + val2;}},
307 {{(Rs1<31:0> + val2<31:0>)<32:>}},
308 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
309 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
310 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
311 );
312 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
313 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
314 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
315 0x14: subcc({{
316 int64_t val2 = Rs2_or_imm13;
317 Rd = Rs1 - val2;}},
318 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
319 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
320 {{(~(Rs1<63:1> + (~val2)<63:1> +
321 (Rs1 | ~val2)<0:>))<63:>}},
322 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
323 );
324 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
325 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
326 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
327 0x18: addccc({{
328 int64_t resTemp, val2 = Rs2_or_imm13;
329 int64_t carryin = Ccr<0:0>;
330 Rd = resTemp = Rs1 + val2 + carryin;}},
331 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
332 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
333 {{((Rs1 & val2) | (~resTemp & (Rs1 | val2)))<63:>}},
334 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
335 );
336 0x1A: IntOpCcRes::umulcc({{
337 uint64_t resTemp;
338 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
339 Y = resTemp<63:32>;}});
340 0x1B: IntOpCcRes::smulcc({{
341 int64_t resTemp;
342 Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
343 Y = resTemp<63:32>;}});
344 0x1C: subccc({{
345 int64_t resTemp, val2 = Rs2_or_imm13;
346 int64_t carryin = Ccr<0:0>;
347 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
348 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<31:>}},
349 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
350 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<63:>}},
351 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
352 );
353 0x1D: IntOpCcRes::udivxcc({{
354 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
355 else Rd = Rs1.udw / Rs2_or_imm13.udw;}});
356 0x1E: udivcc({{
357 uint32_t resTemp, val2 = Rs2_or_imm13.udw;
358 int32_t overflow = 0;
359 if(val2 == 0) fault = new DivisionByZero;
360 else
361 {
362 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
363 overflow = (resTemp<63:32> != 0);
364 if(overflow) Rd = resTemp = 0xFFFFFFFF;
365 else Rd = resTemp;
366 } }},
367 {{0}},
368 {{overflow}},
369 {{0}},
370 {{0}}
371 );
372 0x1F: sdivcc({{
373 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
374 bool overflow = false, underflow = false;
375 if(val2 == 0) fault = new DivisionByZero;
376 else
377 {
378 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
379 overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max());
380 underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min());
381 if(overflow) Rd = 0x7FFFFFFF;
382 else if(underflow) Rd = ULL(0xFFFFFFFF80000000);
383 } }},
384 {{0}},
385 {{overflow || underflow}},
386 {{0}},
387 {{0}}
388 );
389 0x20: taddcc({{
390 int64_t resTemp, val2 = Rs2_or_imm13;
391 Rd = resTemp = Rs1 + val2;
392 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
393 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
394 {{overflow}},
395 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
396 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
397 );
398 0x21: tsubcc({{
399 int64_t resTemp, val2 = Rs2_or_imm13;
400 Rd = resTemp = Rs1 + val2;
401 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
402 {{(Rs1<31:0> + val2<31:0>)<32:0>}},
403 {{overflow}},
404 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
405 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
406 );
407 0x22: taddcctv({{
408 int64_t val2 = Rs2_or_imm13;
409 Rd = Rs1 + val2;
410 int32_t overflow = Rs1<1:0> || val2<1:0> ||
411 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
412 if(overflow) fault = new TagOverflow;}},
413 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
414 {{overflow}},
415 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
416 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}}
417 );
418 0x23: tsubcctv({{
419 int64_t resTemp, val2 = Rs2_or_imm13;
420 Rd = resTemp = Rs1 + val2;
421 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
422 if(overflow) fault = new TagOverflow;}},
423 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
424 {{overflow}},
425 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
426 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
427 );
428 0x24: mulscc({{
429 int64_t resTemp, multiplicand = Rs2_or_imm13;
430 int32_t multiplier = Rs1<31:0>;
431 int32_t savedLSB = Rs1<0:>;
432 multiplier = multiplier<31:1> |
433 ((Ccr<3:3> ^ Ccr<1:1>) << 32);
434 if(!Y<0:>)
435 multiplicand = 0;
436 Rd = resTemp = multiplicand + multiplier;
437 Y = Y<31:1> | (savedLSB << 31);}},
438 {{((multiplicand<31:0> + multiplier<31:0>)<32:0>)}},
439 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
440 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
441 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
442 );
443 }
444 format IntOp
445 {
446 0x25: decode X {
447 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
448 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
449 }
450 0x26: decode X {
451 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
452 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
453 }
454 0x27: decode X {
455 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
456 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
457 }
458 0x28: decode RS1 {
459 0x00: NoPriv::rdy({{Rd = Y<31:0>;}});
460 //1 should cause an illegal instruction exception
461 0x02: NoPriv::rdccr({{Rd = Ccr;}});
462 0x03: NoPriv::rdasi({{Rd = Asi;}});
463 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
464 0x05: NoPriv::rdpc({{
465 if(Pstate<3:>)
466 Rd = (xc->readPC())<31:0>;
467 else
468 Rd = xc->readPC();}});
469 0x06: NoPriv::rdfprs({{
470 //Wait for all fpops to finish.
471 Rd = Fprs;
472 }});
473 //7-14 should cause an illegal instruction exception
474 0x0F: decode I {
475 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp);
476 0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp);
477 }
478 0x10: Priv::rdpcr({{Rd = Pcr;}});
479 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
480 //0x12 should cause an illegal instruction exception
481 0x13: NoPriv::rdgsr({{
482 fault = checkFpEnableFault(xc);
483 if (fault)
484 return fault;
485 Rd = Gsr;
486 }});
487 //0x14-0x15 should cause an illegal instruction exception
488 0x16: Priv::rdsoftint({{Rd = Softint;}});
489 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
490 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}});
491 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
492 0x1A: Priv::rdstrand_sts_reg({{
493 if(Pstate<2:> && !Hpstate<2:>)
494 Rd = StrandStsReg<0:>;
495 else
496 Rd = StrandStsReg;
497 }});
498 //0x1A is supposed to be reserved, but it reads the strand
499 //status register.
500 //0x1B-0x1F should cause an illegal instruction exception
501 }
502 0x29: decode RS1 {
503 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
504 0x01: HPriv::rdhprhtstate({{
505 if(Tl == 0)
506 return new IllegalInstruction;
507 Rd = Htstate;
508 }});
509 //0x02 should cause an illegal instruction exception
510 0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
511 //0x04 should cause an illegal instruction exception
512 0x05: HPriv::rdhprhtba({{Rd = Htba;}});
513 0x06: HPriv::rdhprhver({{Rd = Hver;}});
514 //0x07-0x1E should cause an illegal instruction exception
515 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
516 }
517 0x2A: decode RS1 {
518 0x00: Priv::rdprtpc({{
519 if(Tl == 0)
520 return new IllegalInstruction;
521 Rd = Tpc;
522 }});
523 0x01: Priv::rdprtnpc({{
524 if(Tl == 0)
525 return new IllegalInstruction;
526 Rd = Tnpc;
527 }});
528 0x02: Priv::rdprtstate({{
529 if(Tl == 0)
530 return new IllegalInstruction;
531 Rd = Tstate;
532 }});
533 0x03: Priv::rdprtt({{
534 if(Tl == 0)
535 return new IllegalInstruction;
536 Rd = Tt;
537 }});
538 0x04: Priv::rdprtick({{Rd = Tick;}});
539 0x05: Priv::rdprtba({{Rd = Tba;}});
540 0x06: Priv::rdprpstate({{Rd = Pstate;}});
541 0x07: Priv::rdprtl({{Rd = Tl;}});
542 0x08: Priv::rdprpil({{Rd = Pil;}});
543 0x09: Priv::rdprcwp({{Rd = Cwp;}});
544 0x0A: Priv::rdprcansave({{Rd = Cansave;}});
545 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});
546 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});
547 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}});
548 0x0E: Priv::rdprwstate({{Rd = Wstate;}});
549 //0x0F should cause an illegal instruction exception
550 0x10: Priv::rdprgl({{Rd = Gl;}});
551 //0x11-0x1F should cause an illegal instruction exception
552 }
553 0x2B: BasicOperate::flushw({{
554 if(NWindows - 2 - Cansave != 0)
555 {
556 if(Otherwin)
557 fault = new SpillNOther(4*Wstate<5:3>);
558 else
559 fault = new SpillNNormal(4*Wstate<2:0>);
560 }
561 }});
562 0x2C: decode MOVCC3
563 {
564 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
565 0x1: decode CC
566 {
567 0x0: movcci({{
568 if(passesCondition(Ccr<3:0>, COND4))
569 Rd = Rs2_or_imm11;
570 else
571 Rd = Rd;
572 }});
573 0x2: movccx({{
574 if(passesCondition(Ccr<7:4>, COND4))
575 Rd = Rs2_or_imm11;
576 else
577 Rd = Rd;
578 }});
579 }
580 }
581 0x2D: sdivx({{
582 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
583 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
584 }});
585 0x2E: Trap::popc({{fault = new IllegalInstruction;}});
586 0x2F: decode RCOND3
587 {
588 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
589 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
590 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
591 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
592 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
593 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
594 }
595 0x30: decode RD {
596 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}});
597 //0x01 should cause an illegal instruction exception
598 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
599 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
600 //0x04-0x05 should cause an illegal instruction exception
601 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
602 //0x07-0x0E should cause an illegal instruction exception
603 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
604 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
605 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
606 //0x12 should cause an illegal instruction exception
607 0x13: NoPriv::wrgsr({{
608 if(Fprs<2:> == 0 || Pstate<4:> == 0)
609 return new FpDisabled;
610 Gsr = Rs1 ^ Rs2_or_imm13;
611 }});
612 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
613 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});
614 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
615 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}});
616 0x18: NoPriv::wrstick({{
617 if(!Hpstate<2:>)
618 return new IllegalInstruction;
619 Stick = Rs1 ^ Rs2_or_imm13;
620 }});
621 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}});
622 0x1A: Priv::wrstrand_sts_reg({{
623 StrandStsReg = Rs1 ^ Rs2_or_imm13;
624 }});
625 //0x1A is supposed to be reserved, but it writes the strand
626 //status register.
627 //0x1B-0x1F should cause an illegal instruction exception
628 }
629 0x31: decode FCN {
630 0x0: Priv::saved({{
631 assert(Cansave < NWindows - 2);
632 assert(Otherwin || Canrestore);
633 Cansave = Cansave + 1;
634 if(Otherwin == 0)
635 Canrestore = Canrestore - 1;
636 else
637 Otherwin = Otherwin - 1;
638 }});
639 0x1: Priv::restored({{
640 assert(Cansave || Otherwin);
641 assert(Canrestore < NWindows - 2);
642 Canrestore = Canrestore + 1;
643 if(Otherwin == 0)
644 Cansave = Cansave - 1;
645 else
646 Otherwin = Otherwin - 1;
647
648 if(Cleanwin < NWindows - 1)
649 Cleanwin = Cleanwin + 1;
650 }});
651 }
652 0x32: decode RD {
653 0x00: Priv::wrprtpc({{
654 if(Tl == 0)
655 return new IllegalInstruction;
656 else
657 Tpc = Rs1 ^ Rs2_or_imm13;
658 }});
659 0x01: Priv::wrprtnpc({{
660 if(Tl == 0)
661 return new IllegalInstruction;
662 else
663 Tnpc = Rs1 ^ Rs2_or_imm13;
664 }});
665 0x02: Priv::wrprtstate({{
666 if(Tl == 0)
667 return new IllegalInstruction;
668 else
669 Tstate = Rs1 ^ Rs2_or_imm13;
670 }});
671 0x03: Priv::wrprtt({{
672 if(Tl == 0)
673 return new IllegalInstruction;
674 else
675 Tt = Rs1 ^ Rs2_or_imm13;
676 }});
677 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
678 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
679 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
680 0x07: Priv::wrprtl({{
681 if(Pstate<2:> && !Hpstate<2:>)
682 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
683 else
684 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);
685 }});
686 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
687 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
688 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
689 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
690 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
691 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
692 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
693 //0x0F should cause an illegal instruction exception
694 0x10: Priv::wrprgl({{
695 if(Pstate<2:> && !Hpstate<2:>)
696 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL);
697 else
698 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
699 }});
700 //0x11-0x1F should cause an illegal instruction exception
701 }
702 0x33: decode RD {
703 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
704 0x01: HPriv::wrhprhtstate({{
705 if(Tl == 0)
706 return new IllegalInstruction;
707 Htstate = Rs1 ^ Rs2_or_imm13;
708 }});
709 //0x02 should cause an illegal instruction exception
710 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
711 //0x04 should cause an illegal instruction exception
712 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
713 //0x06-0x01D should cause an illegal instruction exception
714 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
715 }
716 0x34: decode OPF{
717 format FpBasic{
718 0x01: fmovs({{
719 Frds.uw = Frs2s.uw;
720 //fsr.ftt = fsr.cexc = 0
721 Fsr &= ~(7 << 14);
722 Fsr &= ~(0x1F);
723 }});
724 0x02: fmovd({{
725 Frd.udw = Frs2.udw;
726 //fsr.ftt = fsr.cexc = 0
727 Fsr &= ~(7 << 14);
728 Fsr &= ~(0x1F);
729 }});
730 0x03: FpUnimpl::fmovq();
731 0x05: fnegs({{
732 Frds.uw = Frs2s.uw ^ (1UL << 31);
733 //fsr.ftt = fsr.cexc = 0
734 Fsr &= ~(7 << 14);
735 Fsr &= ~(0x1F);
736 }});
737 0x06: fnegd({{
738 Frd.udw = Frs2.udw ^ (1ULL << 63);
739 //fsr.ftt = fsr.cexc = 0
740 Fsr &= ~(7 << 14);
741 Fsr &= ~(0x1F);
742 }});
743 0x07: FpUnimpl::fnegq();
744 0x09: fabss({{
745 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;
746 //fsr.ftt = fsr.cexc = 0
747 Fsr &= ~(7 << 14);
748 Fsr &= ~(0x1F);
749 }});
750 0x0A: fabsd({{
751 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;
752 //fsr.ftt = fsr.cexc = 0
753 Fsr &= ~(7 << 14);
754 Fsr &= ~(0x1F);
755 }});
756 0x0B: FpUnimpl::fabsq();
757 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}});
758 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}});
759 0x2B: FpUnimpl::fsqrtq();
760 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
761 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
762 0x43: FpUnimpl::faddq();
763 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
764 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df; }});
765 0x47: FpUnimpl::fsubq();
766 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
767 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
768 0x4B: FpUnimpl::fmulq();
769 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
770 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
771 0x4F: FpUnimpl::fdivq();
772 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
773 0x6E: FpUnimpl::fdmulq();
774 0x81: fstox({{
775 Frd.sdw = static_cast<int64_t>(Frs2s.sf);
776 }});
777 0x82: fdtox({{
778 Frd.sdw = static_cast<int64_t>(Frs2.df);
779 }});
780 0x83: FpUnimpl::fqtox();
781 0x84: fxtos({{
782 Frds.sf = static_cast<float>(Frs2.sdw);
783 }});
784 0x88: fxtod({{
785 Frd.df = static_cast<double>(Frs2.sdw);
786 }});
787 0x8C: FpUnimpl::fxtoq();
788 0xC4: fitos({{
789 Frds.sf = static_cast<float>(Frs2s.sw);
790 }});
791 0xC6: fdtos({{Frds.sf = Frs2.df;}});
792 0xC7: FpUnimpl::fqtos();
793 0xC8: fitod({{
794 Frd.df = static_cast<double>(Frs2s.sw);
795 }});
796 0xC9: fstod({{Frd.df = Frs2s.sf;}});
797 0xCB: FpUnimpl::fqtod();
798 0xCC: FpUnimpl::fitoq();
799 0xCD: FpUnimpl::fstoq();
800 0xCE: FpUnimpl::fdtoq();
801 0xD1: fstoi({{
802 Frds.sw = static_cast<int32_t>(Frs2s.sf);
803 float t = Frds.sw;
804 if (t != Frs2s.sf)
805 Fsr = insertBits(Fsr, 4,0, 0x01);
806 }});
807 0xD2: fdtoi({{
808 Frds.sw = static_cast<int32_t>(Frs2.df);
809 double t = Frds.sw;
810 if (t != Frs2.df)
811 Fsr = insertBits(Fsr, 4,0, 0x01);
812 }});
813 0xD3: FpUnimpl::fqtoi();
814 default: FailUnimpl::fpop1();
815 }
816 }
817 0x35: decode OPF{
818 format FpBasic{
819 0x01: fmovs_fcc0({{
820 if(passesFpCondition(Fsr<11:10>, COND4))
821 Frds = Frs2s;
822 else
823 Frds = Frds;
824 }});
825 0x02: fmovd_fcc0({{
826 if(passesFpCondition(Fsr<11:10>, COND4))
827 Frd = Frs2;
828 else
829 Frd = Frd;
830 }});
831 0x03: FpUnimpl::fmovq_fcc0();
832 0x25: fmovrsz({{
833 if(Rs1 == 0)
834 Frds = Frs2s;
835 else
836 Frds = Frds;
837 }});
838 0x26: fmovrdz({{
839 if(Rs1 == 0)
840 Frd = Frs2;
841 else
842 Frd = Frd;
843 }});
844 0x27: FpUnimpl::fmovrqz();
845 0x41: fmovs_fcc1({{
846 if(passesFpCondition(Fsr<33:32>, COND4))
847 Frds = Frs2s;
848 else
849 Frds = Frds;
850 }});
851 0x42: fmovd_fcc1({{
852 if(passesFpCondition(Fsr<33:32>, COND4))
853 Frd = Frs2;
854 else
855 Frd = Frd;
856 }});
857 0x43: FpUnimpl::fmovq_fcc1();
858 0x45: fmovrslez({{
859 if(Rs1 <= 0)
860 Frds = Frs2s;
861 else
862 Frds = Frds;
863 }});
864 0x46: fmovrdlez({{
865 if(Rs1 <= 0)
866 Frd = Frs2;
867 else
868 Frd = Frd;
869 }});
870 0x47: FpUnimpl::fmovrqlez();
871 0x51: fcmps({{
872 uint8_t fcc;
873 if(isnan(Frs1s) || isnan(Frs2s))
874 fcc = 3;
875 else if(Frs1s < Frs2s)
876 fcc = 1;
877 else if(Frs1s > Frs2s)
878 fcc = 2;
879 else
880 fcc = 0;
881 uint8_t firstbit = 10;
882 if(FCMPCC)
883 firstbit = FCMPCC * 2 + 30;
884 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
885 }});
886 0x52: fcmpd({{
887 uint8_t fcc;
888 if(isnan(Frs1) || isnan(Frs2))
889 fcc = 3;
890 else if(Frs1 < Frs2)
891 fcc = 1;
892 else if(Frs1 > Frs2)
893 fcc = 2;
894 else
895 fcc = 0;
896 uint8_t firstbit = 10;
897 if(FCMPCC)
898 firstbit = FCMPCC * 2 + 30;
899 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
900 }});
901 0x53: FpUnimpl::fcmpq();
902 0x55: fcmpes({{
903 uint8_t fcc = 0;
904 if(isnan(Frs1s) || isnan(Frs2s))
905 fault = new FpExceptionIEEE754;
906 if(Frs1s < Frs2s)
907 fcc = 1;
908 else if(Frs1s > Frs2s)
909 fcc = 2;
910 uint8_t firstbit = 10;
911 if(FCMPCC)
912 firstbit = FCMPCC * 2 + 30;
913 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
914 }});
915 0x56: fcmped({{
916 uint8_t fcc = 0;
917 if(isnan(Frs1) || isnan(Frs2))
918 fault = new FpExceptionIEEE754;
919 if(Frs1 < Frs2)
920 fcc = 1;
921 else if(Frs1 > Frs2)
922 fcc = 2;
923 uint8_t firstbit = 10;
924 if(FCMPCC)
925 firstbit = FCMPCC * 2 + 30;
926 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
927 }});
928 0x57: FpUnimpl::fcmpeq();
929 0x65: fmovrslz({{
930 if(Rs1 < 0)
931 Frds = Frs2s;
932 else
933 Frds = Frds;
934 }});
935 0x66: fmovrdlz({{
936 if(Rs1 < 0)
937 Frd = Frs2;
938 else
939 Frd = Frd;
940 }});
941 0x67: FpUnimpl::fmovrqlz();
942 0x81: fmovs_fcc2({{
943 if(passesFpCondition(Fsr<35:34>, COND4))
944 Frds = Frs2s;
945 else
946 Frds = Frds;
947 }});
948 0x82: fmovd_fcc2({{
949 if(passesFpCondition(Fsr<35:34>, COND4))
950 Frd = Frs2;
951 else
952 Frd = Frd;
953 }});
954 0x83: FpUnimpl::fmovq_fcc2();
955 0xA5: fmovrsnz({{
956 if(Rs1 != 0)
957 Frds = Frs2s;
958 else
959 Frds = Frds;
960 }});
961 0xA6: fmovrdnz({{
962 if(Rs1 != 0)
963 Frd = Frs2;
964 else
965 Frd = Frd;
966 }});
967 0xA7: FpUnimpl::fmovrqnz();
968 0xC1: fmovs_fcc3({{
969 if(passesFpCondition(Fsr<37:36>, COND4))
970 Frds = Frs2s;
971 else
972 Frds = Frds;
973 }});
974 0xC2: fmovd_fcc3({{
975 if(passesFpCondition(Fsr<37:36>, COND4))
976 Frd = Frs2;
977 else
978 Frd = Frd;
979 }});
980 0xC3: FpUnimpl::fmovq_fcc3();
981 0xC5: fmovrsgz({{
982 if(Rs1 > 0)
983 Frds = Frs2s;
984 else
985 Frds = Frds;
986 }});
987 0xC6: fmovrdgz({{
988 if(Rs1 > 0)
989 Frd = Frs2;
990 else
991 Frd = Frd;
992 }});
993 0xC7: FpUnimpl::fmovrqgz();
994 0xE5: fmovrsgez({{
995 if(Rs1 >= 0)
996 Frds = Frs2s;
997 else
998 Frds = Frds;
999 }});
1000 0xE6: fmovrdgez({{
1001 if(Rs1 >= 0)
1002 Frd = Frs2;
1003 else
1004 Frd = Frd;
1005 }});
1006 0xE7: FpUnimpl::fmovrqgez();
1007 0x101: fmovs_icc({{
1008 if(passesCondition(Ccr<3:0>, COND4))
1009 Frds = Frs2s;
1010 else
1011 Frds = Frds;
1012 }});
1013 0x102: fmovd_icc({{
1014 if(passesCondition(Ccr<3:0>, COND4))
1015 Frd = Frs2;
1016 else
1017 Frd = Frd;
1018 }});
1019 0x103: FpUnimpl::fmovq_icc();
1020 0x181: fmovs_xcc({{
1021 if(passesCondition(Ccr<7:4>, COND4))
1022 Frds = Frs2s;
1023 else
1024 Frds = Frds;
1025 }});
1026 0x182: fmovd_xcc({{
1027 if(passesCondition(Ccr<7:4>, COND4))
1028 Frd = Frs2;
1029 else
1030 Frd = Frd;
1031 }});
1032 0x183: FpUnimpl::fmovq_xcc();
1033 default: FailUnimpl::fpop2();
1034 }
1035 }
1036 //This used to be just impdep1, but now it's a whole bunch
1037 //of instructions
1038 0x36: decode OPF{
1039 0x00: FailUnimpl::edge8();
1040 0x01: FailUnimpl::edge8n();
1041 0x02: FailUnimpl::edge8l();
1042 0x03: FailUnimpl::edge8ln();
1043 0x04: FailUnimpl::edge16();
1044 0x05: FailUnimpl::edge16n();
1045 0x06: FailUnimpl::edge16l();
1046 0x07: FailUnimpl::edge16ln();
1047 0x08: FailUnimpl::edge32();
1048 0x09: FailUnimpl::edge32n();
1049 0x0A: FailUnimpl::edge32l();
1050 0x0B: FailUnimpl::edge32ln();
1051 0x10: FailUnimpl::array8();
1052 0x12: FailUnimpl::array16();
1053 0x14: FailUnimpl::array32();
1054 0x18: BasicOperate::alignaddr({{
1055 uint64_t sum = Rs1 + Rs2;
1056 Rd = sum & ~7;
1057 Gsr = (Gsr & ~7) | (sum & 7);
1058 }});
1059 0x19: FailUnimpl::bmask();
1060 0x1A: BasicOperate::alignaddresslittle({{
1061 uint64_t sum = Rs1 + Rs2;
1062 Rd = sum & ~7;
1063 Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
1064 }});
1065 0x20: FailUnimpl::fcmple16();
1066 0x22: FailUnimpl::fcmpne16();
1067 0x24: FailUnimpl::fcmple32();
1068 0x26: FailUnimpl::fcmpne32();
1069 0x28: FailUnimpl::fcmpgt16();
1070 0x2A: FailUnimpl::fcmpeq16();
1071 0x2C: FailUnimpl::fcmpgt32();
1072 0x2E: FailUnimpl::fcmpeq32();
1073 0x31: FailUnimpl::fmul8x16();
1074 0x33: FailUnimpl::fmul8x16au();
1075 0x35: FailUnimpl::fmul8x16al();
1076 0x36: FailUnimpl::fmul8sux16();
1077 0x37: FailUnimpl::fmul8ulx16();
1078 0x38: FailUnimpl::fmuld8sux16();
1079 0x39: FailUnimpl::fmuld8ulx16();
1080 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
1081 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
1082 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
1083 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
1084 0x48: BasicOperate::faligndata({{
1085 uint64_t msbX = Frs1.udw;
1086 uint64_t lsbX = Frs2.udw;
1087 //Some special cases need to be split out, first
1088 //because they're the most likely to be used, and
1089 //second because otherwise, we end up shifting by
1090 //greater than the width of the type being shifted,
1091 //namely 64, which produces undefined results according
1092 //to the C standard.
1093 switch(Gsr<2:0>)
1094 {
1095 case 0:
1096 Frd.udw = msbX;
1097 break;
1098 case 8:
1099 Frd.udw = lsbX;
1100 break;
1101 default:
1102 uint64_t msbShift = Gsr<2:0> * 8;
1103 uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
1104 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
1105 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
1106 Frd.udw = ((msbX & msbMask) << msbShift) |
1107 ((lsbX & lsbMask) >> lsbShift);
1108 }
1109 }});
1110 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
1111 0x4C: FailUnimpl::bshuffle();
1112 0x4D: FailUnimpl::fexpand();
1113 0x50: FailUnimpl::fpadd16();
1114 0x51: FailUnimpl::fpadd16s();
1115 0x52: FailUnimpl::fpadd32();
1116 0x53: FailUnimpl::fpadd32s();
1117 0x54: FailUnimpl::fpsub16();
1118 0x55: FailUnimpl::fpsub16s();
1119 0x56: FailUnimpl::fpsub32();
1120 0x57: FailUnimpl::fpsub32s();
1121 0x60: FpBasic::fzero({{Frd.df = 0;}});
1122 0x61: FpBasic::fzeros({{Frds.sf = 0;}});
1123 0x62: FailUnimpl::fnor();
1124 0x63: FailUnimpl::fnors();
1125 0x64: FailUnimpl::fandnot2();
1126 0x65: FailUnimpl::fandnot2s();
1127 0x66: FpBasic::fnot2({{
1128 Frd.df = (double)(~((uint64_t)Frs2.df));
1129 }});
1130 0x67: FpBasic::fnot2s({{
1131 Frds.sf = (float)(~((uint32_t)Frs2s.sf));
1132 }});
1133 0x68: FailUnimpl::fandnot1();
1134 0x69: FailUnimpl::fandnot1s();
1135 0x6A: FpBasic::fnot1({{
1136 Frd.df = (double)(~((uint64_t)Frs1.df));
1137 }});
1138 0x6B: FpBasic::fnot1s({{
1139 Frds.sf = (float)(~((uint32_t)Frs1s.sf));
1140 }});
1141 0x6C: FailUnimpl::fxor();
1142 0x6D: FailUnimpl::fxors();
1143 0x6E: FailUnimpl::fnand();
1144 0x6F: FailUnimpl::fnands();
1145 0x70: FailUnimpl::fand();
1146 0x71: FailUnimpl::fands();
1147 0x72: FailUnimpl::fxnor();
1148 0x73: FailUnimpl::fxnors();
1149 0x74: FpBasic::fsrc1({{Frd.udw = Frs1.udw;}});
1150 0x75: FpBasic::fsrc1s({{Frds.uw = Frs1s.uw;}});
1151 0x76: FailUnimpl::fornot2();
1152 0x77: FailUnimpl::fornot2s();
1153 0x78: FpBasic::fsrc2({{Frd.udw = Frs2.udw;}});
1154 0x79: FpBasic::fsrc2s({{Frds.uw = Frs2s.uw;}});
1155 0x7A: FailUnimpl::fornot1();
1156 0x7B: FailUnimpl::fornot1s();
1157 0x7C: FailUnimpl::for();
1158 0x7D: FailUnimpl::fors();
1159 0x7E: FpBasic::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}});
1160 0x7F: FpBasic::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}});
1161 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
1162 0x81: FailUnimpl::siam();
1163 }
1164 // M5 special opcodes use the reserved IMPDEP2A opcode space
1165 0x37: decode M5FUNC {
1166#if FULL_SYSTEM
1167 format BasicOperate {
1168 // we have 7 bits of space here to play with...
1169 0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0);
1170 }}, No_OpClass, IsNonSpeculative);
1171 0x50: m5readfile({{
1172 O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2);
1173 }}, IsNonSpeculative);
1174 0x51: m5break({{PseudoInst::debugbreak(xc->tcBase());
1175 }}, IsNonSpeculative);
1176 0x54: m5panic({{
1177 panic("M5 panic instruction called at pc=%#x.", xc->readPC());
1178 }}, No_OpClass, IsNonSpeculative);
1179 }
1180#endif
1181 default: Trap::impdep2({{fault = new IllegalInstruction;}});
1182 }
1183 0x38: Branch::jmpl({{
1184 Addr target = Rs1 + Rs2_or_imm13;
1185 if(target & 0x3)
1186 fault = new MemAddressNotAligned;
1187 else
1188 {
1189 if (Pstate<3:>)
1190 Rd = (xc->readPC())<31:0>;
1191 else
1192 Rd = xc->readPC();
1193 NNPC = target;
1194 }
1195 }});
1196 0x39: Branch::return({{
1197 Addr target = Rs1 + Rs2_or_imm13;
1198 if(fault == NoFault)
1199 {
1200 //Check for fills which are higher priority than alignment
1201 //faults.
1202 if(Canrestore == 0)
1203 {
1204 if(Otherwin)
1205 fault = new FillNOther(4*Wstate<5:3>);
1206 else
1207 fault = new FillNNormal(4*Wstate<2:0>);
1208 }
1209 //Check for alignment faults
1210 else if(target & 0x3)
1211 fault = new MemAddressNotAligned;
1212 else
1213 {
1214 NNPC = target;
1215 Cwp = (Cwp - 1 + NWindows) % NWindows;
1216 Cansave = Cansave + 1;
1217 Canrestore = Canrestore - 1;
1218 }
1219 }
1220 }});
1221 0x3A: decode CC
1222 {
1223 0x0: Trap::tcci({{
1224 if(passesCondition(Ccr<3:0>, COND2))
1225 {
1226 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
1227 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
1228 fault = new TrapInstruction(lTrapNum);
1229 }
1230 }}, IsSerializeAfter, IsNonSpeculative);
1231 0x2: Trap::tccx({{
1232 if(passesCondition(Ccr<7:4>, COND2))
1233 {
1234 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
1235 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
1236 fault = new TrapInstruction(lTrapNum);
1237 }
1238 }}, IsSerializeAfter, IsNonSpeculative);
1239 }
1240 0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier,
1241 MemWriteOp);
1242 0x3C: save({{
1243 if(Cansave == 0)
1244 {
1245 if(Otherwin)
1246 fault = new SpillNOther(4*Wstate<5:3>);
1247 else
1248 fault = new SpillNNormal(4*Wstate<2:0>);
1249 }
1250 else if(Cleanwin - Canrestore == 0)
1251 {
1252 fault = new CleanWindow;
1253 }
1254 else
1255 {
1256 Cwp = (Cwp + 1) % NWindows;
1257 Rd_next = Rs1 + Rs2_or_imm13;
1258 Cansave = Cansave - 1;
1259 Canrestore = Canrestore + 1;
1260 }
1261 }});
1262 0x3D: restore({{
1263 if(Canrestore == 0)
1264 {
1265 if(Otherwin)
1266 fault = new FillNOther(4*Wstate<5:3>);
1267 else
1268 fault = new FillNNormal(4*Wstate<2:0>);
1269 }
1270 else
1271 {
1272 Cwp = (Cwp - 1 + NWindows) % NWindows;
1273 Rd_prev = Rs1 + Rs2_or_imm13;
1274 Cansave = Cansave + 1;
1275 Canrestore = Canrestore - 1;
1276 }
1277 }});
1278 0x3E: decode FCN {
1279 0x0: Priv::done({{
1280 if(Tl == 0)
1281 return new IllegalInstruction;
1282
1283 Cwp = Tstate<4:0>;
1284 Pstate = Tstate<20:8>;
1285 Asi = Tstate<31:24>;
1286 Ccr = Tstate<39:32>;
1287 Gl = Tstate<42:40>;
1288 Hpstate = Htstate;
1289 NPC = Tnpc;
1290 NNPC = Tnpc + 4;
1291 Tl = Tl - 1;
1292 }});
1293 0x1: Priv::retry({{
1294 if(Tl == 0)
1295 return new IllegalInstruction;
1296 Cwp = Tstate<4:0>;
1297 Pstate = Tstate<20:8>;
1298 Asi = Tstate<31:24>;
1299 Ccr = Tstate<39:32>;
1300 Gl = Tstate<42:40>;
1301 Hpstate = Htstate;
1302 NPC = Tpc;
1303 NNPC = Tnpc;
1304 Tl = Tl - 1;
1305 }});
1306 }
1307 }
1308 }
1309 0x3: decode OP3 {
1310 format Load {
1311 0x00: lduw({{Rd = Mem.uw;}});
1312 0x01: ldub({{Rd = Mem.ub;}});
1313 0x02: lduh({{Rd = Mem.uhw;}});
1314 0x03: ldtw({{
1315 RdLow = (Mem.tuw).a;
1316 RdHigh = (Mem.tuw).b;
1317 }});
1318 }
1319 format Store {
1320 0x04: stw({{Mem.uw = Rd.sw;}});
1321 0x05: stb({{Mem.ub = Rd.sb;}});
1322 0x06: sth({{Mem.uhw = Rd.shw;}});
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