1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OP default Unknown::unknown()
37{
38 0x0: decode OP2
39 {
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 //bpcc
45 0x1: decode COND2
46 {
47 //Branch Always
48 0x8: decode A
49 {
50 0x0: bpa(19, {{
51 NNPC = xc->readPC() + disp;
52 }});
53 0x1: bpa(19, {{
54 NPC = xc->readPC() + disp;
55 NNPC = NPC + 4;
56 }}, ',a');
57 }
58 //Branch Never
59 0x0: decode A
60 {
61 0x0: bpn(19, {{
62 NNPC = NNPC;//Don't do anything
63 }});
64 0x1: bpn(19, {{
65 NNPC = NPC + 8;
66 NPC = NPC + 4;
67 }}, ',a');
68 }
69 default: decode BPCC
70 {
71 0x0: bpcci(19, {{
72 if(passesCondition(Ccr<3:0>, COND2))
73 NNPC = xc->readPC() + disp;
74 else
75 handle_annul
76 }});
77 0x2: bpccx(19, {{
78 if(passesCondition(Ccr<7:4>, COND2))
79 NNPC = xc->readPC() + disp;
80 else
81 handle_annul
82 }});
83 }
84 }
85 //bicc
86 0x2: decode COND2
87 {
88 //Branch Always
89 0x8: decode A
90 {
91 0x0: ba(22, {{
92 NNPC = xc->readPC() + disp;
93 }});
94 0x1: ba(22, {{
95 NPC = xc->readPC() + disp;
96 NNPC = NPC + 4;
97 }}, ',a');
98 }
99 //Branch Never
100 0x0: decode A
101 {
102 0x0: bn(22, {{
103 NNPC = NNPC;//Don't do anything
104 }});
105 0x1: bn(22, {{
106 NNPC = NPC + 8;
107 NPC = NPC + 4;
108 }}, ',a');
109 }
110 default: bicc(22, {{
111 if(passesCondition(Ccr<3:0>, COND2))
112 NNPC = xc->readPC() + disp;
113 else
114 handle_annul
115 }});
116 }
117 }
118 0x3: decode RCOND2
119 {
120 format BranchSplit
121 {
122 0x1: bpreq({{
123 if(Rs1.sdw == 0)
124 NNPC = xc->readPC() + disp;
125 else
126 handle_annul
127 }});
128 0x2: bprle({{
129 if(Rs1.sdw <= 0)
130 NNPC = xc->readPC() + disp;
131 else
132 handle_annul
133 }});
134 0x3: bprl({{
135 if(Rs1.sdw < 0)
136 NNPC = xc->readPC() + disp;
137 else
138 handle_annul
139 }});
140 0x5: bprne({{
141 if(Rs1.sdw != 0)
142 NNPC = xc->readPC() + disp;
143 else
144 handle_annul
145 }});
146 0x6: bprg({{
147 if(Rs1.sdw > 0)
148 NNPC = xc->readPC() + disp;
149 else
150 handle_annul
151 }});
152 0x7: bprge({{
153 if(Rs1.sdw >= 0)
154 NNPC = xc->readPC() + disp;
155 else
156 handle_annul
157 }});
158 }
159 }
160 //SETHI (or NOP if rd == 0 and imm == 0)
161 0x4: SetHi::sethi({{Rd.udw = imm;}});
162 //fbpfcc
163 0x5: decode COND2 {
164 format BranchN {
165 //Branch Always
166 0x8: decode A
167 {
168 0x0: fbpa(22, {{
169 NNPC = xc->readPC() + disp;
170 }});
171 0x1: fbpa(22, {{
172 NPC = xc->readPC() + disp;
173 NNPC = NPC + 4;
174 }}, ',a');
175 }
176 //Branch Never
177 0x0: decode A
178 {
179 0x0: fbpn(22, {{
180 NNPC = NNPC;//Don't do anything
181 }});
182 0x1: fbpn(22, {{
183 NNPC = NPC + 8;
184 NPC = NPC + 4;
185 }}, ',a');
186 }
187 default: decode BPCC {
188 0x0: fbpcc0(22, {{
189 if(passesFpCondition(Fsr<11:10>, COND2))
190 NNPC = xc->readPC() + disp;
191 else
192 handle_annul
193 }});
194 0x1: fbpcc1(22, {{
195 if(passesFpCondition(Fsr<33:32>, COND2))
196 NNPC = xc->readPC() + disp;
197 else
198 handle_annul
199 }});
200 0x2: fbpcc2(22, {{
201 if(passesFpCondition(Fsr<35:34>, COND2))
202 NNPC = xc->readPC() + disp;
203 else
204 handle_annul
205 }});
206 0x3: fbpcc3(22, {{
207 if(passesFpCondition(Fsr<37:36>, COND2))
208 NNPC = xc->readPC() + disp;
209 else
210 handle_annul
211 }});
212 }
213 }
214 }
215 //fbfcc
216 0x6: decode COND2 {
217 format BranchN {
218 //Branch Always
219 0x8: decode A
220 {
221 0x0: fba(22, {{
222 NNPC = xc->readPC() + disp;
223 }});
224 0x1: fba(22, {{
225 NPC = xc->readPC() + disp;
226 NNPC = NPC + 4;
227 }}, ',a');
228 }
229 //Branch Never
230 0x0: decode A
231 {
232 0x0: fbn(22, {{
233 NNPC = NNPC;//Don't do anything
234 }});
235 0x1: fbn(22, {{
236 NNPC = NPC + 8;
237 NPC = NPC + 4;
238 }}, ',a');
239 }
240 default: fbfcc(22, {{
241 if(passesFpCondition(Fsr<11:10>, COND2))
242 NNPC = xc->readPC() + disp;
243 else
244 handle_annul
245 }});
246 }
247 }
248 }
249 0x1: BranchN::call(30, {{
250 if (Pstate<3:>)
251 R15 = (xc->readPC())<31:0>;
252 else
253 R15 = xc->readPC();
254 NNPC = R15 + disp;
255 }});
256 0x2: decode OP3 {
257 format IntOp {
258 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
259 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
260 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
261 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
262 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
263 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}});
264 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}});
265 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
266 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
267 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
268 0x0A: umul({{
269 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
270 Y = Rd<63:32>;
271 }});
272 0x0B: smul({{
273 Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
274 Y = Rd.sdw<63:32>;
275 }});
276 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
277 0x0D: udivx({{
278 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
279 else Rd.udw = Rs1.udw / Rs2_or_imm13;
280 }});
281 0x0E: udiv({{
282 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
283 else
284 {
285 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
286 if(Rd.udw >> 32 != 0)
287 Rd.udw = 0xFFFFFFFF;
288 }
289 }});
290 0x0F: sdiv({{
291 if(Rs2_or_imm13.sdw == 0)
292 fault = new DivisionByZero;
293 else
294 {
295 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
296 if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max())
297 Rd.udw = 0x7FFFFFFF;
298 else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min())
299 Rd.udw = ULL(0xFFFFFFFF80000000);
300 }
301 }});
302 }
303 format IntOpCc {
304 0x10: addcc({{
305 int64_t resTemp, val2 = Rs2_or_imm13;
306 Rd = resTemp = Rs1 + val2;}},
307 {{(Rs1<31:0> + val2<31:0>)<32:>}},
308 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
309 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
310 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
311 );
312 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
313 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
314 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
315 0x14: subcc({{
316 int64_t val2 = Rs2_or_imm13;
317 Rd = Rs1 - val2;}},
318 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
319 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
320 {{(~(Rs1<63:1> + (~val2)<63:1> +
321 (Rs1 | ~val2)<0:>))<63:>}},
322 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
323 );
324 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
325 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
326 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
327 0x18: addccc({{
328 int64_t resTemp, val2 = Rs2_or_imm13;
329 int64_t carryin = Ccr<0:0>;
330 Rd = resTemp = Rs1 + val2 + carryin;}},
331 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
332 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
333 {{((Rs1 & val2) | (~resTemp & (Rs1 | val2)))<63:>}},
334 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
335 );
336 0x1A: IntOpCcRes::umulcc({{
337 uint64_t resTemp;
338 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
339 Y = resTemp<63:32>;}});
340 0x1B: IntOpCcRes::smulcc({{
341 int64_t resTemp;
342 Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
343 Y = resTemp<63:32>;}});
344 0x1C: subccc({{
345 int64_t resTemp, val2 = Rs2_or_imm13;
346 int64_t carryin = Ccr<0:0>;
347 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
348 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<31:>}},
349 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
350 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<63:>}},
351 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
352 );
353 0x1D: IntOpCcRes::udivxcc({{
354 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
355 else Rd = Rs1.udw / Rs2_or_imm13.udw;}});
356 0x1E: udivcc({{
357 uint32_t resTemp, val2 = Rs2_or_imm13.udw;
358 int32_t overflow = 0;
359 if(val2 == 0) fault = new DivisionByZero;
360 else
361 {
362 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
363 overflow = (resTemp<63:32> != 0);
364 if(overflow) Rd = resTemp = 0xFFFFFFFF;
365 else Rd = resTemp;
366 } }},
367 {{0}},
368 {{overflow}},
369 {{0}},
370 {{0}}
371 );
372 0x1F: sdivcc({{
373 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
374 bool overflow = false, underflow = false;
375 if(val2 == 0) fault = new DivisionByZero;
376 else
377 {
378 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
379 overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max());
380 underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min());
381 if(overflow) Rd = 0x7FFFFFFF;
382 else if(underflow) Rd = ULL(0xFFFFFFFF80000000);
383 } }},
384 {{0}},
385 {{overflow || underflow}},
386 {{0}},
387 {{0}}
388 );
389 0x20: taddcc({{
390 int64_t resTemp, val2 = Rs2_or_imm13;
391 Rd = resTemp = Rs1 + val2;
392 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
393 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
394 {{overflow}},
395 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
396 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
397 );
398 0x21: tsubcc({{
399 int64_t resTemp, val2 = Rs2_or_imm13;
400 Rd = resTemp = Rs1 + val2;
401 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
402 {{(Rs1<31:0> + val2<31:0>)<32:0>}},
403 {{overflow}},
404 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
405 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
406 );
407 0x22: taddcctv({{
408 int64_t val2 = Rs2_or_imm13;
409 Rd = Rs1 + val2;
410 int32_t overflow = Rs1<1:0> || val2<1:0> ||
411 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
412 if(overflow) fault = new TagOverflow;}},
413 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
414 {{overflow}},
415 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
416 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}}
417 );
418 0x23: tsubcctv({{
419 int64_t resTemp, val2 = Rs2_or_imm13;
420 Rd = resTemp = Rs1 + val2;
421 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
422 if(overflow) fault = new TagOverflow;}},
423 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
424 {{overflow}},
425 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
426 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
427 );
428 0x24: mulscc({{
429 int64_t resTemp, multiplicand = Rs2_or_imm13;
430 int32_t multiplier = Rs1<31:0>;
431 int32_t savedLSB = Rs1<0:>;
432 multiplier = multiplier<31:1> |
433 ((Ccr<3:3> ^ Ccr<1:1>) << 32);
434 if(!Y<0:>)
435 multiplicand = 0;
436 Rd = resTemp = multiplicand + multiplier;
437 Y = Y<31:1> | (savedLSB << 31);}},
438 {{((multiplicand<31:0> + multiplier<31:0>)<32:0>)}},
439 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
440 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
441 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
442 );
443 }
444 format IntOp
445 {
446 0x25: decode X {
447 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
448 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
449 }
450 0x26: decode X {
451 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
452 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
453 }
454 0x27: decode X {
455 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
456 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
457 }
458 0x28: decode RS1 {
459 0x00: NoPriv::rdy({{Rd = Y<31:0>;}});
460 //1 should cause an illegal instruction exception
461 0x02: NoPriv::rdccr({{Rd = Ccr;}});
462 0x03: NoPriv::rdasi({{Rd = Asi;}});
463 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
464 0x05: NoPriv::rdpc({{
465 if(Pstate<3:>)
466 Rd = (xc->readPC())<31:0>;
467 else
468 Rd = xc->readPC();}});
469 0x06: NoPriv::rdfprs({{
470 //Wait for all fpops to finish.
471 Rd = Fprs;
472 }});
473 //7-14 should cause an illegal instruction exception
474 0x0F: decode I {
| 1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OP default Unknown::unknown()
37{
38 0x0: decode OP2
39 {
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 //bpcc
45 0x1: decode COND2
46 {
47 //Branch Always
48 0x8: decode A
49 {
50 0x0: bpa(19, {{
51 NNPC = xc->readPC() + disp;
52 }});
53 0x1: bpa(19, {{
54 NPC = xc->readPC() + disp;
55 NNPC = NPC + 4;
56 }}, ',a');
57 }
58 //Branch Never
59 0x0: decode A
60 {
61 0x0: bpn(19, {{
62 NNPC = NNPC;//Don't do anything
63 }});
64 0x1: bpn(19, {{
65 NNPC = NPC + 8;
66 NPC = NPC + 4;
67 }}, ',a');
68 }
69 default: decode BPCC
70 {
71 0x0: bpcci(19, {{
72 if(passesCondition(Ccr<3:0>, COND2))
73 NNPC = xc->readPC() + disp;
74 else
75 handle_annul
76 }});
77 0x2: bpccx(19, {{
78 if(passesCondition(Ccr<7:4>, COND2))
79 NNPC = xc->readPC() + disp;
80 else
81 handle_annul
82 }});
83 }
84 }
85 //bicc
86 0x2: decode COND2
87 {
88 //Branch Always
89 0x8: decode A
90 {
91 0x0: ba(22, {{
92 NNPC = xc->readPC() + disp;
93 }});
94 0x1: ba(22, {{
95 NPC = xc->readPC() + disp;
96 NNPC = NPC + 4;
97 }}, ',a');
98 }
99 //Branch Never
100 0x0: decode A
101 {
102 0x0: bn(22, {{
103 NNPC = NNPC;//Don't do anything
104 }});
105 0x1: bn(22, {{
106 NNPC = NPC + 8;
107 NPC = NPC + 4;
108 }}, ',a');
109 }
110 default: bicc(22, {{
111 if(passesCondition(Ccr<3:0>, COND2))
112 NNPC = xc->readPC() + disp;
113 else
114 handle_annul
115 }});
116 }
117 }
118 0x3: decode RCOND2
119 {
120 format BranchSplit
121 {
122 0x1: bpreq({{
123 if(Rs1.sdw == 0)
124 NNPC = xc->readPC() + disp;
125 else
126 handle_annul
127 }});
128 0x2: bprle({{
129 if(Rs1.sdw <= 0)
130 NNPC = xc->readPC() + disp;
131 else
132 handle_annul
133 }});
134 0x3: bprl({{
135 if(Rs1.sdw < 0)
136 NNPC = xc->readPC() + disp;
137 else
138 handle_annul
139 }});
140 0x5: bprne({{
141 if(Rs1.sdw != 0)
142 NNPC = xc->readPC() + disp;
143 else
144 handle_annul
145 }});
146 0x6: bprg({{
147 if(Rs1.sdw > 0)
148 NNPC = xc->readPC() + disp;
149 else
150 handle_annul
151 }});
152 0x7: bprge({{
153 if(Rs1.sdw >= 0)
154 NNPC = xc->readPC() + disp;
155 else
156 handle_annul
157 }});
158 }
159 }
160 //SETHI (or NOP if rd == 0 and imm == 0)
161 0x4: SetHi::sethi({{Rd.udw = imm;}});
162 //fbpfcc
163 0x5: decode COND2 {
164 format BranchN {
165 //Branch Always
166 0x8: decode A
167 {
168 0x0: fbpa(22, {{
169 NNPC = xc->readPC() + disp;
170 }});
171 0x1: fbpa(22, {{
172 NPC = xc->readPC() + disp;
173 NNPC = NPC + 4;
174 }}, ',a');
175 }
176 //Branch Never
177 0x0: decode A
178 {
179 0x0: fbpn(22, {{
180 NNPC = NNPC;//Don't do anything
181 }});
182 0x1: fbpn(22, {{
183 NNPC = NPC + 8;
184 NPC = NPC + 4;
185 }}, ',a');
186 }
187 default: decode BPCC {
188 0x0: fbpcc0(22, {{
189 if(passesFpCondition(Fsr<11:10>, COND2))
190 NNPC = xc->readPC() + disp;
191 else
192 handle_annul
193 }});
194 0x1: fbpcc1(22, {{
195 if(passesFpCondition(Fsr<33:32>, COND2))
196 NNPC = xc->readPC() + disp;
197 else
198 handle_annul
199 }});
200 0x2: fbpcc2(22, {{
201 if(passesFpCondition(Fsr<35:34>, COND2))
202 NNPC = xc->readPC() + disp;
203 else
204 handle_annul
205 }});
206 0x3: fbpcc3(22, {{
207 if(passesFpCondition(Fsr<37:36>, COND2))
208 NNPC = xc->readPC() + disp;
209 else
210 handle_annul
211 }});
212 }
213 }
214 }
215 //fbfcc
216 0x6: decode COND2 {
217 format BranchN {
218 //Branch Always
219 0x8: decode A
220 {
221 0x0: fba(22, {{
222 NNPC = xc->readPC() + disp;
223 }});
224 0x1: fba(22, {{
225 NPC = xc->readPC() + disp;
226 NNPC = NPC + 4;
227 }}, ',a');
228 }
229 //Branch Never
230 0x0: decode A
231 {
232 0x0: fbn(22, {{
233 NNPC = NNPC;//Don't do anything
234 }});
235 0x1: fbn(22, {{
236 NNPC = NPC + 8;
237 NPC = NPC + 4;
238 }}, ',a');
239 }
240 default: fbfcc(22, {{
241 if(passesFpCondition(Fsr<11:10>, COND2))
242 NNPC = xc->readPC() + disp;
243 else
244 handle_annul
245 }});
246 }
247 }
248 }
249 0x1: BranchN::call(30, {{
250 if (Pstate<3:>)
251 R15 = (xc->readPC())<31:0>;
252 else
253 R15 = xc->readPC();
254 NNPC = R15 + disp;
255 }});
256 0x2: decode OP3 {
257 format IntOp {
258 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
259 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
260 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
261 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
262 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
263 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}});
264 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}});
265 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
266 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
267 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
268 0x0A: umul({{
269 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
270 Y = Rd<63:32>;
271 }});
272 0x0B: smul({{
273 Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
274 Y = Rd.sdw<63:32>;
275 }});
276 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
277 0x0D: udivx({{
278 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
279 else Rd.udw = Rs1.udw / Rs2_or_imm13;
280 }});
281 0x0E: udiv({{
282 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
283 else
284 {
285 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
286 if(Rd.udw >> 32 != 0)
287 Rd.udw = 0xFFFFFFFF;
288 }
289 }});
290 0x0F: sdiv({{
291 if(Rs2_or_imm13.sdw == 0)
292 fault = new DivisionByZero;
293 else
294 {
295 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
296 if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max())
297 Rd.udw = 0x7FFFFFFF;
298 else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min())
299 Rd.udw = ULL(0xFFFFFFFF80000000);
300 }
301 }});
302 }
303 format IntOpCc {
304 0x10: addcc({{
305 int64_t resTemp, val2 = Rs2_or_imm13;
306 Rd = resTemp = Rs1 + val2;}},
307 {{(Rs1<31:0> + val2<31:0>)<32:>}},
308 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
309 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
310 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
311 );
312 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
313 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
314 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
315 0x14: subcc({{
316 int64_t val2 = Rs2_or_imm13;
317 Rd = Rs1 - val2;}},
318 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
319 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
320 {{(~(Rs1<63:1> + (~val2)<63:1> +
321 (Rs1 | ~val2)<0:>))<63:>}},
322 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
323 );
324 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
325 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
326 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
327 0x18: addccc({{
328 int64_t resTemp, val2 = Rs2_or_imm13;
329 int64_t carryin = Ccr<0:0>;
330 Rd = resTemp = Rs1 + val2 + carryin;}},
331 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
332 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
333 {{((Rs1 & val2) | (~resTemp & (Rs1 | val2)))<63:>}},
334 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
335 );
336 0x1A: IntOpCcRes::umulcc({{
337 uint64_t resTemp;
338 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
339 Y = resTemp<63:32>;}});
340 0x1B: IntOpCcRes::smulcc({{
341 int64_t resTemp;
342 Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
343 Y = resTemp<63:32>;}});
344 0x1C: subccc({{
345 int64_t resTemp, val2 = Rs2_or_imm13;
346 int64_t carryin = Ccr<0:0>;
347 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
348 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<31:>}},
349 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
350 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<63:>}},
351 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
352 );
353 0x1D: IntOpCcRes::udivxcc({{
354 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
355 else Rd = Rs1.udw / Rs2_or_imm13.udw;}});
356 0x1E: udivcc({{
357 uint32_t resTemp, val2 = Rs2_or_imm13.udw;
358 int32_t overflow = 0;
359 if(val2 == 0) fault = new DivisionByZero;
360 else
361 {
362 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
363 overflow = (resTemp<63:32> != 0);
364 if(overflow) Rd = resTemp = 0xFFFFFFFF;
365 else Rd = resTemp;
366 } }},
367 {{0}},
368 {{overflow}},
369 {{0}},
370 {{0}}
371 );
372 0x1F: sdivcc({{
373 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
374 bool overflow = false, underflow = false;
375 if(val2 == 0) fault = new DivisionByZero;
376 else
377 {
378 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
379 overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max());
380 underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min());
381 if(overflow) Rd = 0x7FFFFFFF;
382 else if(underflow) Rd = ULL(0xFFFFFFFF80000000);
383 } }},
384 {{0}},
385 {{overflow || underflow}},
386 {{0}},
387 {{0}}
388 );
389 0x20: taddcc({{
390 int64_t resTemp, val2 = Rs2_or_imm13;
391 Rd = resTemp = Rs1 + val2;
392 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
393 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
394 {{overflow}},
395 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
396 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
397 );
398 0x21: tsubcc({{
399 int64_t resTemp, val2 = Rs2_or_imm13;
400 Rd = resTemp = Rs1 + val2;
401 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
402 {{(Rs1<31:0> + val2<31:0>)<32:0>}},
403 {{overflow}},
404 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
405 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
406 );
407 0x22: taddcctv({{
408 int64_t val2 = Rs2_or_imm13;
409 Rd = Rs1 + val2;
410 int32_t overflow = Rs1<1:0> || val2<1:0> ||
411 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
412 if(overflow) fault = new TagOverflow;}},
413 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
414 {{overflow}},
415 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
416 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}}
417 );
418 0x23: tsubcctv({{
419 int64_t resTemp, val2 = Rs2_or_imm13;
420 Rd = resTemp = Rs1 + val2;
421 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
422 if(overflow) fault = new TagOverflow;}},
423 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
424 {{overflow}},
425 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
426 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
427 );
428 0x24: mulscc({{
429 int64_t resTemp, multiplicand = Rs2_or_imm13;
430 int32_t multiplier = Rs1<31:0>;
431 int32_t savedLSB = Rs1<0:>;
432 multiplier = multiplier<31:1> |
433 ((Ccr<3:3> ^ Ccr<1:1>) << 32);
434 if(!Y<0:>)
435 multiplicand = 0;
436 Rd = resTemp = multiplicand + multiplier;
437 Y = Y<31:1> | (savedLSB << 31);}},
438 {{((multiplicand<31:0> + multiplier<31:0>)<32:0>)}},
439 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
440 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
441 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
442 );
443 }
444 format IntOp
445 {
446 0x25: decode X {
447 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
448 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
449 }
450 0x26: decode X {
451 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
452 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
453 }
454 0x27: decode X {
455 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
456 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
457 }
458 0x28: decode RS1 {
459 0x00: NoPriv::rdy({{Rd = Y<31:0>;}});
460 //1 should cause an illegal instruction exception
461 0x02: NoPriv::rdccr({{Rd = Ccr;}});
462 0x03: NoPriv::rdasi({{Rd = Asi;}});
463 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
464 0x05: NoPriv::rdpc({{
465 if(Pstate<3:>)
466 Rd = (xc->readPC())<31:0>;
467 else
468 Rd = xc->readPC();}});
469 0x06: NoPriv::rdfprs({{
470 //Wait for all fpops to finish.
471 Rd = Fprs;
472 }});
473 //7-14 should cause an illegal instruction exception
474 0x0F: decode I {
|
475 0x0: Nop::stbar({{/*stuff*/}});
476 0x1: Nop::membar({{/*stuff*/}});
| 475 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp);
476 0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp);
|
477 }
478 0x10: Priv::rdpcr({{Rd = Pcr;}});
479 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
480 //0x12 should cause an illegal instruction exception
481 0x13: NoPriv::rdgsr({{
482 fault = checkFpEnableFault(xc);
483 if (fault)
484 return fault;
485 Rd = Gsr;
486 }});
487 //0x14-0x15 should cause an illegal instruction exception
488 0x16: Priv::rdsoftint({{Rd = Softint;}});
489 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
490 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}});
491 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
492 0x1A: Priv::rdstrand_sts_reg({{
493 if(Pstate<2:> && !Hpstate<2:>)
494 Rd = StrandStsReg<0:>;
495 else
496 Rd = StrandStsReg;
497 }});
498 //0x1A is supposed to be reserved, but it reads the strand
499 //status register.
500 //0x1B-0x1F should cause an illegal instruction exception
501 }
502 0x29: decode RS1 {
503 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
504 0x01: HPriv::rdhprhtstate({{
505 if(Tl == 0)
506 return new IllegalInstruction;
507 Rd = Htstate;
508 }});
509 //0x02 should cause an illegal instruction exception
510 0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
511 //0x04 should cause an illegal instruction exception
512 0x05: HPriv::rdhprhtba({{Rd = Htba;}});
513 0x06: HPriv::rdhprhver({{Rd = Hver;}});
514 //0x07-0x1E should cause an illegal instruction exception
515 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
516 }
517 0x2A: decode RS1 {
518 0x00: Priv::rdprtpc({{
519 if(Tl == 0)
520 return new IllegalInstruction;
521 Rd = Tpc;
522 }});
523 0x01: Priv::rdprtnpc({{
524 if(Tl == 0)
525 return new IllegalInstruction;
526 Rd = Tnpc;
527 }});
528 0x02: Priv::rdprtstate({{
529 if(Tl == 0)
530 return new IllegalInstruction;
531 Rd = Tstate;
532 }});
533 0x03: Priv::rdprtt({{
534 if(Tl == 0)
535 return new IllegalInstruction;
536 Rd = Tt;
537 }});
538 0x04: Priv::rdprtick({{Rd = Tick;}});
539 0x05: Priv::rdprtba({{Rd = Tba;}});
540 0x06: Priv::rdprpstate({{Rd = Pstate;}});
541 0x07: Priv::rdprtl({{Rd = Tl;}});
542 0x08: Priv::rdprpil({{Rd = Pil;}});
543 0x09: Priv::rdprcwp({{Rd = Cwp;}});
544 0x0A: Priv::rdprcansave({{Rd = Cansave;}});
545 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});
546 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});
547 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}});
548 0x0E: Priv::rdprwstate({{Rd = Wstate;}});
549 //0x0F should cause an illegal instruction exception
550 0x10: Priv::rdprgl({{Rd = Gl;}});
551 //0x11-0x1F should cause an illegal instruction exception
552 }
553 0x2B: BasicOperate::flushw({{
554 if(NWindows - 2 - Cansave != 0)
555 {
556 if(Otherwin)
557 fault = new SpillNOther(4*Wstate<5:3>);
558 else
559 fault = new SpillNNormal(4*Wstate<2:0>);
560 }
561 }});
562 0x2C: decode MOVCC3
563 {
564 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
565 0x1: decode CC
566 {
567 0x0: movcci({{
568 if(passesCondition(Ccr<3:0>, COND4))
569 Rd = Rs2_or_imm11;
570 else
571 Rd = Rd;
572 }});
573 0x2: movccx({{
574 if(passesCondition(Ccr<7:4>, COND4))
575 Rd = Rs2_or_imm11;
576 else
577 Rd = Rd;
578 }});
579 }
580 }
581 0x2D: sdivx({{
582 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
583 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
584 }});
585 0x2E: Trap::popc({{fault = new IllegalInstruction;}});
586 0x2F: decode RCOND3
587 {
588 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
589 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
590 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
591 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
592 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
593 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
594 }
595 0x30: decode RD {
596 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}});
597 //0x01 should cause an illegal instruction exception
598 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
599 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
600 //0x04-0x05 should cause an illegal instruction exception
601 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
602 //0x07-0x0E should cause an illegal instruction exception
603 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
604 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
605 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
606 //0x12 should cause an illegal instruction exception
607 0x13: NoPriv::wrgsr({{
608 if(Fprs<2:> == 0 || Pstate<4:> == 0)
609 return new FpDisabled;
610 Gsr = Rs1 ^ Rs2_or_imm13;
611 }});
612 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
613 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});
614 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
615 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}});
616 0x18: NoPriv::wrstick({{
617 if(!Hpstate<2:>)
618 return new IllegalInstruction;
619 Stick = Rs1 ^ Rs2_or_imm13;
620 }});
621 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}});
622 0x1A: Priv::wrstrand_sts_reg({{
623 if(Pstate<2:> && !Hpstate<2:>)
624 StrandStsReg = StrandStsReg<63:1> |
625 (Rs1 ^ Rs2_or_imm13)<0:>;
626 else
627 StrandStsReg = Rs1 ^ Rs2_or_imm13;
628 }});
629 //0x1A is supposed to be reserved, but it writes the strand
630 //status register.
631 //0x1B-0x1F should cause an illegal instruction exception
632 }
633 0x31: decode FCN {
634 0x0: Priv::saved({{
635 assert(Cansave < NWindows - 2);
636 assert(Otherwin || Canrestore);
637 Cansave = Cansave + 1;
638 if(Otherwin == 0)
639 Canrestore = Canrestore - 1;
640 else
641 Otherwin = Otherwin - 1;
642 }});
643 0x1: Priv::restored({{
644 assert(Cansave || Otherwin);
645 assert(Canrestore < NWindows - 2);
646 Canrestore = Canrestore + 1;
647 if(Otherwin == 0)
648 Cansave = Cansave - 1;
649 else
650 Otherwin = Otherwin - 1;
651
652 if(Cleanwin < NWindows - 1)
653 Cleanwin = Cleanwin + 1;
654 }});
655 }
656 0x32: decode RD {
657 0x00: Priv::wrprtpc({{
658 if(Tl == 0)
659 return new IllegalInstruction;
660 else
661 Tpc = Rs1 ^ Rs2_or_imm13;
662 }});
663 0x01: Priv::wrprtnpc({{
664 if(Tl == 0)
665 return new IllegalInstruction;
666 else
667 Tnpc = Rs1 ^ Rs2_or_imm13;
668 }});
669 0x02: Priv::wrprtstate({{
670 if(Tl == 0)
671 return new IllegalInstruction;
672 else
673 Tstate = Rs1 ^ Rs2_or_imm13;
674 }});
675 0x03: Priv::wrprtt({{
676 if(Tl == 0)
677 return new IllegalInstruction;
678 else
679 Tt = Rs1 ^ Rs2_or_imm13;
680 }});
681 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
682 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
683 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
684 0x07: Priv::wrprtl({{
685 if(Pstate<2:> && !Hpstate<2:>)
686 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
687 else
688 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);
689 }});
690 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
691 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
692 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
693 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
694 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
695 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
696 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
697 //0x0F should cause an illegal instruction exception
698 0x10: Priv::wrprgl({{
699 if(Pstate<2:> && !Hpstate<2:>)
700 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL);
701 else
702 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
703 }});
704 //0x11-0x1F should cause an illegal instruction exception
705 }
706 0x33: decode RD {
707 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
708 0x01: HPriv::wrhprhtstate({{
709 if(Tl == 0)
710 return new IllegalInstruction;
711 Htstate = Rs1 ^ Rs2_or_imm13;
712 }});
713 //0x02 should cause an illegal instruction exception
714 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
715 //0x04 should cause an illegal instruction exception
716 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
717 //0x06-0x01D should cause an illegal instruction exception
718 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
719 }
720 0x34: decode OPF{
721 format FpBasic{
722 0x01: fmovs({{
723 Frds.uw = Frs2s.uw;
724 //fsr.ftt = fsr.cexc = 0
725 Fsr &= ~(7 << 14);
726 Fsr &= ~(0x1F);
727 }});
728 0x02: fmovd({{
729 Frd.udw = Frs2.udw;
730 //fsr.ftt = fsr.cexc = 0
731 Fsr &= ~(7 << 14);
732 Fsr &= ~(0x1F);
733 }});
734 0x03: FpUnimpl::fmovq();
735 0x05: fnegs({{
736 Frds.uw = Frs2s.uw ^ (1UL << 31);
737 //fsr.ftt = fsr.cexc = 0
738 Fsr &= ~(7 << 14);
739 Fsr &= ~(0x1F);
740 }});
741 0x06: fnegd({{
742 Frd.udw = Frs2.udw ^ (1ULL << 63);
743 //fsr.ftt = fsr.cexc = 0
744 Fsr &= ~(7 << 14);
745 Fsr &= ~(0x1F);
746 }});
747 0x07: FpUnimpl::fnegq();
748 0x09: fabss({{
749 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;
750 //fsr.ftt = fsr.cexc = 0
751 Fsr &= ~(7 << 14);
752 Fsr &= ~(0x1F);
753 }});
754 0x0A: fabsd({{
755 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;
756 //fsr.ftt = fsr.cexc = 0
757 Fsr &= ~(7 << 14);
758 Fsr &= ~(0x1F);
759 }});
760 0x0B: FpUnimpl::fabsq();
761 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}});
762 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}});
763 0x2B: FpUnimpl::fsqrtq();
764 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
765 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
766 0x43: FpUnimpl::faddq();
767 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
768 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df; }});
769 0x47: FpUnimpl::fsubq();
770 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
771 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
772 0x4B: FpUnimpl::fmulq();
773 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
774 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
775 0x4F: FpUnimpl::fdivq();
776 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
777 0x6E: FpUnimpl::fdmulq();
778 0x81: fstox({{
779 Frd.sdw = static_cast<int64_t>(Frs2s.sf);
780 }});
781 0x82: fdtox({{
782 Frd.sdw = static_cast<int64_t>(Frs2.df);
783 }});
784 0x83: FpUnimpl::fqtox();
785 0x84: fxtos({{
786 Frds.sf = static_cast<float>(Frs2.sdw);
787 }});
788 0x88: fxtod({{
789 Frd.df = static_cast<double>(Frs2.sdw);
790 }});
791 0x8C: FpUnimpl::fxtoq();
792 0xC4: fitos({{
793 Frds.sf = static_cast<float>(Frs2s.sw);
794 }});
795 0xC6: fdtos({{Frds.sf = Frs2.df;}});
796 0xC7: FpUnimpl::fqtos();
797 0xC8: fitod({{
798 Frd.df = static_cast<double>(Frs2s.sw);
799 }});
800 0xC9: fstod({{Frd.df = Frs2s.sf;}});
801 0xCB: FpUnimpl::fqtod();
802 0xCC: FpUnimpl::fitoq();
803 0xCD: FpUnimpl::fstoq();
804 0xCE: FpUnimpl::fdtoq();
805 0xD1: fstoi({{
806 Frds.sw = static_cast<int32_t>(Frs2s.sf);
807 float t = Frds.sw;
808 if (t != Frs2s.sf)
809 Fsr = insertBits(Fsr, 4,0, 0x01);
810 }});
811 0xD2: fdtoi({{
812 Frds.sw = static_cast<int32_t>(Frs2.df);
813 double t = Frds.sw;
814 if (t != Frs2.df)
815 Fsr = insertBits(Fsr, 4,0, 0x01);
816 }});
817 0xD3: FpUnimpl::fqtoi();
818 default: FailUnimpl::fpop1();
819 }
820 }
821 0x35: decode OPF{
822 format FpBasic{
823 0x51: fcmps({{
824 uint8_t fcc;
825 if(isnan(Frs1s) || isnan(Frs2s))
826 fcc = 3;
827 else if(Frs1s < Frs2s)
828 fcc = 1;
829 else if(Frs1s > Frs2s)
830 fcc = 2;
831 else
832 fcc = 0;
833 uint8_t firstbit = 10;
834 if(FCMPCC)
835 firstbit = FCMPCC * 2 + 30;
836 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
837 }});
838 0x52: fcmpd({{
839 uint8_t fcc;
840 if(isnan(Frs1) || isnan(Frs2))
841 fcc = 3;
842 else if(Frs1 < Frs2)
843 fcc = 1;
844 else if(Frs1 > Frs2)
845 fcc = 2;
846 else
847 fcc = 0;
848 uint8_t firstbit = 10;
849 if(FCMPCC)
850 firstbit = FCMPCC * 2 + 30;
851 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
852 }});
853 0x53: FpUnimpl::fcmpq();
854 0x55: fcmpes({{
855 uint8_t fcc = 0;
856 if(isnan(Frs1s) || isnan(Frs2s))
857 fault = new FpExceptionIEEE754;
858 if(Frs1s < Frs2s)
859 fcc = 1;
860 else if(Frs1s > Frs2s)
861 fcc = 2;
862 uint8_t firstbit = 10;
863 if(FCMPCC)
864 firstbit = FCMPCC * 2 + 30;
865 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
866 }});
867 0x56: fcmped({{
868 uint8_t fcc = 0;
869 if(isnan(Frs1) || isnan(Frs2))
870 fault = new FpExceptionIEEE754;
871 if(Frs1 < Frs2)
872 fcc = 1;
873 else if(Frs1 > Frs2)
874 fcc = 2;
875 uint8_t firstbit = 10;
876 if(FCMPCC)
877 firstbit = FCMPCC * 2 + 30;
878 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
879 }});
880 0x57: FpUnimpl::fcmpeq();
881 default: FailUnimpl::fpop2();
882 }
883 }
884 //This used to be just impdep1, but now it's a whole bunch
885 //of instructions
886 0x36: decode OPF{
887 0x00: FailUnimpl::edge8();
888 0x01: FailUnimpl::edge8n();
889 0x02: FailUnimpl::edge8l();
890 0x03: FailUnimpl::edge8ln();
891 0x04: FailUnimpl::edge16();
892 0x05: FailUnimpl::edge16n();
893 0x06: FailUnimpl::edge16l();
894 0x07: FailUnimpl::edge16ln();
895 0x08: FailUnimpl::edge32();
896 0x09: FailUnimpl::edge32n();
897 0x0A: FailUnimpl::edge32l();
898 0x0B: FailUnimpl::edge32ln();
899 0x10: FailUnimpl::array8();
900 0x12: FailUnimpl::array16();
901 0x14: FailUnimpl::array32();
902 0x18: BasicOperate::alignaddr({{
903 uint64_t sum = Rs1 + Rs2;
904 Rd = sum & ~7;
905 Gsr = (Gsr & ~7) | (sum & 7);
906 }});
907 0x19: FailUnimpl::bmask();
908 0x1A: BasicOperate::alignaddresslittle({{
909 uint64_t sum = Rs1 + Rs2;
910 Rd = sum & ~7;
911 Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
912 }});
913 0x20: FailUnimpl::fcmple16();
914 0x22: FailUnimpl::fcmpne16();
915 0x24: FailUnimpl::fcmple32();
916 0x26: FailUnimpl::fcmpne32();
917 0x28: FailUnimpl::fcmpgt16();
918 0x2A: FailUnimpl::fcmpeq16();
919 0x2C: FailUnimpl::fcmpgt32();
920 0x2E: FailUnimpl::fcmpeq32();
921 0x31: FailUnimpl::fmul8x16();
922 0x33: FailUnimpl::fmul8x16au();
923 0x35: FailUnimpl::fmul8x16al();
924 0x36: FailUnimpl::fmul8sux16();
925 0x37: FailUnimpl::fmul8ulx16();
926 0x38: FailUnimpl::fmuld8sux16();
927 0x39: FailUnimpl::fmuld8ulx16();
928 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
929 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
930 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
931 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
932 0x48: BasicOperate::faligndata({{
933 uint64_t msbX = Frs1.udw;
934 uint64_t lsbX = Frs2.udw;
935 //Some special cases need to be split out, first
936 //because they're the most likely to be used, and
937 //second because otherwise, we end up shifting by
938 //greater than the width of the type being shifted,
939 //namely 64, which produces undefined results according
940 //to the C standard.
941 switch(Gsr<2:0>)
942 {
943 case 0:
944 Frd.udw = msbX;
945 break;
946 case 8:
947 Frd.udw = lsbX;
948 break;
949 default:
950 uint64_t msbShift = Gsr<2:0> * 8;
951 uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
952 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
953 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
954 Frd.udw = ((msbX & msbMask) << msbShift) |
955 ((lsbX & lsbMask) >> lsbShift);
956 }
957 }});
958 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
959 0x4C: FailUnimpl::bshuffle();
960 0x4D: FailUnimpl::fexpand();
961 0x50: FailUnimpl::fpadd16();
962 0x51: FailUnimpl::fpadd16s();
963 0x52: FailUnimpl::fpadd32();
964 0x53: FailUnimpl::fpadd32s();
965 0x54: FailUnimpl::fpsub16();
966 0x55: FailUnimpl::fpsub16s();
967 0x56: FailUnimpl::fpsub32();
968 0x57: FailUnimpl::fpsub32s();
969 0x60: FpBasic::fzero({{Frd.df = 0;}});
970 0x61: FpBasic::fzeros({{Frds.sf = 0;}});
971 0x62: FailUnimpl::fnor();
972 0x63: FailUnimpl::fnors();
973 0x64: FailUnimpl::fandnot2();
974 0x65: FailUnimpl::fandnot2s();
975 0x66: FpBasic::fnot2({{
976 Frd.df = (double)(~((uint64_t)Frs2.df));
977 }});
978 0x67: FpBasic::fnot2s({{
979 Frds.sf = (float)(~((uint32_t)Frs2s.sf));
980 }});
981 0x68: FailUnimpl::fandnot1();
982 0x69: FailUnimpl::fandnot1s();
983 0x6A: FpBasic::fnot1({{
984 Frd.df = (double)(~((uint64_t)Frs1.df));
985 }});
986 0x6B: FpBasic::fnot1s({{
987 Frds.sf = (float)(~((uint32_t)Frs1s.sf));
988 }});
989 0x6C: FailUnimpl::fxor();
990 0x6D: FailUnimpl::fxors();
991 0x6E: FailUnimpl::fnand();
992 0x6F: FailUnimpl::fnands();
993 0x70: FailUnimpl::fand();
994 0x71: FailUnimpl::fands();
995 0x72: FailUnimpl::fxnor();
996 0x73: FailUnimpl::fxnors();
997 0x74: FpBasic::fsrc1({{Frd.udw = Frs1.udw;}});
998 0x75: FpBasic::fsrc1s({{Frds.uw = Frs1s.uw;}});
999 0x76: FailUnimpl::fornot2();
1000 0x77: FailUnimpl::fornot2s();
1001 0x78: FpBasic::fsrc2({{Frd.udw = Frs2.udw;}});
1002 0x79: FpBasic::fsrc2s({{Frds.uw = Frs2s.uw;}});
1003 0x7A: FailUnimpl::fornot1();
1004 0x7B: FailUnimpl::fornot1s();
1005 0x7C: FailUnimpl::for();
1006 0x7D: FailUnimpl::fors();
1007 0x7E: FpBasic::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}});
1008 0x7F: FpBasic::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}});
1009 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
1010 0x81: FailUnimpl::siam();
1011 }
1012 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
1013 0x38: Branch::jmpl({{
1014 Addr target = Rs1 + Rs2_or_imm13;
1015 if(target & 0x3)
1016 fault = new MemAddressNotAligned;
1017 else
1018 {
1019 if (Pstate<3:>)
1020 Rd = (xc->readPC())<31:0>;
1021 else
1022 Rd = xc->readPC();
1023 NNPC = target;
1024 }
1025 }});
1026 0x39: Branch::return({{
1027 Addr target = Rs1 + Rs2_or_imm13;
1028 if(fault == NoFault)
1029 {
1030 //Check for fills which are higher priority than alignment
1031 //faults.
1032 if(Canrestore == 0)
1033 {
1034 if(Otherwin)
1035 fault = new FillNOther(4*Wstate<5:3>);
1036 else
1037 fault = new FillNNormal(4*Wstate<2:0>);
1038 }
1039 //Check for alignment faults
1040 else if(target & 0x3)
1041 fault = new MemAddressNotAligned;
1042 else
1043 {
1044 NNPC = target;
1045 Cwp = (Cwp - 1 + NWindows) % NWindows;
1046 Cansave = Cansave + 1;
1047 Canrestore = Canrestore - 1;
1048 }
1049 }
1050 }});
1051 0x3A: decode CC
1052 {
1053 0x0: Trap::tcci({{
1054 if(passesCondition(Ccr<3:0>, COND2))
1055 {
1056#if FULL_SYSTEM
1057 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
1058 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
1059 fault = new TrapInstruction(lTrapNum);
1060#else
1061 DPRINTF(Sparc, "The syscall number is %d\n", R1);
1062 xc->syscall(R1);
1063#endif
1064 }
1065 }}, IsSerializeAfter, IsNonSpeculative);
1066 0x2: Trap::tccx({{
1067 if(passesCondition(Ccr<7:4>, COND2))
1068 {
1069#if FULL_SYSTEM
1070 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
1071 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
1072 fault = new TrapInstruction(lTrapNum);
1073#else
1074 DPRINTF(Sparc, "The syscall number is %d\n", R1);
1075 xc->syscall(R1);
1076#endif
1077 }
1078 }}, IsSerializeAfter, IsNonSpeculative);
1079 }
1080 0x3B: Nop::flush({{/*Instruction memory flush*/}});
1081 0x3C: save({{
1082 if(Cansave == 0)
1083 {
1084 if(Otherwin)
1085 fault = new SpillNOther(4*Wstate<5:3>);
1086 else
1087 fault = new SpillNNormal(4*Wstate<2:0>);
1088 }
1089 else if(Cleanwin - Canrestore == 0)
1090 {
1091 fault = new CleanWindow;
1092 }
1093 else
1094 {
1095 Cwp = (Cwp + 1) % NWindows;
1096 Rd_next = Rs1 + Rs2_or_imm13;
1097 Cansave = Cansave - 1;
1098 Canrestore = Canrestore + 1;
1099 }
1100 }});
1101 0x3D: restore({{
1102 if(Canrestore == 0)
1103 {
1104 if(Otherwin)
1105 fault = new FillNOther(4*Wstate<5:3>);
1106 else
1107 fault = new FillNNormal(4*Wstate<2:0>);
1108 }
1109 else
1110 {
1111 Cwp = (Cwp - 1 + NWindows) % NWindows;
1112 Rd_prev = Rs1 + Rs2_or_imm13;
1113 Cansave = Cansave + 1;
1114 Canrestore = Canrestore - 1;
1115 }
1116 }});
1117 0x3E: decode FCN {
1118 0x0: Priv::done({{
1119 if(Tl == 0)
1120 return new IllegalInstruction;
1121
1122 Cwp = Tstate<4:0>;
1123 Pstate = Tstate<20:8>;
1124 Asi = Tstate<31:24>;
1125 Ccr = Tstate<39:32>;
1126 Gl = Tstate<42:40>;
1127 Hpstate = Htstate;
1128 NPC = Tnpc;
1129 NNPC = Tnpc + 4;
1130 Tl = Tl - 1;
1131 }});
1132 0x1: Priv::retry({{
1133 if(Tl == 0)
1134 return new IllegalInstruction;
1135 Cwp = Tstate<4:0>;
1136 Pstate = Tstate<20:8>;
1137 Asi = Tstate<31:24>;
1138 Ccr = Tstate<39:32>;
1139 Gl = Tstate<42:40>;
1140 Hpstate = Htstate;
1141 NPC = Tpc;
1142 NNPC = Tnpc;
1143 Tl = Tl - 1;
1144 }});
1145 }
1146 }
1147 }
1148 0x3: decode OP3 {
1149 format Load {
1150 0x00: lduw({{Rd = Mem.uw;}});
1151 0x01: ldub({{Rd = Mem.ub;}});
1152 0x02: lduh({{Rd = Mem.uhw;}});
1153 0x03: ldtw({{
1154 uint64_t val = Mem.udw;
1155 RdLow = val<31:0>;
1156 RdHigh = val<63:32>;
1157 }});
1158 }
1159 format Store {
1160 0x04: stw({{Mem.uw = Rd.sw;}});
1161 0x05: stb({{Mem.ub = Rd.sb;}});
1162 0x06: sth({{Mem.uhw = Rd.shw;}});
1163 0x07: sttw({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
1164 }
1165 format Load {
1166 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
1167 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
1168 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
1169 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
1170 }
| 477 }
478 0x10: Priv::rdpcr({{Rd = Pcr;}});
479 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
480 //0x12 should cause an illegal instruction exception
481 0x13: NoPriv::rdgsr({{
482 fault = checkFpEnableFault(xc);
483 if (fault)
484 return fault;
485 Rd = Gsr;
486 }});
487 //0x14-0x15 should cause an illegal instruction exception
488 0x16: Priv::rdsoftint({{Rd = Softint;}});
489 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
490 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}});
491 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
492 0x1A: Priv::rdstrand_sts_reg({{
493 if(Pstate<2:> && !Hpstate<2:>)
494 Rd = StrandStsReg<0:>;
495 else
496 Rd = StrandStsReg;
497 }});
498 //0x1A is supposed to be reserved, but it reads the strand
499 //status register.
500 //0x1B-0x1F should cause an illegal instruction exception
501 }
502 0x29: decode RS1 {
503 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
504 0x01: HPriv::rdhprhtstate({{
505 if(Tl == 0)
506 return new IllegalInstruction;
507 Rd = Htstate;
508 }});
509 //0x02 should cause an illegal instruction exception
510 0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
511 //0x04 should cause an illegal instruction exception
512 0x05: HPriv::rdhprhtba({{Rd = Htba;}});
513 0x06: HPriv::rdhprhver({{Rd = Hver;}});
514 //0x07-0x1E should cause an illegal instruction exception
515 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
516 }
517 0x2A: decode RS1 {
518 0x00: Priv::rdprtpc({{
519 if(Tl == 0)
520 return new IllegalInstruction;
521 Rd = Tpc;
522 }});
523 0x01: Priv::rdprtnpc({{
524 if(Tl == 0)
525 return new IllegalInstruction;
526 Rd = Tnpc;
527 }});
528 0x02: Priv::rdprtstate({{
529 if(Tl == 0)
530 return new IllegalInstruction;
531 Rd = Tstate;
532 }});
533 0x03: Priv::rdprtt({{
534 if(Tl == 0)
535 return new IllegalInstruction;
536 Rd = Tt;
537 }});
538 0x04: Priv::rdprtick({{Rd = Tick;}});
539 0x05: Priv::rdprtba({{Rd = Tba;}});
540 0x06: Priv::rdprpstate({{Rd = Pstate;}});
541 0x07: Priv::rdprtl({{Rd = Tl;}});
542 0x08: Priv::rdprpil({{Rd = Pil;}});
543 0x09: Priv::rdprcwp({{Rd = Cwp;}});
544 0x0A: Priv::rdprcansave({{Rd = Cansave;}});
545 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});
546 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});
547 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}});
548 0x0E: Priv::rdprwstate({{Rd = Wstate;}});
549 //0x0F should cause an illegal instruction exception
550 0x10: Priv::rdprgl({{Rd = Gl;}});
551 //0x11-0x1F should cause an illegal instruction exception
552 }
553 0x2B: BasicOperate::flushw({{
554 if(NWindows - 2 - Cansave != 0)
555 {
556 if(Otherwin)
557 fault = new SpillNOther(4*Wstate<5:3>);
558 else
559 fault = new SpillNNormal(4*Wstate<2:0>);
560 }
561 }});
562 0x2C: decode MOVCC3
563 {
564 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
565 0x1: decode CC
566 {
567 0x0: movcci({{
568 if(passesCondition(Ccr<3:0>, COND4))
569 Rd = Rs2_or_imm11;
570 else
571 Rd = Rd;
572 }});
573 0x2: movccx({{
574 if(passesCondition(Ccr<7:4>, COND4))
575 Rd = Rs2_or_imm11;
576 else
577 Rd = Rd;
578 }});
579 }
580 }
581 0x2D: sdivx({{
582 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
583 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
584 }});
585 0x2E: Trap::popc({{fault = new IllegalInstruction;}});
586 0x2F: decode RCOND3
587 {
588 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
589 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
590 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
591 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
592 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
593 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
594 }
595 0x30: decode RD {
596 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}});
597 //0x01 should cause an illegal instruction exception
598 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
599 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
600 //0x04-0x05 should cause an illegal instruction exception
601 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
602 //0x07-0x0E should cause an illegal instruction exception
603 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
604 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
605 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
606 //0x12 should cause an illegal instruction exception
607 0x13: NoPriv::wrgsr({{
608 if(Fprs<2:> == 0 || Pstate<4:> == 0)
609 return new FpDisabled;
610 Gsr = Rs1 ^ Rs2_or_imm13;
611 }});
612 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
613 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});
614 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
615 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}});
616 0x18: NoPriv::wrstick({{
617 if(!Hpstate<2:>)
618 return new IllegalInstruction;
619 Stick = Rs1 ^ Rs2_or_imm13;
620 }});
621 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}});
622 0x1A: Priv::wrstrand_sts_reg({{
623 if(Pstate<2:> && !Hpstate<2:>)
624 StrandStsReg = StrandStsReg<63:1> |
625 (Rs1 ^ Rs2_or_imm13)<0:>;
626 else
627 StrandStsReg = Rs1 ^ Rs2_or_imm13;
628 }});
629 //0x1A is supposed to be reserved, but it writes the strand
630 //status register.
631 //0x1B-0x1F should cause an illegal instruction exception
632 }
633 0x31: decode FCN {
634 0x0: Priv::saved({{
635 assert(Cansave < NWindows - 2);
636 assert(Otherwin || Canrestore);
637 Cansave = Cansave + 1;
638 if(Otherwin == 0)
639 Canrestore = Canrestore - 1;
640 else
641 Otherwin = Otherwin - 1;
642 }});
643 0x1: Priv::restored({{
644 assert(Cansave || Otherwin);
645 assert(Canrestore < NWindows - 2);
646 Canrestore = Canrestore + 1;
647 if(Otherwin == 0)
648 Cansave = Cansave - 1;
649 else
650 Otherwin = Otherwin - 1;
651
652 if(Cleanwin < NWindows - 1)
653 Cleanwin = Cleanwin + 1;
654 }});
655 }
656 0x32: decode RD {
657 0x00: Priv::wrprtpc({{
658 if(Tl == 0)
659 return new IllegalInstruction;
660 else
661 Tpc = Rs1 ^ Rs2_or_imm13;
662 }});
663 0x01: Priv::wrprtnpc({{
664 if(Tl == 0)
665 return new IllegalInstruction;
666 else
667 Tnpc = Rs1 ^ Rs2_or_imm13;
668 }});
669 0x02: Priv::wrprtstate({{
670 if(Tl == 0)
671 return new IllegalInstruction;
672 else
673 Tstate = Rs1 ^ Rs2_or_imm13;
674 }});
675 0x03: Priv::wrprtt({{
676 if(Tl == 0)
677 return new IllegalInstruction;
678 else
679 Tt = Rs1 ^ Rs2_or_imm13;
680 }});
681 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
682 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
683 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
684 0x07: Priv::wrprtl({{
685 if(Pstate<2:> && !Hpstate<2:>)
686 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
687 else
688 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);
689 }});
690 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
691 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
692 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
693 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
694 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
695 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
696 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
697 //0x0F should cause an illegal instruction exception
698 0x10: Priv::wrprgl({{
699 if(Pstate<2:> && !Hpstate<2:>)
700 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL);
701 else
702 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
703 }});
704 //0x11-0x1F should cause an illegal instruction exception
705 }
706 0x33: decode RD {
707 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
708 0x01: HPriv::wrhprhtstate({{
709 if(Tl == 0)
710 return new IllegalInstruction;
711 Htstate = Rs1 ^ Rs2_or_imm13;
712 }});
713 //0x02 should cause an illegal instruction exception
714 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
715 //0x04 should cause an illegal instruction exception
716 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
717 //0x06-0x01D should cause an illegal instruction exception
718 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
719 }
720 0x34: decode OPF{
721 format FpBasic{
722 0x01: fmovs({{
723 Frds.uw = Frs2s.uw;
724 //fsr.ftt = fsr.cexc = 0
725 Fsr &= ~(7 << 14);
726 Fsr &= ~(0x1F);
727 }});
728 0x02: fmovd({{
729 Frd.udw = Frs2.udw;
730 //fsr.ftt = fsr.cexc = 0
731 Fsr &= ~(7 << 14);
732 Fsr &= ~(0x1F);
733 }});
734 0x03: FpUnimpl::fmovq();
735 0x05: fnegs({{
736 Frds.uw = Frs2s.uw ^ (1UL << 31);
737 //fsr.ftt = fsr.cexc = 0
738 Fsr &= ~(7 << 14);
739 Fsr &= ~(0x1F);
740 }});
741 0x06: fnegd({{
742 Frd.udw = Frs2.udw ^ (1ULL << 63);
743 //fsr.ftt = fsr.cexc = 0
744 Fsr &= ~(7 << 14);
745 Fsr &= ~(0x1F);
746 }});
747 0x07: FpUnimpl::fnegq();
748 0x09: fabss({{
749 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;
750 //fsr.ftt = fsr.cexc = 0
751 Fsr &= ~(7 << 14);
752 Fsr &= ~(0x1F);
753 }});
754 0x0A: fabsd({{
755 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;
756 //fsr.ftt = fsr.cexc = 0
757 Fsr &= ~(7 << 14);
758 Fsr &= ~(0x1F);
759 }});
760 0x0B: FpUnimpl::fabsq();
761 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}});
762 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}});
763 0x2B: FpUnimpl::fsqrtq();
764 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
765 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
766 0x43: FpUnimpl::faddq();
767 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
768 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df; }});
769 0x47: FpUnimpl::fsubq();
770 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
771 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
772 0x4B: FpUnimpl::fmulq();
773 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
774 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
775 0x4F: FpUnimpl::fdivq();
776 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
777 0x6E: FpUnimpl::fdmulq();
778 0x81: fstox({{
779 Frd.sdw = static_cast<int64_t>(Frs2s.sf);
780 }});
781 0x82: fdtox({{
782 Frd.sdw = static_cast<int64_t>(Frs2.df);
783 }});
784 0x83: FpUnimpl::fqtox();
785 0x84: fxtos({{
786 Frds.sf = static_cast<float>(Frs2.sdw);
787 }});
788 0x88: fxtod({{
789 Frd.df = static_cast<double>(Frs2.sdw);
790 }});
791 0x8C: FpUnimpl::fxtoq();
792 0xC4: fitos({{
793 Frds.sf = static_cast<float>(Frs2s.sw);
794 }});
795 0xC6: fdtos({{Frds.sf = Frs2.df;}});
796 0xC7: FpUnimpl::fqtos();
797 0xC8: fitod({{
798 Frd.df = static_cast<double>(Frs2s.sw);
799 }});
800 0xC9: fstod({{Frd.df = Frs2s.sf;}});
801 0xCB: FpUnimpl::fqtod();
802 0xCC: FpUnimpl::fitoq();
803 0xCD: FpUnimpl::fstoq();
804 0xCE: FpUnimpl::fdtoq();
805 0xD1: fstoi({{
806 Frds.sw = static_cast<int32_t>(Frs2s.sf);
807 float t = Frds.sw;
808 if (t != Frs2s.sf)
809 Fsr = insertBits(Fsr, 4,0, 0x01);
810 }});
811 0xD2: fdtoi({{
812 Frds.sw = static_cast<int32_t>(Frs2.df);
813 double t = Frds.sw;
814 if (t != Frs2.df)
815 Fsr = insertBits(Fsr, 4,0, 0x01);
816 }});
817 0xD3: FpUnimpl::fqtoi();
818 default: FailUnimpl::fpop1();
819 }
820 }
821 0x35: decode OPF{
822 format FpBasic{
823 0x51: fcmps({{
824 uint8_t fcc;
825 if(isnan(Frs1s) || isnan(Frs2s))
826 fcc = 3;
827 else if(Frs1s < Frs2s)
828 fcc = 1;
829 else if(Frs1s > Frs2s)
830 fcc = 2;
831 else
832 fcc = 0;
833 uint8_t firstbit = 10;
834 if(FCMPCC)
835 firstbit = FCMPCC * 2 + 30;
836 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
837 }});
838 0x52: fcmpd({{
839 uint8_t fcc;
840 if(isnan(Frs1) || isnan(Frs2))
841 fcc = 3;
842 else if(Frs1 < Frs2)
843 fcc = 1;
844 else if(Frs1 > Frs2)
845 fcc = 2;
846 else
847 fcc = 0;
848 uint8_t firstbit = 10;
849 if(FCMPCC)
850 firstbit = FCMPCC * 2 + 30;
851 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
852 }});
853 0x53: FpUnimpl::fcmpq();
854 0x55: fcmpes({{
855 uint8_t fcc = 0;
856 if(isnan(Frs1s) || isnan(Frs2s))
857 fault = new FpExceptionIEEE754;
858 if(Frs1s < Frs2s)
859 fcc = 1;
860 else if(Frs1s > Frs2s)
861 fcc = 2;
862 uint8_t firstbit = 10;
863 if(FCMPCC)
864 firstbit = FCMPCC * 2 + 30;
865 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
866 }});
867 0x56: fcmped({{
868 uint8_t fcc = 0;
869 if(isnan(Frs1) || isnan(Frs2))
870 fault = new FpExceptionIEEE754;
871 if(Frs1 < Frs2)
872 fcc = 1;
873 else if(Frs1 > Frs2)
874 fcc = 2;
875 uint8_t firstbit = 10;
876 if(FCMPCC)
877 firstbit = FCMPCC * 2 + 30;
878 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
879 }});
880 0x57: FpUnimpl::fcmpeq();
881 default: FailUnimpl::fpop2();
882 }
883 }
884 //This used to be just impdep1, but now it's a whole bunch
885 //of instructions
886 0x36: decode OPF{
887 0x00: FailUnimpl::edge8();
888 0x01: FailUnimpl::edge8n();
889 0x02: FailUnimpl::edge8l();
890 0x03: FailUnimpl::edge8ln();
891 0x04: FailUnimpl::edge16();
892 0x05: FailUnimpl::edge16n();
893 0x06: FailUnimpl::edge16l();
894 0x07: FailUnimpl::edge16ln();
895 0x08: FailUnimpl::edge32();
896 0x09: FailUnimpl::edge32n();
897 0x0A: FailUnimpl::edge32l();
898 0x0B: FailUnimpl::edge32ln();
899 0x10: FailUnimpl::array8();
900 0x12: FailUnimpl::array16();
901 0x14: FailUnimpl::array32();
902 0x18: BasicOperate::alignaddr({{
903 uint64_t sum = Rs1 + Rs2;
904 Rd = sum & ~7;
905 Gsr = (Gsr & ~7) | (sum & 7);
906 }});
907 0x19: FailUnimpl::bmask();
908 0x1A: BasicOperate::alignaddresslittle({{
909 uint64_t sum = Rs1 + Rs2;
910 Rd = sum & ~7;
911 Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
912 }});
913 0x20: FailUnimpl::fcmple16();
914 0x22: FailUnimpl::fcmpne16();
915 0x24: FailUnimpl::fcmple32();
916 0x26: FailUnimpl::fcmpne32();
917 0x28: FailUnimpl::fcmpgt16();
918 0x2A: FailUnimpl::fcmpeq16();
919 0x2C: FailUnimpl::fcmpgt32();
920 0x2E: FailUnimpl::fcmpeq32();
921 0x31: FailUnimpl::fmul8x16();
922 0x33: FailUnimpl::fmul8x16au();
923 0x35: FailUnimpl::fmul8x16al();
924 0x36: FailUnimpl::fmul8sux16();
925 0x37: FailUnimpl::fmul8ulx16();
926 0x38: FailUnimpl::fmuld8sux16();
927 0x39: FailUnimpl::fmuld8ulx16();
928 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
929 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
930 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
931 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
932 0x48: BasicOperate::faligndata({{
933 uint64_t msbX = Frs1.udw;
934 uint64_t lsbX = Frs2.udw;
935 //Some special cases need to be split out, first
936 //because they're the most likely to be used, and
937 //second because otherwise, we end up shifting by
938 //greater than the width of the type being shifted,
939 //namely 64, which produces undefined results according
940 //to the C standard.
941 switch(Gsr<2:0>)
942 {
943 case 0:
944 Frd.udw = msbX;
945 break;
946 case 8:
947 Frd.udw = lsbX;
948 break;
949 default:
950 uint64_t msbShift = Gsr<2:0> * 8;
951 uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
952 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
953 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
954 Frd.udw = ((msbX & msbMask) << msbShift) |
955 ((lsbX & lsbMask) >> lsbShift);
956 }
957 }});
958 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
959 0x4C: FailUnimpl::bshuffle();
960 0x4D: FailUnimpl::fexpand();
961 0x50: FailUnimpl::fpadd16();
962 0x51: FailUnimpl::fpadd16s();
963 0x52: FailUnimpl::fpadd32();
964 0x53: FailUnimpl::fpadd32s();
965 0x54: FailUnimpl::fpsub16();
966 0x55: FailUnimpl::fpsub16s();
967 0x56: FailUnimpl::fpsub32();
968 0x57: FailUnimpl::fpsub32s();
969 0x60: FpBasic::fzero({{Frd.df = 0;}});
970 0x61: FpBasic::fzeros({{Frds.sf = 0;}});
971 0x62: FailUnimpl::fnor();
972 0x63: FailUnimpl::fnors();
973 0x64: FailUnimpl::fandnot2();
974 0x65: FailUnimpl::fandnot2s();
975 0x66: FpBasic::fnot2({{
976 Frd.df = (double)(~((uint64_t)Frs2.df));
977 }});
978 0x67: FpBasic::fnot2s({{
979 Frds.sf = (float)(~((uint32_t)Frs2s.sf));
980 }});
981 0x68: FailUnimpl::fandnot1();
982 0x69: FailUnimpl::fandnot1s();
983 0x6A: FpBasic::fnot1({{
984 Frd.df = (double)(~((uint64_t)Frs1.df));
985 }});
986 0x6B: FpBasic::fnot1s({{
987 Frds.sf = (float)(~((uint32_t)Frs1s.sf));
988 }});
989 0x6C: FailUnimpl::fxor();
990 0x6D: FailUnimpl::fxors();
991 0x6E: FailUnimpl::fnand();
992 0x6F: FailUnimpl::fnands();
993 0x70: FailUnimpl::fand();
994 0x71: FailUnimpl::fands();
995 0x72: FailUnimpl::fxnor();
996 0x73: FailUnimpl::fxnors();
997 0x74: FpBasic::fsrc1({{Frd.udw = Frs1.udw;}});
998 0x75: FpBasic::fsrc1s({{Frds.uw = Frs1s.uw;}});
999 0x76: FailUnimpl::fornot2();
1000 0x77: FailUnimpl::fornot2s();
1001 0x78: FpBasic::fsrc2({{Frd.udw = Frs2.udw;}});
1002 0x79: FpBasic::fsrc2s({{Frds.uw = Frs2s.uw;}});
1003 0x7A: FailUnimpl::fornot1();
1004 0x7B: FailUnimpl::fornot1s();
1005 0x7C: FailUnimpl::for();
1006 0x7D: FailUnimpl::fors();
1007 0x7E: FpBasic::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}});
1008 0x7F: FpBasic::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}});
1009 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
1010 0x81: FailUnimpl::siam();
1011 }
1012 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
1013 0x38: Branch::jmpl({{
1014 Addr target = Rs1 + Rs2_or_imm13;
1015 if(target & 0x3)
1016 fault = new MemAddressNotAligned;
1017 else
1018 {
1019 if (Pstate<3:>)
1020 Rd = (xc->readPC())<31:0>;
1021 else
1022 Rd = xc->readPC();
1023 NNPC = target;
1024 }
1025 }});
1026 0x39: Branch::return({{
1027 Addr target = Rs1 + Rs2_or_imm13;
1028 if(fault == NoFault)
1029 {
1030 //Check for fills which are higher priority than alignment
1031 //faults.
1032 if(Canrestore == 0)
1033 {
1034 if(Otherwin)
1035 fault = new FillNOther(4*Wstate<5:3>);
1036 else
1037 fault = new FillNNormal(4*Wstate<2:0>);
1038 }
1039 //Check for alignment faults
1040 else if(target & 0x3)
1041 fault = new MemAddressNotAligned;
1042 else
1043 {
1044 NNPC = target;
1045 Cwp = (Cwp - 1 + NWindows) % NWindows;
1046 Cansave = Cansave + 1;
1047 Canrestore = Canrestore - 1;
1048 }
1049 }
1050 }});
1051 0x3A: decode CC
1052 {
1053 0x0: Trap::tcci({{
1054 if(passesCondition(Ccr<3:0>, COND2))
1055 {
1056#if FULL_SYSTEM
1057 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
1058 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
1059 fault = new TrapInstruction(lTrapNum);
1060#else
1061 DPRINTF(Sparc, "The syscall number is %d\n", R1);
1062 xc->syscall(R1);
1063#endif
1064 }
1065 }}, IsSerializeAfter, IsNonSpeculative);
1066 0x2: Trap::tccx({{
1067 if(passesCondition(Ccr<7:4>, COND2))
1068 {
1069#if FULL_SYSTEM
1070 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
1071 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
1072 fault = new TrapInstruction(lTrapNum);
1073#else
1074 DPRINTF(Sparc, "The syscall number is %d\n", R1);
1075 xc->syscall(R1);
1076#endif
1077 }
1078 }}, IsSerializeAfter, IsNonSpeculative);
1079 }
1080 0x3B: Nop::flush({{/*Instruction memory flush*/}});
1081 0x3C: save({{
1082 if(Cansave == 0)
1083 {
1084 if(Otherwin)
1085 fault = new SpillNOther(4*Wstate<5:3>);
1086 else
1087 fault = new SpillNNormal(4*Wstate<2:0>);
1088 }
1089 else if(Cleanwin - Canrestore == 0)
1090 {
1091 fault = new CleanWindow;
1092 }
1093 else
1094 {
1095 Cwp = (Cwp + 1) % NWindows;
1096 Rd_next = Rs1 + Rs2_or_imm13;
1097 Cansave = Cansave - 1;
1098 Canrestore = Canrestore + 1;
1099 }
1100 }});
1101 0x3D: restore({{
1102 if(Canrestore == 0)
1103 {
1104 if(Otherwin)
1105 fault = new FillNOther(4*Wstate<5:3>);
1106 else
1107 fault = new FillNNormal(4*Wstate<2:0>);
1108 }
1109 else
1110 {
1111 Cwp = (Cwp - 1 + NWindows) % NWindows;
1112 Rd_prev = Rs1 + Rs2_or_imm13;
1113 Cansave = Cansave + 1;
1114 Canrestore = Canrestore - 1;
1115 }
1116 }});
1117 0x3E: decode FCN {
1118 0x0: Priv::done({{
1119 if(Tl == 0)
1120 return new IllegalInstruction;
1121
1122 Cwp = Tstate<4:0>;
1123 Pstate = Tstate<20:8>;
1124 Asi = Tstate<31:24>;
1125 Ccr = Tstate<39:32>;
1126 Gl = Tstate<42:40>;
1127 Hpstate = Htstate;
1128 NPC = Tnpc;
1129 NNPC = Tnpc + 4;
1130 Tl = Tl - 1;
1131 }});
1132 0x1: Priv::retry({{
1133 if(Tl == 0)
1134 return new IllegalInstruction;
1135 Cwp = Tstate<4:0>;
1136 Pstate = Tstate<20:8>;
1137 Asi = Tstate<31:24>;
1138 Ccr = Tstate<39:32>;
1139 Gl = Tstate<42:40>;
1140 Hpstate = Htstate;
1141 NPC = Tpc;
1142 NNPC = Tnpc;
1143 Tl = Tl - 1;
1144 }});
1145 }
1146 }
1147 }
1148 0x3: decode OP3 {
1149 format Load {
1150 0x00: lduw({{Rd = Mem.uw;}});
1151 0x01: ldub({{Rd = Mem.ub;}});
1152 0x02: lduh({{Rd = Mem.uhw;}});
1153 0x03: ldtw({{
1154 uint64_t val = Mem.udw;
1155 RdLow = val<31:0>;
1156 RdHigh = val<63:32>;
1157 }});
1158 }
1159 format Store {
1160 0x04: stw({{Mem.uw = Rd.sw;}});
1161 0x05: stb({{Mem.ub = Rd.sb;}});
1162 0x06: sth({{Mem.uhw = Rd.shw;}});
1163 0x07: sttw({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
1164 }
1165 format Load {
1166 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
1167 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
1168 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
1169 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
1170 }
|
1171 0x0D: LoadStore::ldstub(
1172 {{uReg0 = Mem.ub;}},
1173 {{Rd.ub = uReg0;
1174 Mem.ub = 0xFF;}});
| 1171 0x0D: Swap::ldstub({{Mem.ub = 0xFF;}},
1172 {{
1173 uint8_t tmp = mem_data;
1174 Rd.ub = tmp;
1175 }}, MEM_SWAP);
|
1175 0x0E: Store::stx({{Mem.udw = Rd}});
| 1176 0x0E: Store::stx({{Mem.udw = Rd}});
|
1176 0x0F: LoadStore::swap(
1177 {{ uReg0 = Mem.uw}},
1178 {{ Mem.uw = Rd.uw;
1179 Rd.uw = uReg0;}});
| 1177 0x0F: Swap::swap({{Mem.uw = Rd.uw}},
1178 {{
1179 uint32_t tmp = mem_data;
1180 Rd.uw = tmp;
1181 }}, MEM_SWAP);
|
1180 format LoadAlt {
1181 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
1182 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
1183 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
1184 0x13: decode EXT_ASI {
1185 //ASI_LDTD_AIUP
1186 0x22: TwinLoad::ldtx_aiup(
| 1182 format LoadAlt {
1183 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
1184 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
1185 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
1186 0x13: decode EXT_ASI {
1187 //ASI_LDTD_AIUP
1188 0x22: TwinLoad::ldtx_aiup(
|
1187 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
| 1189 {{RdLow.udw = (Mem.tudw).a;
1190 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
|
1188 //ASI_LDTD_AIUS
1189 0x23: TwinLoad::ldtx_aius(
| 1191 //ASI_LDTD_AIUS
1192 0x23: TwinLoad::ldtx_aius(
|
1190 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
| 1193 {{RdLow.udw = (Mem.tudw).a;
1194 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
|
1191 //ASI_QUAD_LDD
1192 0x24: TwinLoad::ldtx_quad_ldd(
| 1195 //ASI_QUAD_LDD
1196 0x24: TwinLoad::ldtx_quad_ldd(
|
1193 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
| 1197 {{RdLow.udw = (Mem.tudw).a;
1198 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
|
1194 //ASI_LDTX_REAL
1195 0x26: TwinLoad::ldtx_real(
| 1199 //ASI_LDTX_REAL
1200 0x26: TwinLoad::ldtx_real(
|
1196 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1197 //ASI_LDTX_N
1198 0x27: TwinLoad::ldtx_n(
1199 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1200 //ASI_LDTX_L
1201 0x2C: TwinLoad::ldtx_l(
1202 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
| 1201 {{RdLow.udw = (Mem.tudw).a;
1202 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1203 //ASI_LDTX_N
1204 0x27: TwinLoad::ldtx_n(
1205 {{RdLow.udw = (Mem.tudw).a;
1206 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1207 //ASI_LDTX_AIUP_L
1208 0x2A: TwinLoad::ldtx_aiup_l(
1209 {{RdLow.udw = (Mem.tudw).a;
1210 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1211 //ASI_LDTX_AIUS_L
1212 0x2B: TwinLoad::ldtx_aius_l(
1213 {{RdLow.udw = (Mem.tudw).a;
1214 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1215 //ASI_LDTX_L
1216 0x2C: TwinLoad::ldtx_l(
1217 {{RdLow.udw = (Mem.tudw).a;
1218 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
|
1203 //ASI_LDTX_REAL_L
1204 0x2E: TwinLoad::ldtx_real_l(
| 1219 //ASI_LDTX_REAL_L
1220 0x2E: TwinLoad::ldtx_real_l(
|
1205 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
| 1221 {{RdLow.udw = (Mem.tudw).a;
1222 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
|
1206 //ASI_LDTX_N_L
1207 0x2F: TwinLoad::ldtx_n_l(
| 1223 //ASI_LDTX_N_L
1224 0x2F: TwinLoad::ldtx_n_l(
|
1208 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
| 1225 {{RdLow.udw = (Mem.tudw).a;
1226 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
|
1209 //ASI_LDTX_P
1210 0xE2: TwinLoad::ldtx_p(
| 1227 //ASI_LDTX_P
1228 0xE2: TwinLoad::ldtx_p(
|
1211 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
| 1229 {{RdLow.udw = (Mem.tudw).a;
1230 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
|
1212 //ASI_LDTX_S
1213 0xE3: TwinLoad::ldtx_s(
| 1231 //ASI_LDTX_S
1232 0xE3: TwinLoad::ldtx_s(
|
1214 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
| 1233 {{RdLow.udw = (Mem.tudw).a;
1234 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1235 //ASI_LDTX_PL
1236 0xEA: TwinLoad::ldtx_pl(
1237 {{RdLow.udw = (Mem.tudw).a;
1238 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
1239 //ASI_LDTX_SL
1240 0xEB: TwinLoad::ldtx_sl(
1241 {{RdLow.udw = (Mem.tudw).a;
1242 RdHigh.udw = (Mem.tudw).b;}}, {{EXT_ASI}});
|
1215 default: ldtwa({{
1216 uint64_t val = Mem.udw;
1217 RdLow = val<31:0>;
1218 RdHigh = val<63:32>;
1219 }}, {{EXT_ASI}});
1220 }
1221 }
1222 format StoreAlt {
1223 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
1224 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
1225 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
1226 0x17: sttwa({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}});
1227 }
1228 format LoadAlt {
1229 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
1230 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}});
1231 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}});
1232 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}});
1233 }
| 1243 default: ldtwa({{
1244 uint64_t val = Mem.udw;
1245 RdLow = val<31:0>;
1246 RdHigh = val<63:32>;
1247 }}, {{EXT_ASI}});
1248 }
1249 }
1250 format StoreAlt {
1251 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
1252 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
1253 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
1254 0x17: sttwa({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}});
1255 }
1256 format LoadAlt {
1257 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
1258 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}});
1259 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}});
1260 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}});
1261 }
|
1234 0x1D: LoadStoreAlt::ldstuba(
1235 {{uReg0 = Mem.ub;}},
1236 {{Rd.ub = uReg0;
1237 Mem.ub = 0xFF;}}, {{EXT_ASI}});
| 1262 0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}},
1263 {{
1264 uint8_t tmp = mem_data;
1265 Rd.ub = tmp;
1266 }}, {{EXT_ASI}}, MEM_SWAP);
|
1238 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}});
| 1267 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}});
|
1239 0x1F: LoadStoreAlt::swapa(
1240 {{ uReg0 = Mem.uw}},
1241 {{ Mem.uw = Rd.uw;
1242 Rd.uw = uReg0;}}, {{EXT_ASI}});
| 1268 0x1F: SwapAlt::swapa({{Mem.uw = Rd.uw}},
1269 {{
1270 uint32_t tmp = mem_data;
1271 Rd.uw = tmp;
1272 }}, {{EXT_ASI}}, MEM_SWAP);
1273
|
1243 format Trap {
1244 0x20: Load::ldf({{Frds.uw = Mem.uw;}});
1245 0x21: decode RD {
1246 0x0: Load::ldfsr({{fault = checkFpEnableFault(xc);
1247 if (fault)
1248 return fault;
1249 Fsr = Mem.uw | Fsr<63:32>;}});
1250 0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc);
1251 if (fault)
1252 return fault;
1253 Fsr = Mem.udw;}});
1254 default: FailUnimpl::ldfsrOther();
1255 }
1256 0x22: ldqf({{fault = new FpDisabled;}});
1257 0x23: Load::lddf({{Frd.udw = Mem.udw;}});
1258 0x24: Store::stf({{Mem.uw = Frds.uw;}});
1259 0x25: decode RD {
1260 0x0: Store::stfsr({{fault = checkFpEnableFault(xc);
1261 if (fault)
1262 return fault;
1263 Mem.uw = Fsr<31:0>;
1264 Fsr = insertBits(Fsr,16,14,0);}});
1265 0x1: Store::stxfsr({{fault = checkFpEnableFault(xc);
1266 if (fault)
1267 return fault;
1268 Mem.udw = Fsr;
1269 Fsr = insertBits(Fsr,16,14,0);}});
1270 default: FailUnimpl::stfsrOther();
1271 }
1272 0x26: stqf({{fault = new FpDisabled;}});
1273 0x27: Store::stdf({{Mem.udw = Frd.udw;}});
1274 0x2D: Nop::prefetch({{ }});
1275 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}});
1276 0x32: ldqfa({{fault = new FpDisabled;}});
1277 format LoadAlt {
1278 0x33: decode EXT_ASI {
1279 //ASI_NUCLEUS
1280 0x04: FailUnimpl::lddfa_n();
1281 //ASI_NUCLEUS_LITTLE
1282 0x0C: FailUnimpl::lddfa_nl();
1283 //ASI_AS_IF_USER_PRIMARY
1284 0x10: FailUnimpl::lddfa_aiup();
1285 //ASI_AS_IF_USER_PRIMARY_LITTLE
1286 0x18: FailUnimpl::lddfa_aiupl();
1287 //ASI_AS_IF_USER_SECONDARY
1288 0x11: FailUnimpl::lddfa_aius();
1289 //ASI_AS_IF_USER_SECONDARY_LITTLE
1290 0x19: FailUnimpl::lddfa_aiusl();
1291 //ASI_REAL
1292 0x14: FailUnimpl::lddfa_real();
1293 //ASI_REAL_LITTLE
1294 0x1C: FailUnimpl::lddfa_real_l();
1295 //ASI_REAL_IO
1296 0x15: FailUnimpl::lddfa_real_io();
1297 //ASI_REAL_IO_LITTLE
1298 0x1D: FailUnimpl::lddfa_real_io_l();
1299 //ASI_PRIMARY
1300 0x80: FailUnimpl::lddfa_p();
1301 //ASI_PRIMARY_LITTLE
1302 0x88: FailUnimpl::lddfa_pl();
1303 //ASI_SECONDARY
1304 0x81: FailUnimpl::lddfa_s();
1305 //ASI_SECONDARY_LITTLE
1306 0x89: FailUnimpl::lddfa_sl();
1307 //ASI_PRIMARY_NO_FAULT
1308 0x82: FailUnimpl::lddfa_pnf();
1309 //ASI_PRIMARY_NO_FAULT_LITTLE
1310 0x8A: FailUnimpl::lddfa_pnfl();
1311 //ASI_SECONDARY_NO_FAULT
1312 0x83: FailUnimpl::lddfa_snf();
1313 //ASI_SECONDARY_NO_FAULT_LITTLE
1314 0x8B: FailUnimpl::lddfa_snfl();
1315
1316 format BlockLoad {
1317 // LDBLOCKF
1318 //ASI_BLOCK_AS_IF_USER_PRIMARY
1319 0x16: FailUnimpl::ldblockf_aiup();
1320 //ASI_BLOCK_AS_IF_USER_SECONDARY
1321 0x17: FailUnimpl::ldblockf_aius();
1322 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1323 0x1E: FailUnimpl::ldblockf_aiupl();
1324 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1325 0x1F: FailUnimpl::ldblockf_aiusl();
1326 //ASI_BLOCK_PRIMARY
1327 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}});
1328 //ASI_BLOCK_SECONDARY
1329 0xF1: FailUnimpl::ldblockf_s();
1330 //ASI_BLOCK_PRIMARY_LITTLE
1331 0xF8: FailUnimpl::ldblockf_pl();
1332 //ASI_BLOCK_SECONDARY_LITTLE
1333 0xF9: FailUnimpl::ldblockf_sl();
1334 }
1335
1336 //LDSHORTF
1337 //ASI_FL8_PRIMARY
1338 0xD0: FailUnimpl::ldshortf_8p();
1339 //ASI_FL8_SECONDARY
1340 0xD1: FailUnimpl::ldshortf_8s();
1341 //ASI_FL8_PRIMARY_LITTLE
1342 0xD8: FailUnimpl::ldshortf_8pl();
1343 //ASI_FL8_SECONDARY_LITTLE
1344 0xD9: FailUnimpl::ldshortf_8sl();
1345 //ASI_FL16_PRIMARY
1346 0xD2: FailUnimpl::ldshortf_16p();
1347 //ASI_FL16_SECONDARY
1348 0xD3: FailUnimpl::ldshortf_16s();
1349 //ASI_FL16_PRIMARY_LITTLE
1350 0xDA: FailUnimpl::ldshortf_16pl();
1351 //ASI_FL16_SECONDARY_LITTLE
1352 0xDB: FailUnimpl::ldshortf_16sl();
1353 //Not an ASI which is legal with lddfa
1354 default: Trap::lddfa_bad_asi(
1355 {{fault = new DataAccessException;}});
1356 }
1357 }
1358 0x34: Store::stfa({{Mem.uw = Frds.uw;}});
1359 0x36: stqfa({{fault = new FpDisabled;}});
1360 format StoreAlt {
1361 0x37: decode EXT_ASI {
1362 //ASI_NUCLEUS
1363 0x04: FailUnimpl::stdfa_n();
1364 //ASI_NUCLEUS_LITTLE
1365 0x0C: FailUnimpl::stdfa_nl();
1366 //ASI_AS_IF_USER_PRIMARY
1367 0x10: FailUnimpl::stdfa_aiup();
1368 //ASI_AS_IF_USER_PRIMARY_LITTLE
1369 0x18: FailUnimpl::stdfa_aiupl();
1370 //ASI_AS_IF_USER_SECONDARY
1371 0x11: FailUnimpl::stdfa_aius();
1372 //ASI_AS_IF_USER_SECONDARY_LITTLE
1373 0x19: FailUnimpl::stdfa_aiusl();
1374 //ASI_REAL
1375 0x14: FailUnimpl::stdfa_real();
1376 //ASI_REAL_LITTLE
1377 0x1C: FailUnimpl::stdfa_real_l();
1378 //ASI_REAL_IO
1379 0x15: FailUnimpl::stdfa_real_io();
1380 //ASI_REAL_IO_LITTLE
1381 0x1D: FailUnimpl::stdfa_real_io_l();
1382 //ASI_PRIMARY
1383 0x80: FailUnimpl::stdfa_p();
1384 //ASI_PRIMARY_LITTLE
1385 0x88: FailUnimpl::stdfa_pl();
1386 //ASI_SECONDARY
1387 0x81: FailUnimpl::stdfa_s();
1388 //ASI_SECONDARY_LITTLE
1389 0x89: FailUnimpl::stdfa_sl();
1390 //ASI_PRIMARY_NO_FAULT
1391 0x82: FailUnimpl::stdfa_pnf();
1392 //ASI_PRIMARY_NO_FAULT_LITTLE
1393 0x8A: FailUnimpl::stdfa_pnfl();
1394 //ASI_SECONDARY_NO_FAULT
1395 0x83: FailUnimpl::stdfa_snf();
1396 //ASI_SECONDARY_NO_FAULT_LITTLE
1397 0x8B: FailUnimpl::stdfa_snfl();
1398
1399 format BlockStore {
1400 // STBLOCKF
1401 //ASI_BLOCK_AS_IF_USER_PRIMARY
1402 0x16: FailUnimpl::stblockf_aiup();
1403 //ASI_BLOCK_AS_IF_USER_SECONDARY
1404 0x17: FailUnimpl::stblockf_aius();
1405 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1406 0x1E: FailUnimpl::stblockf_aiupl();
1407 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1408 0x1F: FailUnimpl::stblockf_aiusl();
1409 //ASI_BLOCK_PRIMARY
1410 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}});
1411 //ASI_BLOCK_SECONDARY
1412 0xF1: FailUnimpl::stblockf_s();
1413 //ASI_BLOCK_PRIMARY_LITTLE
1414 0xF8: FailUnimpl::stblockf_pl();
1415 //ASI_BLOCK_SECONDARY_LITTLE
1416 0xF9: FailUnimpl::stblockf_sl();
1417 }
1418
1419 //STSHORTF
1420 //ASI_FL8_PRIMARY
1421 0xD0: FailUnimpl::stshortf_8p();
1422 //ASI_FL8_SECONDARY
1423 0xD1: FailUnimpl::stshortf_8s();
1424 //ASI_FL8_PRIMARY_LITTLE
1425 0xD8: FailUnimpl::stshortf_8pl();
1426 //ASI_FL8_SECONDARY_LITTLE
1427 0xD9: FailUnimpl::stshortf_8sl();
1428 //ASI_FL16_PRIMARY
1429 0xD2: FailUnimpl::stshortf_16p();
1430 //ASI_FL16_SECONDARY
1431 0xD3: FailUnimpl::stshortf_16s();
1432 //ASI_FL16_PRIMARY_LITTLE
1433 0xDA: FailUnimpl::stshortf_16pl();
1434 //ASI_FL16_SECONDARY_LITTLE
1435 0xDB: FailUnimpl::stshortf_16sl();
1436 //Not an ASI which is legal with lddfa
1437 default: Trap::stdfa_bad_asi(
1438 {{fault = new DataAccessException;}});
1439 }
1440 }
| 1274 format Trap {
1275 0x20: Load::ldf({{Frds.uw = Mem.uw;}});
1276 0x21: decode RD {
1277 0x0: Load::ldfsr({{fault = checkFpEnableFault(xc);
1278 if (fault)
1279 return fault;
1280 Fsr = Mem.uw | Fsr<63:32>;}});
1281 0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc);
1282 if (fault)
1283 return fault;
1284 Fsr = Mem.udw;}});
1285 default: FailUnimpl::ldfsrOther();
1286 }
1287 0x22: ldqf({{fault = new FpDisabled;}});
1288 0x23: Load::lddf({{Frd.udw = Mem.udw;}});
1289 0x24: Store::stf({{Mem.uw = Frds.uw;}});
1290 0x25: decode RD {
1291 0x0: Store::stfsr({{fault = checkFpEnableFault(xc);
1292 if (fault)
1293 return fault;
1294 Mem.uw = Fsr<31:0>;
1295 Fsr = insertBits(Fsr,16,14,0);}});
1296 0x1: Store::stxfsr({{fault = checkFpEnableFault(xc);
1297 if (fault)
1298 return fault;
1299 Mem.udw = Fsr;
1300 Fsr = insertBits(Fsr,16,14,0);}});
1301 default: FailUnimpl::stfsrOther();
1302 }
1303 0x26: stqf({{fault = new FpDisabled;}});
1304 0x27: Store::stdf({{Mem.udw = Frd.udw;}});
1305 0x2D: Nop::prefetch({{ }});
1306 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}});
1307 0x32: ldqfa({{fault = new FpDisabled;}});
1308 format LoadAlt {
1309 0x33: decode EXT_ASI {
1310 //ASI_NUCLEUS
1311 0x04: FailUnimpl::lddfa_n();
1312 //ASI_NUCLEUS_LITTLE
1313 0x0C: FailUnimpl::lddfa_nl();
1314 //ASI_AS_IF_USER_PRIMARY
1315 0x10: FailUnimpl::lddfa_aiup();
1316 //ASI_AS_IF_USER_PRIMARY_LITTLE
1317 0x18: FailUnimpl::lddfa_aiupl();
1318 //ASI_AS_IF_USER_SECONDARY
1319 0x11: FailUnimpl::lddfa_aius();
1320 //ASI_AS_IF_USER_SECONDARY_LITTLE
1321 0x19: FailUnimpl::lddfa_aiusl();
1322 //ASI_REAL
1323 0x14: FailUnimpl::lddfa_real();
1324 //ASI_REAL_LITTLE
1325 0x1C: FailUnimpl::lddfa_real_l();
1326 //ASI_REAL_IO
1327 0x15: FailUnimpl::lddfa_real_io();
1328 //ASI_REAL_IO_LITTLE
1329 0x1D: FailUnimpl::lddfa_real_io_l();
1330 //ASI_PRIMARY
1331 0x80: FailUnimpl::lddfa_p();
1332 //ASI_PRIMARY_LITTLE
1333 0x88: FailUnimpl::lddfa_pl();
1334 //ASI_SECONDARY
1335 0x81: FailUnimpl::lddfa_s();
1336 //ASI_SECONDARY_LITTLE
1337 0x89: FailUnimpl::lddfa_sl();
1338 //ASI_PRIMARY_NO_FAULT
1339 0x82: FailUnimpl::lddfa_pnf();
1340 //ASI_PRIMARY_NO_FAULT_LITTLE
1341 0x8A: FailUnimpl::lddfa_pnfl();
1342 //ASI_SECONDARY_NO_FAULT
1343 0x83: FailUnimpl::lddfa_snf();
1344 //ASI_SECONDARY_NO_FAULT_LITTLE
1345 0x8B: FailUnimpl::lddfa_snfl();
1346
1347 format BlockLoad {
1348 // LDBLOCKF
1349 //ASI_BLOCK_AS_IF_USER_PRIMARY
1350 0x16: FailUnimpl::ldblockf_aiup();
1351 //ASI_BLOCK_AS_IF_USER_SECONDARY
1352 0x17: FailUnimpl::ldblockf_aius();
1353 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1354 0x1E: FailUnimpl::ldblockf_aiupl();
1355 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1356 0x1F: FailUnimpl::ldblockf_aiusl();
1357 //ASI_BLOCK_PRIMARY
1358 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}});
1359 //ASI_BLOCK_SECONDARY
1360 0xF1: FailUnimpl::ldblockf_s();
1361 //ASI_BLOCK_PRIMARY_LITTLE
1362 0xF8: FailUnimpl::ldblockf_pl();
1363 //ASI_BLOCK_SECONDARY_LITTLE
1364 0xF9: FailUnimpl::ldblockf_sl();
1365 }
1366
1367 //LDSHORTF
1368 //ASI_FL8_PRIMARY
1369 0xD0: FailUnimpl::ldshortf_8p();
1370 //ASI_FL8_SECONDARY
1371 0xD1: FailUnimpl::ldshortf_8s();
1372 //ASI_FL8_PRIMARY_LITTLE
1373 0xD8: FailUnimpl::ldshortf_8pl();
1374 //ASI_FL8_SECONDARY_LITTLE
1375 0xD9: FailUnimpl::ldshortf_8sl();
1376 //ASI_FL16_PRIMARY
1377 0xD2: FailUnimpl::ldshortf_16p();
1378 //ASI_FL16_SECONDARY
1379 0xD3: FailUnimpl::ldshortf_16s();
1380 //ASI_FL16_PRIMARY_LITTLE
1381 0xDA: FailUnimpl::ldshortf_16pl();
1382 //ASI_FL16_SECONDARY_LITTLE
1383 0xDB: FailUnimpl::ldshortf_16sl();
1384 //Not an ASI which is legal with lddfa
1385 default: Trap::lddfa_bad_asi(
1386 {{fault = new DataAccessException;}});
1387 }
1388 }
1389 0x34: Store::stfa({{Mem.uw = Frds.uw;}});
1390 0x36: stqfa({{fault = new FpDisabled;}});
1391 format StoreAlt {
1392 0x37: decode EXT_ASI {
1393 //ASI_NUCLEUS
1394 0x04: FailUnimpl::stdfa_n();
1395 //ASI_NUCLEUS_LITTLE
1396 0x0C: FailUnimpl::stdfa_nl();
1397 //ASI_AS_IF_USER_PRIMARY
1398 0x10: FailUnimpl::stdfa_aiup();
1399 //ASI_AS_IF_USER_PRIMARY_LITTLE
1400 0x18: FailUnimpl::stdfa_aiupl();
1401 //ASI_AS_IF_USER_SECONDARY
1402 0x11: FailUnimpl::stdfa_aius();
1403 //ASI_AS_IF_USER_SECONDARY_LITTLE
1404 0x19: FailUnimpl::stdfa_aiusl();
1405 //ASI_REAL
1406 0x14: FailUnimpl::stdfa_real();
1407 //ASI_REAL_LITTLE
1408 0x1C: FailUnimpl::stdfa_real_l();
1409 //ASI_REAL_IO
1410 0x15: FailUnimpl::stdfa_real_io();
1411 //ASI_REAL_IO_LITTLE
1412 0x1D: FailUnimpl::stdfa_real_io_l();
1413 //ASI_PRIMARY
1414 0x80: FailUnimpl::stdfa_p();
1415 //ASI_PRIMARY_LITTLE
1416 0x88: FailUnimpl::stdfa_pl();
1417 //ASI_SECONDARY
1418 0x81: FailUnimpl::stdfa_s();
1419 //ASI_SECONDARY_LITTLE
1420 0x89: FailUnimpl::stdfa_sl();
1421 //ASI_PRIMARY_NO_FAULT
1422 0x82: FailUnimpl::stdfa_pnf();
1423 //ASI_PRIMARY_NO_FAULT_LITTLE
1424 0x8A: FailUnimpl::stdfa_pnfl();
1425 //ASI_SECONDARY_NO_FAULT
1426 0x83: FailUnimpl::stdfa_snf();
1427 //ASI_SECONDARY_NO_FAULT_LITTLE
1428 0x8B: FailUnimpl::stdfa_snfl();
1429
1430 format BlockStore {
1431 // STBLOCKF
1432 //ASI_BLOCK_AS_IF_USER_PRIMARY
1433 0x16: FailUnimpl::stblockf_aiup();
1434 //ASI_BLOCK_AS_IF_USER_SECONDARY
1435 0x17: FailUnimpl::stblockf_aius();
1436 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1437 0x1E: FailUnimpl::stblockf_aiupl();
1438 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1439 0x1F: FailUnimpl::stblockf_aiusl();
1440 //ASI_BLOCK_PRIMARY
1441 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}});
1442 //ASI_BLOCK_SECONDARY
1443 0xF1: FailUnimpl::stblockf_s();
1444 //ASI_BLOCK_PRIMARY_LITTLE
1445 0xF8: FailUnimpl::stblockf_pl();
1446 //ASI_BLOCK_SECONDARY_LITTLE
1447 0xF9: FailUnimpl::stblockf_sl();
1448 }
1449
1450 //STSHORTF
1451 //ASI_FL8_PRIMARY
1452 0xD0: FailUnimpl::stshortf_8p();
1453 //ASI_FL8_SECONDARY
1454 0xD1: FailUnimpl::stshortf_8s();
1455 //ASI_FL8_PRIMARY_LITTLE
1456 0xD8: FailUnimpl::stshortf_8pl();
1457 //ASI_FL8_SECONDARY_LITTLE
1458 0xD9: FailUnimpl::stshortf_8sl();
1459 //ASI_FL16_PRIMARY
1460 0xD2: FailUnimpl::stshortf_16p();
1461 //ASI_FL16_SECONDARY
1462 0xD3: FailUnimpl::stshortf_16s();
1463 //ASI_FL16_PRIMARY_LITTLE
1464 0xDA: FailUnimpl::stshortf_16pl();
1465 //ASI_FL16_SECONDARY_LITTLE
1466 0xDB: FailUnimpl::stshortf_16sl();
1467 //Not an ASI which is legal with lddfa
1468 default: Trap::stdfa_bad_asi(
1469 {{fault = new DataAccessException;}});
1470 }
1471 }
|
1441 0x3C: Cas::casa(
1442 {{uReg0 = Mem.uw;}},
1443 {{if(Rs2.uw == uReg0)
1444 Mem.uw = Rd.uw;
1445 else
1446 storeCond = false;
1447 Rd.uw = uReg0;}}, {{EXT_ASI}});
| 1472 0x3C: CasAlt::casa({{
1473 mem_data = htog(Rs2.uw);
1474 Mem.uw = Rd.uw;}},
1475 {{
1476 uint32_t tmp = mem_data;
1477 Rd.uw = tmp;
1478 }}, {{EXT_ASI}}, MEM_SWAP_COND);
|
1448 0x3D: Nop::prefetcha({{ }});
| 1479 0x3D: Nop::prefetcha({{ }});
|
1449 0x3E: Cas::casxa(
1450 {{uReg0 = Mem.udw;}},
1451 {{if(Rs2 == uReg0)
1452 Mem.udw = Rd;
1453 else
1454 storeCond = false;
1455 Rd = uReg0;}}, {{EXT_ASI}});
| 1480 0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2);
1481 Mem.udw = Rd.udw; }},
1482 {{ Rd.udw = mem_data; }}, {{EXT_ASI}}, MEM_SWAP_COND);
|
1456 }
1457 }
1458}
| 1483 }
1484 }
1485}
|