1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OP default Unknown::unknown()
37{
38 0x0: decode OP2
39 {
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 //bpcc
45 0x1: decode COND2
46 {
47 //Branch Always
48 0x8: decode A
49 {
50 0x0: bpa(19, {{
51 NNPC = xc->readPC() + disp;
52 }});
53 0x1: bpa(19, {{
54 NPC = xc->readPC() + disp;
55 NNPC = NPC + 4;
56 }}, ',a');
57 }
58 //Branch Never
59 0x0: decode A
60 {
61 0x0: bpn(19, {{
62 NNPC = NNPC;//Don't do anything
63 }});
64 0x1: bpn(19, {{
65 NPC = xc->readNextPC() + 4;
66 NNPC = NPC + 4;
67 }}, ',a');
68 }
69 default: decode BPCC
70 {
71 0x0: bpcci(19, {{
72 if(passesCondition(Ccr<3:0>, COND2))
73 NNPC = xc->readPC() + disp;
74 else
75 handle_annul
76 }});
77 0x2: bpccx(19, {{
78 if(passesCondition(Ccr<7:4>, COND2))
79 {
80 //warn("Took branch!\n");
81 NNPC = xc->readPC() + disp;
82 }
83 else
84 {
85 //warn("Didn't take branch!\n");
86 handle_annul
87 }
88 }});
89 }
90 }
91 //bicc
92 0x2: decode COND2
93 {
94 //Branch Always
95 0x8: decode A
96 {
97 0x0: ba(22, {{
98 NNPC = xc->readPC() + disp;
99 }});
100 0x1: ba(22, {{
101 NPC = xc->readPC() + disp;
102 NNPC = NPC + 4;
103 }}, ',a');
104 }
105 //Branch Never
106 0x0: decode A
107 {
108 0x0: bn(22, {{
109 NNPC = NNPC;//Don't do anything
110 }});
111 0x1: bn(22, {{
112 NPC = xc->readNextPC() + 4;
113 NNPC = NPC + 4;
114 }}, ',a');
115 }
116 default: bicc(22, {{
117 if(passesCondition(Ccr<3:0>, COND2))
118 NNPC = xc->readPC() + disp;
119 else
120 handle_annul
121 }});
122 }
123 }
124 0x3: decode RCOND2
125 {
126 format BranchSplit
127 {
128 0x1: bpreq({{
129 if(Rs1.sdw == 0)
130 NNPC = xc->readPC() + disp;
131 else
132 handle_annul
133 }});
134 0x2: bprle({{
135 if(Rs1.sdw <= 0)
136 NNPC = xc->readPC() + disp;
137 else
138 handle_annul
139 }});
140 0x3: bprl({{
141 if(Rs1.sdw < 0)
142 NNPC = xc->readPC() + disp;
143 else
144 handle_annul
145 }});
146 0x5: bprne({{
147 if(Rs1.sdw != 0)
148 NNPC = xc->readPC() + disp;
149 else
150 handle_annul
151 }});
152 0x6: bprg({{
153 if(Rs1.sdw > 0)
154 NNPC = xc->readPC() + disp;
155 else
156 handle_annul
157 }});
158 0x7: bprge({{
159 if(Rs1.sdw >= 0)
160 NNPC = xc->readPC() + disp;
161 else
162 handle_annul
163 }});
164 }
165 }
166 //SETHI (or NOP if rd == 0 and imm == 0)
167 0x4: SetHi::sethi({{Rd.udw = imm;}});
168 0x5: FailUnimpl::fbpfcc();
169 0x6: FailUnimpl::fbfcc();
170 }
171 0x1: BranchN::call(30, {{
172 if (Pstate<3:>)
173 R15 = (xc->readPC())<31:0>;
174 else
175 R15 = xc->readPC();
176 NNPC = R15 + disp;
177 }});
178 0x2: decode OP3 {
179 format IntOp {
180 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
181 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
182 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
183 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
184 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
185 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}});
186 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}});
187 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
188 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
189 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
190 0x0A: umul({{
191 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
192 Y = Rd<63:32>;
193 }});
194 0x0B: smul({{
195 Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
196 Y = Rd.sdw<63:32>;
197 }});
198 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
199 0x0D: udivx({{
200 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
201 else Rd.udw = Rs1.udw / Rs2_or_imm13;
202 }});
203 0x0E: udiv({{
204 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
205 else
206 {
207 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
208 if(Rd.udw >> 32 != 0)
209 Rd.udw = 0xFFFFFFFF;
210 }
211 }});
212 0x0F: sdiv({{
213 if(Rs2_or_imm13.sdw == 0)
214 fault = new DivisionByZero;
215 else
216 {
217 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
218 if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max())
219 Rd.udw = 0x7FFFFFFF;
220 else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min())
221 Rd.udw = ULL(0xFFFFFFFF80000000);
222 }
223 }});
224 }
225 format IntOpCc {
226 0x10: addcc({{
227 int64_t resTemp, val2 = Rs2_or_imm13;
228 Rd = resTemp = Rs1 + val2;}},
229 {{(Rs1<31:0> + val2<31:0>)<32:>}},
230 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
231 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
232 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
233 );
234 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
235 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
236 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
237 0x14: subcc({{
238 int64_t val2 = Rs2_or_imm13;
239 Rd = Rs1 - val2;}},
240 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
241 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
242 {{(~(Rs1<63:1> + (~val2)<63:1> +
243 (Rs1 | ~val2)<0:>))<63:>}},
244 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
245 );
246 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
247 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
248 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
249 0x18: addccc({{
250 int64_t resTemp, val2 = Rs2_or_imm13;
251 int64_t carryin = Ccr<0:0>;
252 Rd = resTemp = Rs1 + val2 + carryin;}},
253 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
254 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
255 {{((Rs1 & val2) | (~resTemp & (Rs1 | val2)))<63:>}},
256 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
257 );
258 0x1A: IntOpCcRes::umulcc({{
259 uint64_t resTemp;
260 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
261 Y = resTemp<63:32>;}});
262 0x1B: IntOpCcRes::smulcc({{
263 int64_t resTemp;
264 Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
265 Y = resTemp<63:32>;}});
266 0x1C: subccc({{
267 int64_t resTemp, val2 = Rs2_or_imm13;
268 int64_t carryin = Ccr<0:0>;
269 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
270 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<31:>}},
271 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
272 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<63:>}},
273 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
274 );
275 0x1D: IntOpCcRes::udivxcc({{
276 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
277 else Rd = Rs1.udw / Rs2_or_imm13.udw;}});
278 0x1E: udivcc({{
279 uint32_t resTemp, val2 = Rs2_or_imm13.udw;
280 int32_t overflow = 0;
281 if(val2 == 0) fault = new DivisionByZero;
282 else
283 {
284 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
285 overflow = (resTemp<63:32> != 0);
286 if(overflow) Rd = resTemp = 0xFFFFFFFF;
287 else Rd = resTemp;
288 } }},
289 {{0}},
290 {{overflow}},
291 {{0}},
292 {{0}}
293 );
294 0x1F: sdivcc({{
295 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
296 bool overflow = false, underflow = false;
297 if(val2 == 0) fault = new DivisionByZero;
298 else
299 {
300 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
301 overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max());
302 underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min());
303 if(overflow) Rd = 0x7FFFFFFF;
304 else if(underflow) Rd = ULL(0xFFFFFFFF80000000);
305 } }},
306 {{0}},
307 {{overflow || underflow}},
308 {{0}},
309 {{0}}
310 );
311 0x20: taddcc({{
312 int64_t resTemp, val2 = Rs2_or_imm13;
313 Rd = resTemp = Rs1 + val2;
314 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
315 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
316 {{overflow}},
317 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
318 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
319 );
320 0x21: tsubcc({{
321 int64_t resTemp, val2 = Rs2_or_imm13;
322 Rd = resTemp = Rs1 + val2;
323 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
324 {{(Rs1<31:0> + val2<31:0>)<32:0>}},
325 {{overflow}},
326 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
327 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
328 );
329 0x22: taddcctv({{
330 int64_t val2 = Rs2_or_imm13;
331 Rd = Rs1 + val2;
332 int32_t overflow = Rs1<1:0> || val2<1:0> ||
333 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
334 if(overflow) fault = new TagOverflow;}},
335 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
336 {{overflow}},
337 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
338 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}}
339 );
340 0x23: tsubcctv({{
341 int64_t resTemp, val2 = Rs2_or_imm13;
342 Rd = resTemp = Rs1 + val2;
343 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
344 if(overflow) fault = new TagOverflow;}},
345 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
346 {{overflow}},
347 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
348 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
349 );
350 0x24: mulscc({{
351 int64_t resTemp, multiplicand = Rs2_or_imm13;
352 int32_t multiplier = Rs1<31:0>;
353 int32_t savedLSB = Rs1<0:>;
354 multiplier = multiplier<31:1> |
355 ((Ccr<3:3> ^ Ccr<1:1>) << 32);
356 if(!Y<0:>)
357 multiplicand = 0;
358 Rd = resTemp = multiplicand + multiplier;
359 Y = Y<31:1> | (savedLSB << 31);}},
360 {{((multiplicand<31:0> + multiplier<31:0>)<32:0>)}},
361 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
362 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
363 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
364 );
365 }
366 format IntOp
367 {
368 0x25: decode X {
369 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
370 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
371 }
372 0x26: decode X {
373 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
374 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
375 }
376 0x27: decode X {
377 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
378 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
379 }
380 0x28: decode RS1 {
381 0x00: NoPriv::rdy({{Rd = Y<31:0>;}});
382 //1 should cause an illegal instruction exception
383 0x02: NoPriv::rdccr({{Rd = Ccr;}});
384 0x03: NoPriv::rdasi({{Rd = Asi;}});
385 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
386 0x05: NoPriv::rdpc({{
387 if(Pstate<3:>)
388 Rd = (xc->readPC())<31:0>;
389 else
390 Rd = xc->readPC();}});
391 0x06: NoPriv::rdfprs({{
392 //Wait for all fpops to finish.
393 Rd = Fprs;
394 }});
395 //7-14 should cause an illegal instruction exception
396 0x0F: decode I {
397 0x0: Nop::stbar({{/*stuff*/}});
398 0x1: Nop::membar({{/*stuff*/}});
399 }
400 0x10: Priv::rdpcr({{Rd = Pcr;}});
401 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
402 //0x12 should cause an illegal instruction exception
403 0x13: NoPriv::rdgsr({{
404 if(Fprs<2:> == 0 || Pstate<4:> == 0)
405 Rd = Gsr;
406 else
407 fault = new FpDisabled;
408 }});
409 //0x14-0x15 should cause an illegal instruction exception
410 0x16: Priv::rdsoftint({{Rd = Softint;}});
411 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
412 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}});
413 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
414 0x1A: Priv::rdstrand_sts_reg({{
415 if(Pstate<2:> && !Hpstate<2:>)
416 Rd = StrandStsReg<0:>;
417 else
418 Rd = StrandStsReg;
419 }});
420 //0x1A is supposed to be reserved, but it reads the strand
421 //status register.
422 //0x1B-0x1F should cause an illegal instruction exception
423 }
424 0x29: decode RS1 {
425 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
426 0x01: HPriv::rdhprhtstate({{
427 if(Tl == 0)
428 return new IllegalInstruction;
429 Rd = Htstate;
430 }});
431 //0x02 should cause an illegal instruction exception
432 0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
433 //0x04 should cause an illegal instruction exception
434 0x05: HPriv::rdhprhtba({{Rd = Htba;}});
435 0x06: HPriv::rdhprhver({{Rd = Hver;}});
436 //0x07-0x1E should cause an illegal instruction exception
437 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
438 }
439 0x2A: decode RS1 {
440 0x00: Priv::rdprtpc({{
441 if(Tl == 0)
442 return new IllegalInstruction;
443 Rd = Tpc;
444 }});
445 0x01: Priv::rdprtnpc({{
446 if(Tl == 0)
447 return new IllegalInstruction;
448 Rd = Tnpc;
449 }});
450 0x02: Priv::rdprtstate({{
451 if(Tl == 0)
452 return new IllegalInstruction;
453 Rd = Tstate;
454 }});
455 0x03: Priv::rdprtt({{
456 if(Tl == 0)
457 return new IllegalInstruction;
458 Rd = Tt;
459 }});
460 0x04: Priv::rdprtick({{Rd = Tick;}});
461 0x05: Priv::rdprtba({{Rd = Tba;}});
462 0x06: Priv::rdprpstate({{Rd = Pstate;}});
463 0x07: Priv::rdprtl({{Rd = Tl;}});
464 0x08: Priv::rdprpil({{Rd = Pil;}});
465 0x09: Priv::rdprcwp({{Rd = Cwp;}});
466 0x0A: Priv::rdprcansave({{Rd = Cansave;}});
467 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});
468 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});
469 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}});
470 0x0E: Priv::rdprwstate({{Rd = Wstate;}});
471 //0x0F should cause an illegal instruction exception
472 0x10: Priv::rdprgl({{Rd = Gl;}});
473 //0x11-0x1F should cause an illegal instruction exception
474 }
475 0x2B: BasicOperate::flushw({{
476 if(NWindows - 2 - Cansave != 0)
477 {
478 if(Otherwin)
479 fault = new SpillNOther(4*Wstate<5:3>);
480 else
481 fault = new SpillNNormal(4*Wstate<2:0>);
482 }
483 }});
484 0x2C: decode MOVCC3
485 {
486 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
487 0x1: decode CC
488 {
489 0x0: movcci({{
490 if(passesCondition(Ccr<3:0>, COND4))
491 Rd = Rs2_or_imm11;
492 else
493 Rd = Rd;
494 }});
495 0x2: movccx({{
496 if(passesCondition(Ccr<7:4>, COND4))
497 Rd = Rs2_or_imm11;
498 else
499 Rd = Rd;
500 }});
501 }
502 }
503 0x2D: sdivx({{
504 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
505 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
506 }});
507 0x2E: Trap::popc({{fault = new IllegalInstruction;}});
508 0x2F: decode RCOND3
509 {
510 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
511 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
512 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
513 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
514 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
515 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
516 }
517 0x30: decode RD {
518 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}});
519 //0x01 should cause an illegal instruction exception
520 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
521 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
522 //0x04-0x05 should cause an illegal instruction exception
523 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
524 //0x07-0x0E should cause an illegal instruction exception
525 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
526 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
527 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
528 //0x12 should cause an illegal instruction exception
529 0x13: NoPriv::wrgsr({{
530 if(Fprs<2:> == 0 || Pstate<4:> == 0)
531 return new FpDisabled;
532 Gsr = Rs1 ^ Rs2_or_imm13;
533 }});
534 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
535 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});
536 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
537 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}});
538 0x18: NoPriv::wrstick({{
539 if(!Hpstate<2:>)
540 return new IllegalInstruction;
541 Stick = Rs1 ^ Rs2_or_imm13;
542 }});
543 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}});
544 0x1A: Priv::wrstrand_sts_reg({{
545 if(Pstate<2:> && !Hpstate<2:>)
546 StrandStsReg = StrandStsReg<63:1> |
547 (Rs1 ^ Rs2_or_imm13)<0:>;
548 else
549 StrandStsReg = Rs1 ^ Rs2_or_imm13;
550 }});
551 //0x1A is supposed to be reserved, but it writes the strand
552 //status register.
553 //0x1B-0x1F should cause an illegal instruction exception
554 }
555 0x31: decode FCN {
556 0x0: Priv::saved({{
557 assert(Cansave < NWindows - 2);
558 assert(Otherwin || Canrestore);
559 Cansave = Cansave + 1;
560 if(Otherwin == 0)
561 Canrestore = Canrestore - 1;
562 else
563 Otherwin = Otherwin - 1;
564 }});
565 0x1: Priv::restored({{
566 assert(Cansave || Otherwin);
567 assert(Canrestore < NWindows - 2);
568 Canrestore = Canrestore + 1;
569 if(Otherwin == 0)
570 Cansave = Cansave - 1;
571 else
572 Otherwin = Otherwin - 1;
573
574 if(Cleanwin < NWindows - 1)
575 Cleanwin = Cleanwin + 1;
576 }});
577 }
578 0x32: decode RD {
579 0x00: Priv::wrprtpc({{
580 if(Tl == 0)
581 return new IllegalInstruction;
582 else
583 Tpc = Rs1 ^ Rs2_or_imm13;
584 }});
585 0x01: Priv::wrprtnpc({{
586 if(Tl == 0)
587 return new IllegalInstruction;
588 else
589 Tnpc = Rs1 ^ Rs2_or_imm13;
590 }});
591 0x02: Priv::wrprtstate({{
592 if(Tl == 0)
593 return new IllegalInstruction;
594 else
595 Tstate = Rs1 ^ Rs2_or_imm13;
596 }});
597 0x03: Priv::wrprtt({{
598 if(Tl == 0)
599 return new IllegalInstruction;
600 else
601 Tt = Rs1 ^ Rs2_or_imm13;
602 }});
603 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
604 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
605 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
606 0x07: Priv::wrprtl({{
607 if(Pstate<2:> && !Hpstate<2:>)
608 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
609 else
610 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);
611 }});
612 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
613 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
614 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
615 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
616 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
617 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
618 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
619 //0x0F should cause an illegal instruction exception
620 0x10: Priv::wrprgl({{
621 if(Pstate<2:> && !Hpstate<2:>)
622 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL);
623 else
624 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
625 }});
626 //0x11-0x1F should cause an illegal instruction exception
627 }
628 0x33: decode RD {
629 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
630 0x01: HPriv::wrhprhtstate({{
631 if(Tl == 0)
632 return new IllegalInstruction;
633 Htstate = Rs1 ^ Rs2_or_imm13;
634 }});
635 //0x02 should cause an illegal instruction exception
636 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
637 //0x04 should cause an illegal instruction exception
638 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
639 //0x06-0x01D should cause an illegal instruction exception
640 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
641 }
642 0x34: decode OPF{
643 format BasicOperate{
644 0x01: fmovs({{
645 Frds.uw = Frs2s.uw;
646 //fsr.ftt = fsr.cexc = 0
647 Fsr &= ~(7 << 14);
648 Fsr &= ~(0x1F);
649 }});
650 0x02: fmovd({{
651 Frd.udw = Frs2.udw;
652 //fsr.ftt = fsr.cexc = 0
653 Fsr &= ~(7 << 14);
654 Fsr &= ~(0x1F);
655 }});
656 0x03: Trap::fmovq({{fault = new FpExceptionOther;}}); //unimp fpop
657 0x05: fnegs({{
658 Frds.uw = Frs2s.uw ^ (1UL << 31);
659 //fsr.ftt = fsr.cexc = 0
660 Fsr &= ~(7 << 14);
661 Fsr &= ~(0x1F);
662 }});
663 0x06: fnegd({{
664 Frd.udw = Frs2.udw ^ (1ULL << 63);
665 //fsr.ftt = fsr.cexc = 0
666 Fsr &= ~(7 << 14);
667 Fsr &= ~(0x1F);
668 }});
669 0x07: Trap::fnegq({{fault = new FpExceptionOther;}}); //fpop unimp
670 0x09: fabss({{
671 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;
672 //fsr.ftt = fsr.cexc = 0
673 Fsr &= ~(7 << 14);
674 Fsr &= ~(0x1F);
675 }});
676 0x0A: fabsd({{
677 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;
678 //fsr.ftt = fsr.cexc = 0
679 Fsr &= ~(7 << 14);
680 Fsr &= ~(0x1F);
681 }});
682 0x0B: Trap::fabsq({{fault = new FpExceptionOther;}}); //fpop unimp
683 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}});
684 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}});
685 0x2B: Trap::fsqrtq({{fault = new FpExceptionOther;}}); //unimp fpop
686 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
687 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
688 0x43: Trap::faddq({{fault = new FpExceptionOther;}}); //unimp fpop
689 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
690 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
691 0x47: Trap::fsubq({{fault = new FpExceptionOther;}}); //unimp fpop
692 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
693 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
694 0x4B: Trap::fmulq({{fault = new FpExceptionOther;}}); //unimp fpop
695 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
696 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
697 0x4F: Trap::fdivq({{fault = new FpExceptionOther;}}); //unimp fpop
698 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
699 0x6E: Trap::fdmulq({{fault = new FpExceptionOther;}}); //unimp fpop
700 0x81: fstox({{
701 Frd.df = (double)static_cast<int64_t>(Frs2s.sf);
702 }});
703 0x82: fdtox({{
704 Frd.df = (double)static_cast<int64_t>(Frs2.df);
705 }});
706 0x83: Trap::fqtox({{fault = new FpExceptionOther;}}); //unimp fpop
707 0x84: fxtos({{
708 Frds.sf = static_cast<float>((int64_t)Frs2.df);
709 }});
710 0x88: fxtod({{
711 Frd.df = static_cast<double>((int64_t)Frs2.df);
712 }});
713 0x8C: Trap::fxtoq({{fault = new FpExceptionOther;}}); //unimp fpop
714 0xC4: fitos({{
715 Frds.sf = static_cast<float>((int32_t)Frs2s.sf);
716 }});
717 0xC6: fdtos({{Frds.sf = Frs2.df;}});
718 0xC7: Trap::fqtos({{fault = new FpExceptionOther;}}); //unimp fpop
719 0xC8: fitod({{
720 Frd.df = static_cast<double>((int32_t)Frs2s.sf);
721 }});
722 0xC9: fstod({{Frd.df = Frs2s.sf;}});
723 0xCB: Trap::fqtod({{fault = new FpExceptionOther;}}); // unimp fpop
724 0xCC: Trap::fitoq({{fault = new FpExceptionOther;}}); // unimp fpop
725 0xCD: Trap::fstoq({{fault = new FpExceptionOther;}}); // unimp fpop
726 0xCE: Trap::fdtoq({{fault = new FpExceptionOther;}}); // unimp fpop
727 0xD1: fstoi({{
728 Frds.sf = (float)static_cast<int32_t>(Frs2s.sf);
729 }});
730 0xD2: fdtoi({{
731 Frds.sf = (float)static_cast<int32_t>(Frs2.df);
732 }});
733 0xD3: Trap::fqtoi({{fault = new FpExceptionOther;}}); // unimp fpop
734 default: FailUnimpl::fpop1();
735 }
736 }
| 1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OP default Unknown::unknown()
37{
38 0x0: decode OP2
39 {
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 //bpcc
45 0x1: decode COND2
46 {
47 //Branch Always
48 0x8: decode A
49 {
50 0x0: bpa(19, {{
51 NNPC = xc->readPC() + disp;
52 }});
53 0x1: bpa(19, {{
54 NPC = xc->readPC() + disp;
55 NNPC = NPC + 4;
56 }}, ',a');
57 }
58 //Branch Never
59 0x0: decode A
60 {
61 0x0: bpn(19, {{
62 NNPC = NNPC;//Don't do anything
63 }});
64 0x1: bpn(19, {{
65 NPC = xc->readNextPC() + 4;
66 NNPC = NPC + 4;
67 }}, ',a');
68 }
69 default: decode BPCC
70 {
71 0x0: bpcci(19, {{
72 if(passesCondition(Ccr<3:0>, COND2))
73 NNPC = xc->readPC() + disp;
74 else
75 handle_annul
76 }});
77 0x2: bpccx(19, {{
78 if(passesCondition(Ccr<7:4>, COND2))
79 {
80 //warn("Took branch!\n");
81 NNPC = xc->readPC() + disp;
82 }
83 else
84 {
85 //warn("Didn't take branch!\n");
86 handle_annul
87 }
88 }});
89 }
90 }
91 //bicc
92 0x2: decode COND2
93 {
94 //Branch Always
95 0x8: decode A
96 {
97 0x0: ba(22, {{
98 NNPC = xc->readPC() + disp;
99 }});
100 0x1: ba(22, {{
101 NPC = xc->readPC() + disp;
102 NNPC = NPC + 4;
103 }}, ',a');
104 }
105 //Branch Never
106 0x0: decode A
107 {
108 0x0: bn(22, {{
109 NNPC = NNPC;//Don't do anything
110 }});
111 0x1: bn(22, {{
112 NPC = xc->readNextPC() + 4;
113 NNPC = NPC + 4;
114 }}, ',a');
115 }
116 default: bicc(22, {{
117 if(passesCondition(Ccr<3:0>, COND2))
118 NNPC = xc->readPC() + disp;
119 else
120 handle_annul
121 }});
122 }
123 }
124 0x3: decode RCOND2
125 {
126 format BranchSplit
127 {
128 0x1: bpreq({{
129 if(Rs1.sdw == 0)
130 NNPC = xc->readPC() + disp;
131 else
132 handle_annul
133 }});
134 0x2: bprle({{
135 if(Rs1.sdw <= 0)
136 NNPC = xc->readPC() + disp;
137 else
138 handle_annul
139 }});
140 0x3: bprl({{
141 if(Rs1.sdw < 0)
142 NNPC = xc->readPC() + disp;
143 else
144 handle_annul
145 }});
146 0x5: bprne({{
147 if(Rs1.sdw != 0)
148 NNPC = xc->readPC() + disp;
149 else
150 handle_annul
151 }});
152 0x6: bprg({{
153 if(Rs1.sdw > 0)
154 NNPC = xc->readPC() + disp;
155 else
156 handle_annul
157 }});
158 0x7: bprge({{
159 if(Rs1.sdw >= 0)
160 NNPC = xc->readPC() + disp;
161 else
162 handle_annul
163 }});
164 }
165 }
166 //SETHI (or NOP if rd == 0 and imm == 0)
167 0x4: SetHi::sethi({{Rd.udw = imm;}});
168 0x5: FailUnimpl::fbpfcc();
169 0x6: FailUnimpl::fbfcc();
170 }
171 0x1: BranchN::call(30, {{
172 if (Pstate<3:>)
173 R15 = (xc->readPC())<31:0>;
174 else
175 R15 = xc->readPC();
176 NNPC = R15 + disp;
177 }});
178 0x2: decode OP3 {
179 format IntOp {
180 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
181 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
182 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
183 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
184 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
185 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}});
186 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}});
187 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
188 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
189 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
190 0x0A: umul({{
191 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
192 Y = Rd<63:32>;
193 }});
194 0x0B: smul({{
195 Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
196 Y = Rd.sdw<63:32>;
197 }});
198 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
199 0x0D: udivx({{
200 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
201 else Rd.udw = Rs1.udw / Rs2_or_imm13;
202 }});
203 0x0E: udiv({{
204 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
205 else
206 {
207 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
208 if(Rd.udw >> 32 != 0)
209 Rd.udw = 0xFFFFFFFF;
210 }
211 }});
212 0x0F: sdiv({{
213 if(Rs2_or_imm13.sdw == 0)
214 fault = new DivisionByZero;
215 else
216 {
217 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
218 if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max())
219 Rd.udw = 0x7FFFFFFF;
220 else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min())
221 Rd.udw = ULL(0xFFFFFFFF80000000);
222 }
223 }});
224 }
225 format IntOpCc {
226 0x10: addcc({{
227 int64_t resTemp, val2 = Rs2_or_imm13;
228 Rd = resTemp = Rs1 + val2;}},
229 {{(Rs1<31:0> + val2<31:0>)<32:>}},
230 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
231 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
232 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
233 );
234 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
235 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
236 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
237 0x14: subcc({{
238 int64_t val2 = Rs2_or_imm13;
239 Rd = Rs1 - val2;}},
240 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
241 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
242 {{(~(Rs1<63:1> + (~val2)<63:1> +
243 (Rs1 | ~val2)<0:>))<63:>}},
244 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
245 );
246 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
247 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
248 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
249 0x18: addccc({{
250 int64_t resTemp, val2 = Rs2_or_imm13;
251 int64_t carryin = Ccr<0:0>;
252 Rd = resTemp = Rs1 + val2 + carryin;}},
253 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
254 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
255 {{((Rs1 & val2) | (~resTemp & (Rs1 | val2)))<63:>}},
256 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
257 );
258 0x1A: IntOpCcRes::umulcc({{
259 uint64_t resTemp;
260 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
261 Y = resTemp<63:32>;}});
262 0x1B: IntOpCcRes::smulcc({{
263 int64_t resTemp;
264 Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
265 Y = resTemp<63:32>;}});
266 0x1C: subccc({{
267 int64_t resTemp, val2 = Rs2_or_imm13;
268 int64_t carryin = Ccr<0:0>;
269 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
270 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<31:>}},
271 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
272 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<63:>}},
273 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
274 );
275 0x1D: IntOpCcRes::udivxcc({{
276 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
277 else Rd = Rs1.udw / Rs2_or_imm13.udw;}});
278 0x1E: udivcc({{
279 uint32_t resTemp, val2 = Rs2_or_imm13.udw;
280 int32_t overflow = 0;
281 if(val2 == 0) fault = new DivisionByZero;
282 else
283 {
284 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
285 overflow = (resTemp<63:32> != 0);
286 if(overflow) Rd = resTemp = 0xFFFFFFFF;
287 else Rd = resTemp;
288 } }},
289 {{0}},
290 {{overflow}},
291 {{0}},
292 {{0}}
293 );
294 0x1F: sdivcc({{
295 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
296 bool overflow = false, underflow = false;
297 if(val2 == 0) fault = new DivisionByZero;
298 else
299 {
300 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
301 overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max());
302 underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min());
303 if(overflow) Rd = 0x7FFFFFFF;
304 else if(underflow) Rd = ULL(0xFFFFFFFF80000000);
305 } }},
306 {{0}},
307 {{overflow || underflow}},
308 {{0}},
309 {{0}}
310 );
311 0x20: taddcc({{
312 int64_t resTemp, val2 = Rs2_or_imm13;
313 Rd = resTemp = Rs1 + val2;
314 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
315 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
316 {{overflow}},
317 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
318 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
319 );
320 0x21: tsubcc({{
321 int64_t resTemp, val2 = Rs2_or_imm13;
322 Rd = resTemp = Rs1 + val2;
323 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
324 {{(Rs1<31:0> + val2<31:0>)<32:0>}},
325 {{overflow}},
326 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
327 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
328 );
329 0x22: taddcctv({{
330 int64_t val2 = Rs2_or_imm13;
331 Rd = Rs1 + val2;
332 int32_t overflow = Rs1<1:0> || val2<1:0> ||
333 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
334 if(overflow) fault = new TagOverflow;}},
335 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
336 {{overflow}},
337 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
338 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}}
339 );
340 0x23: tsubcctv({{
341 int64_t resTemp, val2 = Rs2_or_imm13;
342 Rd = resTemp = Rs1 + val2;
343 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
344 if(overflow) fault = new TagOverflow;}},
345 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
346 {{overflow}},
347 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
348 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
349 );
350 0x24: mulscc({{
351 int64_t resTemp, multiplicand = Rs2_or_imm13;
352 int32_t multiplier = Rs1<31:0>;
353 int32_t savedLSB = Rs1<0:>;
354 multiplier = multiplier<31:1> |
355 ((Ccr<3:3> ^ Ccr<1:1>) << 32);
356 if(!Y<0:>)
357 multiplicand = 0;
358 Rd = resTemp = multiplicand + multiplier;
359 Y = Y<31:1> | (savedLSB << 31);}},
360 {{((multiplicand<31:0> + multiplier<31:0>)<32:0>)}},
361 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
362 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
363 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
364 );
365 }
366 format IntOp
367 {
368 0x25: decode X {
369 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
370 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
371 }
372 0x26: decode X {
373 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
374 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
375 }
376 0x27: decode X {
377 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
378 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
379 }
380 0x28: decode RS1 {
381 0x00: NoPriv::rdy({{Rd = Y<31:0>;}});
382 //1 should cause an illegal instruction exception
383 0x02: NoPriv::rdccr({{Rd = Ccr;}});
384 0x03: NoPriv::rdasi({{Rd = Asi;}});
385 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
386 0x05: NoPriv::rdpc({{
387 if(Pstate<3:>)
388 Rd = (xc->readPC())<31:0>;
389 else
390 Rd = xc->readPC();}});
391 0x06: NoPriv::rdfprs({{
392 //Wait for all fpops to finish.
393 Rd = Fprs;
394 }});
395 //7-14 should cause an illegal instruction exception
396 0x0F: decode I {
397 0x0: Nop::stbar({{/*stuff*/}});
398 0x1: Nop::membar({{/*stuff*/}});
399 }
400 0x10: Priv::rdpcr({{Rd = Pcr;}});
401 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
402 //0x12 should cause an illegal instruction exception
403 0x13: NoPriv::rdgsr({{
404 if(Fprs<2:> == 0 || Pstate<4:> == 0)
405 Rd = Gsr;
406 else
407 fault = new FpDisabled;
408 }});
409 //0x14-0x15 should cause an illegal instruction exception
410 0x16: Priv::rdsoftint({{Rd = Softint;}});
411 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
412 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}});
413 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
414 0x1A: Priv::rdstrand_sts_reg({{
415 if(Pstate<2:> && !Hpstate<2:>)
416 Rd = StrandStsReg<0:>;
417 else
418 Rd = StrandStsReg;
419 }});
420 //0x1A is supposed to be reserved, but it reads the strand
421 //status register.
422 //0x1B-0x1F should cause an illegal instruction exception
423 }
424 0x29: decode RS1 {
425 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
426 0x01: HPriv::rdhprhtstate({{
427 if(Tl == 0)
428 return new IllegalInstruction;
429 Rd = Htstate;
430 }});
431 //0x02 should cause an illegal instruction exception
432 0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
433 //0x04 should cause an illegal instruction exception
434 0x05: HPriv::rdhprhtba({{Rd = Htba;}});
435 0x06: HPriv::rdhprhver({{Rd = Hver;}});
436 //0x07-0x1E should cause an illegal instruction exception
437 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
438 }
439 0x2A: decode RS1 {
440 0x00: Priv::rdprtpc({{
441 if(Tl == 0)
442 return new IllegalInstruction;
443 Rd = Tpc;
444 }});
445 0x01: Priv::rdprtnpc({{
446 if(Tl == 0)
447 return new IllegalInstruction;
448 Rd = Tnpc;
449 }});
450 0x02: Priv::rdprtstate({{
451 if(Tl == 0)
452 return new IllegalInstruction;
453 Rd = Tstate;
454 }});
455 0x03: Priv::rdprtt({{
456 if(Tl == 0)
457 return new IllegalInstruction;
458 Rd = Tt;
459 }});
460 0x04: Priv::rdprtick({{Rd = Tick;}});
461 0x05: Priv::rdprtba({{Rd = Tba;}});
462 0x06: Priv::rdprpstate({{Rd = Pstate;}});
463 0x07: Priv::rdprtl({{Rd = Tl;}});
464 0x08: Priv::rdprpil({{Rd = Pil;}});
465 0x09: Priv::rdprcwp({{Rd = Cwp;}});
466 0x0A: Priv::rdprcansave({{Rd = Cansave;}});
467 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});
468 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});
469 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}});
470 0x0E: Priv::rdprwstate({{Rd = Wstate;}});
471 //0x0F should cause an illegal instruction exception
472 0x10: Priv::rdprgl({{Rd = Gl;}});
473 //0x11-0x1F should cause an illegal instruction exception
474 }
475 0x2B: BasicOperate::flushw({{
476 if(NWindows - 2 - Cansave != 0)
477 {
478 if(Otherwin)
479 fault = new SpillNOther(4*Wstate<5:3>);
480 else
481 fault = new SpillNNormal(4*Wstate<2:0>);
482 }
483 }});
484 0x2C: decode MOVCC3
485 {
486 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
487 0x1: decode CC
488 {
489 0x0: movcci({{
490 if(passesCondition(Ccr<3:0>, COND4))
491 Rd = Rs2_or_imm11;
492 else
493 Rd = Rd;
494 }});
495 0x2: movccx({{
496 if(passesCondition(Ccr<7:4>, COND4))
497 Rd = Rs2_or_imm11;
498 else
499 Rd = Rd;
500 }});
501 }
502 }
503 0x2D: sdivx({{
504 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
505 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
506 }});
507 0x2E: Trap::popc({{fault = new IllegalInstruction;}});
508 0x2F: decode RCOND3
509 {
510 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
511 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
512 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
513 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
514 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
515 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
516 }
517 0x30: decode RD {
518 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}});
519 //0x01 should cause an illegal instruction exception
520 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
521 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
522 //0x04-0x05 should cause an illegal instruction exception
523 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
524 //0x07-0x0E should cause an illegal instruction exception
525 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
526 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
527 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
528 //0x12 should cause an illegal instruction exception
529 0x13: NoPriv::wrgsr({{
530 if(Fprs<2:> == 0 || Pstate<4:> == 0)
531 return new FpDisabled;
532 Gsr = Rs1 ^ Rs2_or_imm13;
533 }});
534 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
535 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});
536 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
537 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}});
538 0x18: NoPriv::wrstick({{
539 if(!Hpstate<2:>)
540 return new IllegalInstruction;
541 Stick = Rs1 ^ Rs2_or_imm13;
542 }});
543 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}});
544 0x1A: Priv::wrstrand_sts_reg({{
545 if(Pstate<2:> && !Hpstate<2:>)
546 StrandStsReg = StrandStsReg<63:1> |
547 (Rs1 ^ Rs2_or_imm13)<0:>;
548 else
549 StrandStsReg = Rs1 ^ Rs2_or_imm13;
550 }});
551 //0x1A is supposed to be reserved, but it writes the strand
552 //status register.
553 //0x1B-0x1F should cause an illegal instruction exception
554 }
555 0x31: decode FCN {
556 0x0: Priv::saved({{
557 assert(Cansave < NWindows - 2);
558 assert(Otherwin || Canrestore);
559 Cansave = Cansave + 1;
560 if(Otherwin == 0)
561 Canrestore = Canrestore - 1;
562 else
563 Otherwin = Otherwin - 1;
564 }});
565 0x1: Priv::restored({{
566 assert(Cansave || Otherwin);
567 assert(Canrestore < NWindows - 2);
568 Canrestore = Canrestore + 1;
569 if(Otherwin == 0)
570 Cansave = Cansave - 1;
571 else
572 Otherwin = Otherwin - 1;
573
574 if(Cleanwin < NWindows - 1)
575 Cleanwin = Cleanwin + 1;
576 }});
577 }
578 0x32: decode RD {
579 0x00: Priv::wrprtpc({{
580 if(Tl == 0)
581 return new IllegalInstruction;
582 else
583 Tpc = Rs1 ^ Rs2_or_imm13;
584 }});
585 0x01: Priv::wrprtnpc({{
586 if(Tl == 0)
587 return new IllegalInstruction;
588 else
589 Tnpc = Rs1 ^ Rs2_or_imm13;
590 }});
591 0x02: Priv::wrprtstate({{
592 if(Tl == 0)
593 return new IllegalInstruction;
594 else
595 Tstate = Rs1 ^ Rs2_or_imm13;
596 }});
597 0x03: Priv::wrprtt({{
598 if(Tl == 0)
599 return new IllegalInstruction;
600 else
601 Tt = Rs1 ^ Rs2_or_imm13;
602 }});
603 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
604 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
605 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
606 0x07: Priv::wrprtl({{
607 if(Pstate<2:> && !Hpstate<2:>)
608 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
609 else
610 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);
611 }});
612 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
613 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
614 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
615 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
616 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
617 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
618 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
619 //0x0F should cause an illegal instruction exception
620 0x10: Priv::wrprgl({{
621 if(Pstate<2:> && !Hpstate<2:>)
622 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL);
623 else
624 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
625 }});
626 //0x11-0x1F should cause an illegal instruction exception
627 }
628 0x33: decode RD {
629 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
630 0x01: HPriv::wrhprhtstate({{
631 if(Tl == 0)
632 return new IllegalInstruction;
633 Htstate = Rs1 ^ Rs2_or_imm13;
634 }});
635 //0x02 should cause an illegal instruction exception
636 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
637 //0x04 should cause an illegal instruction exception
638 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
639 //0x06-0x01D should cause an illegal instruction exception
640 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
641 }
642 0x34: decode OPF{
643 format BasicOperate{
644 0x01: fmovs({{
645 Frds.uw = Frs2s.uw;
646 //fsr.ftt = fsr.cexc = 0
647 Fsr &= ~(7 << 14);
648 Fsr &= ~(0x1F);
649 }});
650 0x02: fmovd({{
651 Frd.udw = Frs2.udw;
652 //fsr.ftt = fsr.cexc = 0
653 Fsr &= ~(7 << 14);
654 Fsr &= ~(0x1F);
655 }});
656 0x03: Trap::fmovq({{fault = new FpExceptionOther;}}); //unimp fpop
657 0x05: fnegs({{
658 Frds.uw = Frs2s.uw ^ (1UL << 31);
659 //fsr.ftt = fsr.cexc = 0
660 Fsr &= ~(7 << 14);
661 Fsr &= ~(0x1F);
662 }});
663 0x06: fnegd({{
664 Frd.udw = Frs2.udw ^ (1ULL << 63);
665 //fsr.ftt = fsr.cexc = 0
666 Fsr &= ~(7 << 14);
667 Fsr &= ~(0x1F);
668 }});
669 0x07: Trap::fnegq({{fault = new FpExceptionOther;}}); //fpop unimp
670 0x09: fabss({{
671 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;
672 //fsr.ftt = fsr.cexc = 0
673 Fsr &= ~(7 << 14);
674 Fsr &= ~(0x1F);
675 }});
676 0x0A: fabsd({{
677 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;
678 //fsr.ftt = fsr.cexc = 0
679 Fsr &= ~(7 << 14);
680 Fsr &= ~(0x1F);
681 }});
682 0x0B: Trap::fabsq({{fault = new FpExceptionOther;}}); //fpop unimp
683 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}});
684 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}});
685 0x2B: Trap::fsqrtq({{fault = new FpExceptionOther;}}); //unimp fpop
686 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
687 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
688 0x43: Trap::faddq({{fault = new FpExceptionOther;}}); //unimp fpop
689 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
690 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
691 0x47: Trap::fsubq({{fault = new FpExceptionOther;}}); //unimp fpop
692 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
693 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
694 0x4B: Trap::fmulq({{fault = new FpExceptionOther;}}); //unimp fpop
695 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
696 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
697 0x4F: Trap::fdivq({{fault = new FpExceptionOther;}}); //unimp fpop
698 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
699 0x6E: Trap::fdmulq({{fault = new FpExceptionOther;}}); //unimp fpop
700 0x81: fstox({{
701 Frd.df = (double)static_cast<int64_t>(Frs2s.sf);
702 }});
703 0x82: fdtox({{
704 Frd.df = (double)static_cast<int64_t>(Frs2.df);
705 }});
706 0x83: Trap::fqtox({{fault = new FpExceptionOther;}}); //unimp fpop
707 0x84: fxtos({{
708 Frds.sf = static_cast<float>((int64_t)Frs2.df);
709 }});
710 0x88: fxtod({{
711 Frd.df = static_cast<double>((int64_t)Frs2.df);
712 }});
713 0x8C: Trap::fxtoq({{fault = new FpExceptionOther;}}); //unimp fpop
714 0xC4: fitos({{
715 Frds.sf = static_cast<float>((int32_t)Frs2s.sf);
716 }});
717 0xC6: fdtos({{Frds.sf = Frs2.df;}});
718 0xC7: Trap::fqtos({{fault = new FpExceptionOther;}}); //unimp fpop
719 0xC8: fitod({{
720 Frd.df = static_cast<double>((int32_t)Frs2s.sf);
721 }});
722 0xC9: fstod({{Frd.df = Frs2s.sf;}});
723 0xCB: Trap::fqtod({{fault = new FpExceptionOther;}}); // unimp fpop
724 0xCC: Trap::fitoq({{fault = new FpExceptionOther;}}); // unimp fpop
725 0xCD: Trap::fstoq({{fault = new FpExceptionOther;}}); // unimp fpop
726 0xCE: Trap::fdtoq({{fault = new FpExceptionOther;}}); // unimp fpop
727 0xD1: fstoi({{
728 Frds.sf = (float)static_cast<int32_t>(Frs2s.sf);
729 }});
730 0xD2: fdtoi({{
731 Frds.sf = (float)static_cast<int32_t>(Frs2.df);
732 }});
733 0xD3: Trap::fqtoi({{fault = new FpExceptionOther;}}); // unimp fpop
734 default: FailUnimpl::fpop1();
735 }
736 }
|
738 //This used to be just impdep1, but now it's a whole bunch
739 //of instructions
740 0x36: decode OPF{
741 0x00: FailUnimpl::edge8();
742 0x01: FailUnimpl::edge8n();
743 0x02: FailUnimpl::edge8l();
744 0x03: FailUnimpl::edge8ln();
745 0x04: FailUnimpl::edge16();
746 0x05: FailUnimpl::edge16n();
747 0x06: FailUnimpl::edge16l();
748 0x07: FailUnimpl::edge16ln();
749 0x08: FailUnimpl::edge32();
750 0x09: FailUnimpl::edge32n();
751 0x0A: FailUnimpl::edge32l();
752 0x0B: FailUnimpl::edge32ln();
753 0x10: FailUnimpl::array8();
754 0x12: FailUnimpl::array16();
755 0x14: FailUnimpl::array32();
756 0x18: BasicOperate::alignaddr({{
757 uint64_t sum = Rs1 + Rs2;
758 Rd = sum & ~7;
759 Gsr = (Gsr & ~7) | (sum & 7);
760 }});
761 0x19: FailUnimpl::bmask();
762 0x1A: BasicOperate::alignaddresslittle({{
763 uint64_t sum = Rs1 + Rs2;
764 Rd = sum & ~7;
765 Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
766 }});
767 0x20: FailUnimpl::fcmple16();
768 0x22: FailUnimpl::fcmpne16();
769 0x24: FailUnimpl::fcmple32();
770 0x26: FailUnimpl::fcmpne32();
771 0x28: FailUnimpl::fcmpgt16();
772 0x2A: FailUnimpl::fcmpeq16();
773 0x2C: FailUnimpl::fcmpgt32();
774 0x2E: FailUnimpl::fcmpeq32();
775 0x31: FailUnimpl::fmul8x16();
776 0x33: FailUnimpl::fmul8x16au();
777 0x35: FailUnimpl::fmul8x16al();
778 0x36: FailUnimpl::fmul8sux16();
779 0x37: FailUnimpl::fmul8ulx16();
780 0x38: FailUnimpl::fmuld8sux16();
781 0x39: FailUnimpl::fmuld8ulx16();
782 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
783 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
784 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
785 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
786 0x48: BasicOperate::faligndata({{
787 uint64_t msbX = Frs1.udw;
788 uint64_t lsbX = Frs2.udw;
789 //Some special cases need to be split out, first
790 //because they're the most likely to be used, and
791 //second because otherwise, we end up shifting by
792 //greater than the width of the type being shifted,
793 //namely 64, which produces undefined results according
794 //to the C standard.
795 switch(Gsr<2:0>)
796 {
797 case 0:
798 Frd.udw = msbX;
799 break;
800 case 8:
801 Frd.udw = lsbX;
802 break;
803 default:
804 uint64_t msbShift = Gsr<2:0> * 8;
805 uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
806 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
807 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
808 Frd.udw = ((msbX & msbMask) << msbShift) |
809 ((lsbX & lsbMask) >> lsbShift);
810 }
811 }});
812 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
813 0x4C: FailUnimpl::bshuffle();
814 0x4D: FailUnimpl::fexpand();
815 0x50: FailUnimpl::fpadd16();
816 0x51: FailUnimpl::fpadd16s();
817 0x52: FailUnimpl::fpadd32();
818 0x53: FailUnimpl::fpadd32s();
819 0x54: FailUnimpl::fpsub16();
820 0x55: FailUnimpl::fpsub16s();
821 0x56: FailUnimpl::fpsub32();
822 0x57: FailUnimpl::fpsub32s();
823 0x60: BasicOperate::fzero({{Frd.df = 0;}});
824 0x61: BasicOperate::fzeros({{Frds.sf = 0;}});
825 0x62: FailUnimpl::fnor();
826 0x63: FailUnimpl::fnors();
827 0x64: FailUnimpl::fandnot2();
828 0x65: FailUnimpl::fandnot2s();
829 0x66: BasicOperate::fnot2({{
830 Frd.df = (double)(~((uint64_t)Frs2.df));
831 }});
832 0x67: BasicOperate::fnot2s({{
833 Frds.sf = (float)(~((uint32_t)Frs2s.sf));
834 }});
835 0x68: FailUnimpl::fandnot1();
836 0x69: FailUnimpl::fandnot1s();
837 0x6A: BasicOperate::fnot1({{
838 Frd.df = (double)(~((uint64_t)Frs1.df));
839 }});
840 0x6B: BasicOperate::fnot1s({{
841 Frds.sf = (float)(~((uint32_t)Frs1s.sf));
842 }});
843 0x6C: FailUnimpl::fxor();
844 0x6D: FailUnimpl::fxors();
845 0x6E: FailUnimpl::fnand();
846 0x6F: FailUnimpl::fnands();
847 0x70: FailUnimpl::fand();
848 0x71: FailUnimpl::fands();
849 0x72: FailUnimpl::fxnor();
850 0x73: FailUnimpl::fxnors();
851 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}});
852 0x75: BasicOperate::fsrc1s({{Frds.uw = Frs1s.uw;}});
853 0x76: FailUnimpl::fornot2();
854 0x77: FailUnimpl::fornot2s();
855 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}});
856 0x79: BasicOperate::fsrc2s({{Frds.uw = Frs2s.uw;}});
857 0x7A: FailUnimpl::fornot1();
858 0x7B: FailUnimpl::fornot1s();
859 0x7C: FailUnimpl::for();
860 0x7D: FailUnimpl::fors();
861 0x7E: BasicOperate::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}});
862 0x7F: BasicOperate::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}});
863 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
864 0x81: FailUnimpl::siam();
865 }
866 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
867 0x38: Branch::jmpl({{
868 Addr target = Rs1 + Rs2_or_imm13;
869 if(target & 0x3)
870 fault = new MemAddressNotAligned;
871 else
872 {
873 if (Pstate<3:>)
874 Rd = (xc->readPC())<31:0>;
875 else
876 Rd = xc->readPC();
877 NNPC = target;
878 }
879 }});
880 0x39: Branch::return({{
881 Addr target = Rs1 + Rs2_or_imm13;
882 if(fault == NoFault)
883 {
884 //Check for fills which are higher priority than alignment
885 //faults.
886 if(Canrestore == 0)
887 {
888 if(Otherwin)
889 fault = new FillNOther(4*Wstate<5:3>);
890 else
891 fault = new FillNNormal(4*Wstate<2:0>);
892 }
893 //Check for alignment faults
894 else if(target & 0x3)
895 fault = new MemAddressNotAligned;
896 else
897 {
898 NNPC = target;
899 Cwp = (Cwp - 1 + NWindows) % NWindows;
900 Cansave = Cansave + 1;
901 Canrestore = Canrestore - 1;
902 }
903 }
904 }});
905 0x3A: decode CC
906 {
907 0x0: Trap::tcci({{
908 if(passesCondition(Ccr<3:0>, COND2))
909 {
910#if FULL_SYSTEM
911 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
912 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
913 fault = new TrapInstruction(lTrapNum);
914#else
915 DPRINTF(Sparc, "The syscall number is %d\n", R1);
916 xc->syscall(R1);
917#endif
918 }
919 }}, IsSerializeAfter, IsNonSpeculative);
920 0x2: Trap::tccx({{
921 if(passesCondition(Ccr<7:4>, COND2))
922 {
923#if FULL_SYSTEM
924 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
925 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
926 fault = new TrapInstruction(lTrapNum);
927#else
928 DPRINTF(Sparc, "The syscall number is %d\n", R1);
929 xc->syscall(R1);
930#endif
931 }
932 }}, IsSerializeAfter, IsNonSpeculative);
933 }
934 0x3B: Nop::flush({{/*Instruction memory flush*/}});
935 0x3C: save({{
936 if(Cansave == 0)
937 {
938 if(Otherwin)
939 fault = new SpillNOther(4*Wstate<5:3>);
940 else
941 fault = new SpillNNormal(4*Wstate<2:0>);
942 }
943 else if(Cleanwin - Canrestore == 0)
944 {
945 fault = new CleanWindow;
946 }
947 else
948 {
949 Cwp = (Cwp + 1) % NWindows;
950 Rd_next = Rs1 + Rs2_or_imm13;
951 Cansave = Cansave - 1;
952 Canrestore = Canrestore + 1;
953 }
954 }});
955 0x3D: restore({{
956 if(Canrestore == 0)
957 {
958 if(Otherwin)
959 fault = new FillNOther(4*Wstate<5:3>);
960 else
961 fault = new FillNNormal(4*Wstate<2:0>);
962 }
963 else
964 {
965 Cwp = (Cwp - 1 + NWindows) % NWindows;
966 Rd_prev = Rs1 + Rs2_or_imm13;
967 Cansave = Cansave + 1;
968 Canrestore = Canrestore - 1;
969 }
970 }});
971 0x3E: decode FCN {
972 0x0: Priv::done({{
973 if(Tl == 0)
974 return new IllegalInstruction;
975
976 Cwp = Tstate<4:0>;
977 Pstate = Tstate<20:8>;
978 Asi = Tstate<31:24>;
979 Ccr = Tstate<39:32>;
980 Gl = Tstate<42:40>;
981 Hpstate = Htstate;
982 NPC = Tnpc;
983 NNPC = Tnpc + 4;
984 Tl = Tl - 1;
985 }});
986 0x1: Priv::retry({{
987 if(Tl == 0)
988 return new IllegalInstruction;
989 Cwp = Tstate<4:0>;
990 Pstate = Tstate<20:8>;
991 Asi = Tstate<31:24>;
992 Ccr = Tstate<39:32>;
993 Gl = Tstate<42:40>;
994 Hpstate = Htstate;
995 NPC = Tpc;
996 NNPC = Tnpc;
997 Tl = Tl - 1;
998 }});
999 }
1000 }
1001 }
1002 0x3: decode OP3 {
1003 format Load {
1004 0x00: lduw({{Rd = Mem.uw;}});
1005 0x01: ldub({{Rd = Mem.ub;}});
1006 0x02: lduh({{Rd = Mem.uhw;}});
1007 0x03: ldtw({{
1008 uint64_t val = Mem.udw;
1009 RdLow = val<31:0>;
1010 RdHigh = val<63:32>;
1011 }});
1012 }
1013 format Store {
1014 0x04: stw({{Mem.uw = Rd.sw;}});
1015 0x05: stb({{Mem.ub = Rd.sb;}});
1016 0x06: sth({{Mem.uhw = Rd.shw;}});
1017 0x07: sttw({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
1018 }
1019 format Load {
1020 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
1021 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
1022 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
1023 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
1024 }
1025 0x0D: LoadStore::ldstub(
1026 {{uReg0 = Mem.ub;}},
1027 {{Rd.ub = uReg0;
1028 Mem.ub = 0xFF;}});
1029 0x0E: Store::stx({{Mem.udw = Rd}});
1030 0x0F: LoadStore::swap(
1031 {{ uReg0 = Mem.uw}},
1032 {{ Mem.uw = Rd.uw;
1033 Rd.uw = uReg0;}});
1034 format LoadAlt {
1035 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
1036 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
1037 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
1038 0x13: decode EXT_ASI {
1039 //ASI_LDTD_AIUP
1040 0x22: TwinLoad::ldtx_aiup(
1041 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1042 //ASI_LDTD_AIUS
1043 0x23: TwinLoad::ldtx_aius(
1044 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1045 //ASI_QUAD_LDD
1046 0x24: TwinLoad::ldtx_quad_ldd(
1047 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1048 //ASI_LDTX_REAL
1049 0x26: TwinLoad::ldtx_real(
1050 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1051 //ASI_LDTX_N
1052 0x27: TwinLoad::ldtx_n(
1053 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1054 //ASI_LDTX_L
1055 0x2C: TwinLoad::ldtx_l(
1056 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1057 //ASI_LDTX_REAL_L
1058 0x2E: TwinLoad::ldtx_real_l(
1059 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1060 //ASI_LDTX_N_L
1061 0x2F: TwinLoad::ldtx_n_l(
1062 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1063 //ASI_LDTX_P
1064 0xE2: TwinLoad::ldtx_p(
1065 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1066 //ASI_LDTX_S
1067 0xE3: TwinLoad::ldtx_s(
1068 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1069 default: ldtwa({{
1070 uint64_t val = Mem.udw;
1071 RdLow = val<31:0>;
1072 RdHigh = val<63:32>;
1073 }}, {{EXT_ASI}});
1074 }
1075 }
1076 format StoreAlt {
1077 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
1078 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
1079 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
1080 0x17: sttwa({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}});
1081 }
1082 format LoadAlt {
1083 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
1084 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}});
1085 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}});
1086 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}});
1087 }
1088 0x1D: LoadStoreAlt::ldstuba(
1089 {{uReg0 = Mem.ub;}},
1090 {{Rd.ub = uReg0;
1091 Mem.ub = 0xFF;}}, {{EXT_ASI}});
1092 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}});
1093 0x1F: LoadStoreAlt::swapa(
1094 {{ uReg0 = Mem.uw}},
1095 {{ Mem.uw = Rd.uw;
1096 Rd.uw = uReg0;}}, {{EXT_ASI}});
1097 format Trap {
1098 0x20: Load::ldf({{Frds.uw = Mem.uw;}});
1099 0x21: decode X {
1100 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}});
1101 0x1: Load::ldxfsr({{Fsr = Mem.udw;}});
1102 }
1103 0x22: ldqf({{fault = new FpDisabled;}});
1104 0x23: Load::lddf({{Frd.udw = Mem.udw;}});
1105 0x24: Store::stf({{Mem.uw = Frds.uw;}});
1106 0x25: decode X {
1107 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}});
1108 0x1: Store::stxfsr({{Mem.udw = Fsr;}});
1109 }
1110 0x26: stqf({{fault = new FpDisabled;}});
1111 0x27: Store::stdf({{Mem.udw = Frd.udw;}});
1112 0x2D: Nop::prefetch({{ }});
1113 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}});
1114 0x32: ldqfa({{fault = new FpDisabled;}});
1115 format LoadAlt {
1116 0x33: decode EXT_ASI {
1117 //ASI_NUCLEUS
1118 0x04: FailUnimpl::lddfa_n();
1119 //ASI_NUCLEUS_LITTLE
1120 0x0C: FailUnimpl::lddfa_nl();
1121 //ASI_AS_IF_USER_PRIMARY
1122 0x10: FailUnimpl::lddfa_aiup();
1123 //ASI_AS_IF_USER_PRIMARY_LITTLE
1124 0x18: FailUnimpl::lddfa_aiupl();
1125 //ASI_AS_IF_USER_SECONDARY
1126 0x11: FailUnimpl::lddfa_aius();
1127 //ASI_AS_IF_USER_SECONDARY_LITTLE
1128 0x19: FailUnimpl::lddfa_aiusl();
1129 //ASI_REAL
1130 0x14: FailUnimpl::lddfa_real();
1131 //ASI_REAL_LITTLE
1132 0x1C: FailUnimpl::lddfa_real_l();
1133 //ASI_REAL_IO
1134 0x15: FailUnimpl::lddfa_real_io();
1135 //ASI_REAL_IO_LITTLE
1136 0x1D: FailUnimpl::lddfa_real_io_l();
1137 //ASI_PRIMARY
1138 0x80: FailUnimpl::lddfa_p();
1139 //ASI_PRIMARY_LITTLE
1140 0x88: FailUnimpl::lddfa_pl();
1141 //ASI_SECONDARY
1142 0x81: FailUnimpl::lddfa_s();
1143 //ASI_SECONDARY_LITTLE
1144 0x89: FailUnimpl::lddfa_sl();
1145 //ASI_PRIMARY_NO_FAULT
1146 0x82: FailUnimpl::lddfa_pnf();
1147 //ASI_PRIMARY_NO_FAULT_LITTLE
1148 0x8A: FailUnimpl::lddfa_pnfl();
1149 //ASI_SECONDARY_NO_FAULT
1150 0x83: FailUnimpl::lddfa_snf();
1151 //ASI_SECONDARY_NO_FAULT_LITTLE
1152 0x8B: FailUnimpl::lddfa_snfl();
1153
1154 format BlockLoad {
1155 // LDBLOCKF
1156 //ASI_BLOCK_AS_IF_USER_PRIMARY
1157 0x16: FailUnimpl::ldblockf_aiup();
1158 //ASI_BLOCK_AS_IF_USER_SECONDARY
1159 0x17: FailUnimpl::ldblockf_aius();
1160 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1161 0x1E: FailUnimpl::ldblockf_aiupl();
1162 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1163 0x1F: FailUnimpl::ldblockf_aiusl();
1164 //ASI_BLOCK_PRIMARY
1165 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}});
1166 //ASI_BLOCK_SECONDARY
1167 0xF1: FailUnimpl::ldblockf_s();
1168 //ASI_BLOCK_PRIMARY_LITTLE
1169 0xF8: FailUnimpl::ldblockf_pl();
1170 //ASI_BLOCK_SECONDARY_LITTLE
1171 0xF9: FailUnimpl::ldblockf_sl();
1172 }
1173
1174 //LDSHORTF
1175 //ASI_FL8_PRIMARY
1176 0xD0: FailUnimpl::ldshortf_8p();
1177 //ASI_FL8_SECONDARY
1178 0xD1: FailUnimpl::ldshortf_8s();
1179 //ASI_FL8_PRIMARY_LITTLE
1180 0xD8: FailUnimpl::ldshortf_8pl();
1181 //ASI_FL8_SECONDARY_LITTLE
1182 0xD9: FailUnimpl::ldshortf_8sl();
1183 //ASI_FL16_PRIMARY
1184 0xD2: FailUnimpl::ldshortf_16p();
1185 //ASI_FL16_SECONDARY
1186 0xD3: FailUnimpl::ldshortf_16s();
1187 //ASI_FL16_PRIMARY_LITTLE
1188 0xDA: FailUnimpl::ldshortf_16pl();
1189 //ASI_FL16_SECONDARY_LITTLE
1190 0xDB: FailUnimpl::ldshortf_16sl();
1191 //Not an ASI which is legal with lddfa
1192 default: Trap::lddfa_bad_asi(
1193 {{fault = new DataAccessException;}});
1194 }
1195 }
1196 0x34: Store::stfa({{Mem.uw = Frds.uw;}});
1197 0x36: stqfa({{fault = new FpDisabled;}});
1198 format StoreAlt {
1199 0x37: decode EXT_ASI {
1200 //ASI_NUCLEUS
1201 0x04: FailUnimpl::stdfa_n();
1202 //ASI_NUCLEUS_LITTLE
1203 0x0C: FailUnimpl::stdfa_nl();
1204 //ASI_AS_IF_USER_PRIMARY
1205 0x10: FailUnimpl::stdfa_aiup();
1206 //ASI_AS_IF_USER_PRIMARY_LITTLE
1207 0x18: FailUnimpl::stdfa_aiupl();
1208 //ASI_AS_IF_USER_SECONDARY
1209 0x11: FailUnimpl::stdfa_aius();
1210 //ASI_AS_IF_USER_SECONDARY_LITTLE
1211 0x19: FailUnimpl::stdfa_aiusl();
1212 //ASI_REAL
1213 0x14: FailUnimpl::stdfa_real();
1214 //ASI_REAL_LITTLE
1215 0x1C: FailUnimpl::stdfa_real_l();
1216 //ASI_REAL_IO
1217 0x15: FailUnimpl::stdfa_real_io();
1218 //ASI_REAL_IO_LITTLE
1219 0x1D: FailUnimpl::stdfa_real_io_l();
1220 //ASI_PRIMARY
1221 0x80: FailUnimpl::stdfa_p();
1222 //ASI_PRIMARY_LITTLE
1223 0x88: FailUnimpl::stdfa_pl();
1224 //ASI_SECONDARY
1225 0x81: FailUnimpl::stdfa_s();
1226 //ASI_SECONDARY_LITTLE
1227 0x89: FailUnimpl::stdfa_sl();
1228 //ASI_PRIMARY_NO_FAULT
1229 0x82: FailUnimpl::stdfa_pnf();
1230 //ASI_PRIMARY_NO_FAULT_LITTLE
1231 0x8A: FailUnimpl::stdfa_pnfl();
1232 //ASI_SECONDARY_NO_FAULT
1233 0x83: FailUnimpl::stdfa_snf();
1234 //ASI_SECONDARY_NO_FAULT_LITTLE
1235 0x8B: FailUnimpl::stdfa_snfl();
1236
1237 format BlockStore {
1238 // STBLOCKF
1239 //ASI_BLOCK_AS_IF_USER_PRIMARY
1240 0x16: FailUnimpl::stblockf_aiup();
1241 //ASI_BLOCK_AS_IF_USER_SECONDARY
1242 0x17: FailUnimpl::stblockf_aius();
1243 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1244 0x1E: FailUnimpl::stblockf_aiupl();
1245 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1246 0x1F: FailUnimpl::stblockf_aiusl();
1247 //ASI_BLOCK_PRIMARY
1248 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}});
1249 //ASI_BLOCK_SECONDARY
1250 0xF1: FailUnimpl::stblockf_s();
1251 //ASI_BLOCK_PRIMARY_LITTLE
1252 0xF8: FailUnimpl::stblockf_pl();
1253 //ASI_BLOCK_SECONDARY_LITTLE
1254 0xF9: FailUnimpl::stblockf_sl();
1255 }
1256
1257 //STSHORTF
1258 //ASI_FL8_PRIMARY
1259 0xD0: FailUnimpl::stshortf_8p();
1260 //ASI_FL8_SECONDARY
1261 0xD1: FailUnimpl::stshortf_8s();
1262 //ASI_FL8_PRIMARY_LITTLE
1263 0xD8: FailUnimpl::stshortf_8pl();
1264 //ASI_FL8_SECONDARY_LITTLE
1265 0xD9: FailUnimpl::stshortf_8sl();
1266 //ASI_FL16_PRIMARY
1267 0xD2: FailUnimpl::stshortf_16p();
1268 //ASI_FL16_SECONDARY
1269 0xD3: FailUnimpl::stshortf_16s();
1270 //ASI_FL16_PRIMARY_LITTLE
1271 0xDA: FailUnimpl::stshortf_16pl();
1272 //ASI_FL16_SECONDARY_LITTLE
1273 0xDB: FailUnimpl::stshortf_16sl();
1274 //Not an ASI which is legal with lddfa
1275 default: Trap::stdfa_bad_asi(
1276 {{fault = new DataAccessException;}});
1277 }
1278 }
1279 0x3C: Cas::casa(
1280 {{uReg0 = Mem.uw;}},
1281 {{if(Rs2.uw == uReg0)
1282 Mem.uw = Rd.uw;
1283 else
1284 storeCond = false;
1285 Rd.uw = uReg0;}}, {{EXT_ASI}});
1286 0x3D: Nop::prefetcha({{ }});
1287 0x3E: Cas::casxa(
1288 {{uReg0 = Mem.udw;}},
1289 {{if(Rs2 == uReg0)
1290 Mem.udw = Rd;
1291 else
1292 storeCond = false;
1293 Rd = uReg0;}}, {{EXT_ASI}});
1294 }
1295 }
1296}
| 800 //This used to be just impdep1, but now it's a whole bunch
801 //of instructions
802 0x36: decode OPF{
803 0x00: FailUnimpl::edge8();
804 0x01: FailUnimpl::edge8n();
805 0x02: FailUnimpl::edge8l();
806 0x03: FailUnimpl::edge8ln();
807 0x04: FailUnimpl::edge16();
808 0x05: FailUnimpl::edge16n();
809 0x06: FailUnimpl::edge16l();
810 0x07: FailUnimpl::edge16ln();
811 0x08: FailUnimpl::edge32();
812 0x09: FailUnimpl::edge32n();
813 0x0A: FailUnimpl::edge32l();
814 0x0B: FailUnimpl::edge32ln();
815 0x10: FailUnimpl::array8();
816 0x12: FailUnimpl::array16();
817 0x14: FailUnimpl::array32();
818 0x18: BasicOperate::alignaddr({{
819 uint64_t sum = Rs1 + Rs2;
820 Rd = sum & ~7;
821 Gsr = (Gsr & ~7) | (sum & 7);
822 }});
823 0x19: FailUnimpl::bmask();
824 0x1A: BasicOperate::alignaddresslittle({{
825 uint64_t sum = Rs1 + Rs2;
826 Rd = sum & ~7;
827 Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
828 }});
829 0x20: FailUnimpl::fcmple16();
830 0x22: FailUnimpl::fcmpne16();
831 0x24: FailUnimpl::fcmple32();
832 0x26: FailUnimpl::fcmpne32();
833 0x28: FailUnimpl::fcmpgt16();
834 0x2A: FailUnimpl::fcmpeq16();
835 0x2C: FailUnimpl::fcmpgt32();
836 0x2E: FailUnimpl::fcmpeq32();
837 0x31: FailUnimpl::fmul8x16();
838 0x33: FailUnimpl::fmul8x16au();
839 0x35: FailUnimpl::fmul8x16al();
840 0x36: FailUnimpl::fmul8sux16();
841 0x37: FailUnimpl::fmul8ulx16();
842 0x38: FailUnimpl::fmuld8sux16();
843 0x39: FailUnimpl::fmuld8ulx16();
844 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
845 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
846 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
847 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
848 0x48: BasicOperate::faligndata({{
849 uint64_t msbX = Frs1.udw;
850 uint64_t lsbX = Frs2.udw;
851 //Some special cases need to be split out, first
852 //because they're the most likely to be used, and
853 //second because otherwise, we end up shifting by
854 //greater than the width of the type being shifted,
855 //namely 64, which produces undefined results according
856 //to the C standard.
857 switch(Gsr<2:0>)
858 {
859 case 0:
860 Frd.udw = msbX;
861 break;
862 case 8:
863 Frd.udw = lsbX;
864 break;
865 default:
866 uint64_t msbShift = Gsr<2:0> * 8;
867 uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
868 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
869 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
870 Frd.udw = ((msbX & msbMask) << msbShift) |
871 ((lsbX & lsbMask) >> lsbShift);
872 }
873 }});
874 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
875 0x4C: FailUnimpl::bshuffle();
876 0x4D: FailUnimpl::fexpand();
877 0x50: FailUnimpl::fpadd16();
878 0x51: FailUnimpl::fpadd16s();
879 0x52: FailUnimpl::fpadd32();
880 0x53: FailUnimpl::fpadd32s();
881 0x54: FailUnimpl::fpsub16();
882 0x55: FailUnimpl::fpsub16s();
883 0x56: FailUnimpl::fpsub32();
884 0x57: FailUnimpl::fpsub32s();
885 0x60: BasicOperate::fzero({{Frd.df = 0;}});
886 0x61: BasicOperate::fzeros({{Frds.sf = 0;}});
887 0x62: FailUnimpl::fnor();
888 0x63: FailUnimpl::fnors();
889 0x64: FailUnimpl::fandnot2();
890 0x65: FailUnimpl::fandnot2s();
891 0x66: BasicOperate::fnot2({{
892 Frd.df = (double)(~((uint64_t)Frs2.df));
893 }});
894 0x67: BasicOperate::fnot2s({{
895 Frds.sf = (float)(~((uint32_t)Frs2s.sf));
896 }});
897 0x68: FailUnimpl::fandnot1();
898 0x69: FailUnimpl::fandnot1s();
899 0x6A: BasicOperate::fnot1({{
900 Frd.df = (double)(~((uint64_t)Frs1.df));
901 }});
902 0x6B: BasicOperate::fnot1s({{
903 Frds.sf = (float)(~((uint32_t)Frs1s.sf));
904 }});
905 0x6C: FailUnimpl::fxor();
906 0x6D: FailUnimpl::fxors();
907 0x6E: FailUnimpl::fnand();
908 0x6F: FailUnimpl::fnands();
909 0x70: FailUnimpl::fand();
910 0x71: FailUnimpl::fands();
911 0x72: FailUnimpl::fxnor();
912 0x73: FailUnimpl::fxnors();
913 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}});
914 0x75: BasicOperate::fsrc1s({{Frds.uw = Frs1s.uw;}});
915 0x76: FailUnimpl::fornot2();
916 0x77: FailUnimpl::fornot2s();
917 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}});
918 0x79: BasicOperate::fsrc2s({{Frds.uw = Frs2s.uw;}});
919 0x7A: FailUnimpl::fornot1();
920 0x7B: FailUnimpl::fornot1s();
921 0x7C: FailUnimpl::for();
922 0x7D: FailUnimpl::fors();
923 0x7E: BasicOperate::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}});
924 0x7F: BasicOperate::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}});
925 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
926 0x81: FailUnimpl::siam();
927 }
928 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
929 0x38: Branch::jmpl({{
930 Addr target = Rs1 + Rs2_or_imm13;
931 if(target & 0x3)
932 fault = new MemAddressNotAligned;
933 else
934 {
935 if (Pstate<3:>)
936 Rd = (xc->readPC())<31:0>;
937 else
938 Rd = xc->readPC();
939 NNPC = target;
940 }
941 }});
942 0x39: Branch::return({{
943 Addr target = Rs1 + Rs2_or_imm13;
944 if(fault == NoFault)
945 {
946 //Check for fills which are higher priority than alignment
947 //faults.
948 if(Canrestore == 0)
949 {
950 if(Otherwin)
951 fault = new FillNOther(4*Wstate<5:3>);
952 else
953 fault = new FillNNormal(4*Wstate<2:0>);
954 }
955 //Check for alignment faults
956 else if(target & 0x3)
957 fault = new MemAddressNotAligned;
958 else
959 {
960 NNPC = target;
961 Cwp = (Cwp - 1 + NWindows) % NWindows;
962 Cansave = Cansave + 1;
963 Canrestore = Canrestore - 1;
964 }
965 }
966 }});
967 0x3A: decode CC
968 {
969 0x0: Trap::tcci({{
970 if(passesCondition(Ccr<3:0>, COND2))
971 {
972#if FULL_SYSTEM
973 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
974 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
975 fault = new TrapInstruction(lTrapNum);
976#else
977 DPRINTF(Sparc, "The syscall number is %d\n", R1);
978 xc->syscall(R1);
979#endif
980 }
981 }}, IsSerializeAfter, IsNonSpeculative);
982 0x2: Trap::tccx({{
983 if(passesCondition(Ccr<7:4>, COND2))
984 {
985#if FULL_SYSTEM
986 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
987 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
988 fault = new TrapInstruction(lTrapNum);
989#else
990 DPRINTF(Sparc, "The syscall number is %d\n", R1);
991 xc->syscall(R1);
992#endif
993 }
994 }}, IsSerializeAfter, IsNonSpeculative);
995 }
996 0x3B: Nop::flush({{/*Instruction memory flush*/}});
997 0x3C: save({{
998 if(Cansave == 0)
999 {
1000 if(Otherwin)
1001 fault = new SpillNOther(4*Wstate<5:3>);
1002 else
1003 fault = new SpillNNormal(4*Wstate<2:0>);
1004 }
1005 else if(Cleanwin - Canrestore == 0)
1006 {
1007 fault = new CleanWindow;
1008 }
1009 else
1010 {
1011 Cwp = (Cwp + 1) % NWindows;
1012 Rd_next = Rs1 + Rs2_or_imm13;
1013 Cansave = Cansave - 1;
1014 Canrestore = Canrestore + 1;
1015 }
1016 }});
1017 0x3D: restore({{
1018 if(Canrestore == 0)
1019 {
1020 if(Otherwin)
1021 fault = new FillNOther(4*Wstate<5:3>);
1022 else
1023 fault = new FillNNormal(4*Wstate<2:0>);
1024 }
1025 else
1026 {
1027 Cwp = (Cwp - 1 + NWindows) % NWindows;
1028 Rd_prev = Rs1 + Rs2_or_imm13;
1029 Cansave = Cansave + 1;
1030 Canrestore = Canrestore - 1;
1031 }
1032 }});
1033 0x3E: decode FCN {
1034 0x0: Priv::done({{
1035 if(Tl == 0)
1036 return new IllegalInstruction;
1037
1038 Cwp = Tstate<4:0>;
1039 Pstate = Tstate<20:8>;
1040 Asi = Tstate<31:24>;
1041 Ccr = Tstate<39:32>;
1042 Gl = Tstate<42:40>;
1043 Hpstate = Htstate;
1044 NPC = Tnpc;
1045 NNPC = Tnpc + 4;
1046 Tl = Tl - 1;
1047 }});
1048 0x1: Priv::retry({{
1049 if(Tl == 0)
1050 return new IllegalInstruction;
1051 Cwp = Tstate<4:0>;
1052 Pstate = Tstate<20:8>;
1053 Asi = Tstate<31:24>;
1054 Ccr = Tstate<39:32>;
1055 Gl = Tstate<42:40>;
1056 Hpstate = Htstate;
1057 NPC = Tpc;
1058 NNPC = Tnpc;
1059 Tl = Tl - 1;
1060 }});
1061 }
1062 }
1063 }
1064 0x3: decode OP3 {
1065 format Load {
1066 0x00: lduw({{Rd = Mem.uw;}});
1067 0x01: ldub({{Rd = Mem.ub;}});
1068 0x02: lduh({{Rd = Mem.uhw;}});
1069 0x03: ldtw({{
1070 uint64_t val = Mem.udw;
1071 RdLow = val<31:0>;
1072 RdHigh = val<63:32>;
1073 }});
1074 }
1075 format Store {
1076 0x04: stw({{Mem.uw = Rd.sw;}});
1077 0x05: stb({{Mem.ub = Rd.sb;}});
1078 0x06: sth({{Mem.uhw = Rd.shw;}});
1079 0x07: sttw({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
1080 }
1081 format Load {
1082 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
1083 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
1084 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
1085 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
1086 }
1087 0x0D: LoadStore::ldstub(
1088 {{uReg0 = Mem.ub;}},
1089 {{Rd.ub = uReg0;
1090 Mem.ub = 0xFF;}});
1091 0x0E: Store::stx({{Mem.udw = Rd}});
1092 0x0F: LoadStore::swap(
1093 {{ uReg0 = Mem.uw}},
1094 {{ Mem.uw = Rd.uw;
1095 Rd.uw = uReg0;}});
1096 format LoadAlt {
1097 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
1098 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
1099 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
1100 0x13: decode EXT_ASI {
1101 //ASI_LDTD_AIUP
1102 0x22: TwinLoad::ldtx_aiup(
1103 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1104 //ASI_LDTD_AIUS
1105 0x23: TwinLoad::ldtx_aius(
1106 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1107 //ASI_QUAD_LDD
1108 0x24: TwinLoad::ldtx_quad_ldd(
1109 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1110 //ASI_LDTX_REAL
1111 0x26: TwinLoad::ldtx_real(
1112 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1113 //ASI_LDTX_N
1114 0x27: TwinLoad::ldtx_n(
1115 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1116 //ASI_LDTX_L
1117 0x2C: TwinLoad::ldtx_l(
1118 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1119 //ASI_LDTX_REAL_L
1120 0x2E: TwinLoad::ldtx_real_l(
1121 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1122 //ASI_LDTX_N_L
1123 0x2F: TwinLoad::ldtx_n_l(
1124 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1125 //ASI_LDTX_P
1126 0xE2: TwinLoad::ldtx_p(
1127 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1128 //ASI_LDTX_S
1129 0xE3: TwinLoad::ldtx_s(
1130 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1131 default: ldtwa({{
1132 uint64_t val = Mem.udw;
1133 RdLow = val<31:0>;
1134 RdHigh = val<63:32>;
1135 }}, {{EXT_ASI}});
1136 }
1137 }
1138 format StoreAlt {
1139 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
1140 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
1141 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
1142 0x17: sttwa({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}});
1143 }
1144 format LoadAlt {
1145 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
1146 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}});
1147 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}});
1148 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}});
1149 }
1150 0x1D: LoadStoreAlt::ldstuba(
1151 {{uReg0 = Mem.ub;}},
1152 {{Rd.ub = uReg0;
1153 Mem.ub = 0xFF;}}, {{EXT_ASI}});
1154 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}});
1155 0x1F: LoadStoreAlt::swapa(
1156 {{ uReg0 = Mem.uw}},
1157 {{ Mem.uw = Rd.uw;
1158 Rd.uw = uReg0;}}, {{EXT_ASI}});
1159 format Trap {
1160 0x20: Load::ldf({{Frds.uw = Mem.uw;}});
1161 0x21: decode X {
1162 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}});
1163 0x1: Load::ldxfsr({{Fsr = Mem.udw;}});
1164 }
1165 0x22: ldqf({{fault = new FpDisabled;}});
1166 0x23: Load::lddf({{Frd.udw = Mem.udw;}});
1167 0x24: Store::stf({{Mem.uw = Frds.uw;}});
1168 0x25: decode X {
1169 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}});
1170 0x1: Store::stxfsr({{Mem.udw = Fsr;}});
1171 }
1172 0x26: stqf({{fault = new FpDisabled;}});
1173 0x27: Store::stdf({{Mem.udw = Frd.udw;}});
1174 0x2D: Nop::prefetch({{ }});
1175 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}});
1176 0x32: ldqfa({{fault = new FpDisabled;}});
1177 format LoadAlt {
1178 0x33: decode EXT_ASI {
1179 //ASI_NUCLEUS
1180 0x04: FailUnimpl::lddfa_n();
1181 //ASI_NUCLEUS_LITTLE
1182 0x0C: FailUnimpl::lddfa_nl();
1183 //ASI_AS_IF_USER_PRIMARY
1184 0x10: FailUnimpl::lddfa_aiup();
1185 //ASI_AS_IF_USER_PRIMARY_LITTLE
1186 0x18: FailUnimpl::lddfa_aiupl();
1187 //ASI_AS_IF_USER_SECONDARY
1188 0x11: FailUnimpl::lddfa_aius();
1189 //ASI_AS_IF_USER_SECONDARY_LITTLE
1190 0x19: FailUnimpl::lddfa_aiusl();
1191 //ASI_REAL
1192 0x14: FailUnimpl::lddfa_real();
1193 //ASI_REAL_LITTLE
1194 0x1C: FailUnimpl::lddfa_real_l();
1195 //ASI_REAL_IO
1196 0x15: FailUnimpl::lddfa_real_io();
1197 //ASI_REAL_IO_LITTLE
1198 0x1D: FailUnimpl::lddfa_real_io_l();
1199 //ASI_PRIMARY
1200 0x80: FailUnimpl::lddfa_p();
1201 //ASI_PRIMARY_LITTLE
1202 0x88: FailUnimpl::lddfa_pl();
1203 //ASI_SECONDARY
1204 0x81: FailUnimpl::lddfa_s();
1205 //ASI_SECONDARY_LITTLE
1206 0x89: FailUnimpl::lddfa_sl();
1207 //ASI_PRIMARY_NO_FAULT
1208 0x82: FailUnimpl::lddfa_pnf();
1209 //ASI_PRIMARY_NO_FAULT_LITTLE
1210 0x8A: FailUnimpl::lddfa_pnfl();
1211 //ASI_SECONDARY_NO_FAULT
1212 0x83: FailUnimpl::lddfa_snf();
1213 //ASI_SECONDARY_NO_FAULT_LITTLE
1214 0x8B: FailUnimpl::lddfa_snfl();
1215
1216 format BlockLoad {
1217 // LDBLOCKF
1218 //ASI_BLOCK_AS_IF_USER_PRIMARY
1219 0x16: FailUnimpl::ldblockf_aiup();
1220 //ASI_BLOCK_AS_IF_USER_SECONDARY
1221 0x17: FailUnimpl::ldblockf_aius();
1222 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1223 0x1E: FailUnimpl::ldblockf_aiupl();
1224 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1225 0x1F: FailUnimpl::ldblockf_aiusl();
1226 //ASI_BLOCK_PRIMARY
1227 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}});
1228 //ASI_BLOCK_SECONDARY
1229 0xF1: FailUnimpl::ldblockf_s();
1230 //ASI_BLOCK_PRIMARY_LITTLE
1231 0xF8: FailUnimpl::ldblockf_pl();
1232 //ASI_BLOCK_SECONDARY_LITTLE
1233 0xF9: FailUnimpl::ldblockf_sl();
1234 }
1235
1236 //LDSHORTF
1237 //ASI_FL8_PRIMARY
1238 0xD0: FailUnimpl::ldshortf_8p();
1239 //ASI_FL8_SECONDARY
1240 0xD1: FailUnimpl::ldshortf_8s();
1241 //ASI_FL8_PRIMARY_LITTLE
1242 0xD8: FailUnimpl::ldshortf_8pl();
1243 //ASI_FL8_SECONDARY_LITTLE
1244 0xD9: FailUnimpl::ldshortf_8sl();
1245 //ASI_FL16_PRIMARY
1246 0xD2: FailUnimpl::ldshortf_16p();
1247 //ASI_FL16_SECONDARY
1248 0xD3: FailUnimpl::ldshortf_16s();
1249 //ASI_FL16_PRIMARY_LITTLE
1250 0xDA: FailUnimpl::ldshortf_16pl();
1251 //ASI_FL16_SECONDARY_LITTLE
1252 0xDB: FailUnimpl::ldshortf_16sl();
1253 //Not an ASI which is legal with lddfa
1254 default: Trap::lddfa_bad_asi(
1255 {{fault = new DataAccessException;}});
1256 }
1257 }
1258 0x34: Store::stfa({{Mem.uw = Frds.uw;}});
1259 0x36: stqfa({{fault = new FpDisabled;}});
1260 format StoreAlt {
1261 0x37: decode EXT_ASI {
1262 //ASI_NUCLEUS
1263 0x04: FailUnimpl::stdfa_n();
1264 //ASI_NUCLEUS_LITTLE
1265 0x0C: FailUnimpl::stdfa_nl();
1266 //ASI_AS_IF_USER_PRIMARY
1267 0x10: FailUnimpl::stdfa_aiup();
1268 //ASI_AS_IF_USER_PRIMARY_LITTLE
1269 0x18: FailUnimpl::stdfa_aiupl();
1270 //ASI_AS_IF_USER_SECONDARY
1271 0x11: FailUnimpl::stdfa_aius();
1272 //ASI_AS_IF_USER_SECONDARY_LITTLE
1273 0x19: FailUnimpl::stdfa_aiusl();
1274 //ASI_REAL
1275 0x14: FailUnimpl::stdfa_real();
1276 //ASI_REAL_LITTLE
1277 0x1C: FailUnimpl::stdfa_real_l();
1278 //ASI_REAL_IO
1279 0x15: FailUnimpl::stdfa_real_io();
1280 //ASI_REAL_IO_LITTLE
1281 0x1D: FailUnimpl::stdfa_real_io_l();
1282 //ASI_PRIMARY
1283 0x80: FailUnimpl::stdfa_p();
1284 //ASI_PRIMARY_LITTLE
1285 0x88: FailUnimpl::stdfa_pl();
1286 //ASI_SECONDARY
1287 0x81: FailUnimpl::stdfa_s();
1288 //ASI_SECONDARY_LITTLE
1289 0x89: FailUnimpl::stdfa_sl();
1290 //ASI_PRIMARY_NO_FAULT
1291 0x82: FailUnimpl::stdfa_pnf();
1292 //ASI_PRIMARY_NO_FAULT_LITTLE
1293 0x8A: FailUnimpl::stdfa_pnfl();
1294 //ASI_SECONDARY_NO_FAULT
1295 0x83: FailUnimpl::stdfa_snf();
1296 //ASI_SECONDARY_NO_FAULT_LITTLE
1297 0x8B: FailUnimpl::stdfa_snfl();
1298
1299 format BlockStore {
1300 // STBLOCKF
1301 //ASI_BLOCK_AS_IF_USER_PRIMARY
1302 0x16: FailUnimpl::stblockf_aiup();
1303 //ASI_BLOCK_AS_IF_USER_SECONDARY
1304 0x17: FailUnimpl::stblockf_aius();
1305 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1306 0x1E: FailUnimpl::stblockf_aiupl();
1307 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1308 0x1F: FailUnimpl::stblockf_aiusl();
1309 //ASI_BLOCK_PRIMARY
1310 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}});
1311 //ASI_BLOCK_SECONDARY
1312 0xF1: FailUnimpl::stblockf_s();
1313 //ASI_BLOCK_PRIMARY_LITTLE
1314 0xF8: FailUnimpl::stblockf_pl();
1315 //ASI_BLOCK_SECONDARY_LITTLE
1316 0xF9: FailUnimpl::stblockf_sl();
1317 }
1318
1319 //STSHORTF
1320 //ASI_FL8_PRIMARY
1321 0xD0: FailUnimpl::stshortf_8p();
1322 //ASI_FL8_SECONDARY
1323 0xD1: FailUnimpl::stshortf_8s();
1324 //ASI_FL8_PRIMARY_LITTLE
1325 0xD8: FailUnimpl::stshortf_8pl();
1326 //ASI_FL8_SECONDARY_LITTLE
1327 0xD9: FailUnimpl::stshortf_8sl();
1328 //ASI_FL16_PRIMARY
1329 0xD2: FailUnimpl::stshortf_16p();
1330 //ASI_FL16_SECONDARY
1331 0xD3: FailUnimpl::stshortf_16s();
1332 //ASI_FL16_PRIMARY_LITTLE
1333 0xDA: FailUnimpl::stshortf_16pl();
1334 //ASI_FL16_SECONDARY_LITTLE
1335 0xDB: FailUnimpl::stshortf_16sl();
1336 //Not an ASI which is legal with lddfa
1337 default: Trap::stdfa_bad_asi(
1338 {{fault = new DataAccessException;}});
1339 }
1340 }
1341 0x3C: Cas::casa(
1342 {{uReg0 = Mem.uw;}},
1343 {{if(Rs2.uw == uReg0)
1344 Mem.uw = Rd.uw;
1345 else
1346 storeCond = false;
1347 Rd.uw = uReg0;}}, {{EXT_ASI}});
1348 0x3D: Nop::prefetcha({{ }});
1349 0x3E: Cas::casxa(
1350 {{uReg0 = Mem.udw;}},
1351 {{if(Rs2 == uReg0)
1352 Mem.udw = Rd;
1353 else
1354 storeCond = false;
1355 Rd = uReg0;}}, {{EXT_ASI}});
1356 }
1357 }
1358}
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