1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OP default Unknown::unknown()
37{
38 0x0: decode OP2
39 {
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 //bpcc
45 0x1: decode COND2
46 {
47 //Branch Always
48 0x8: decode A
49 {
50 0x0: bpa(19, {{
51 NNPC = xc->readPC() + disp;
52 }});
53 0x1: bpa(19, {{
54 NPC = xc->readPC() + disp;
55 NNPC = NPC + 4;
56 }}, ',a');
57 }
58 //Branch Never
59 0x0: decode A
60 {
61 0x0: bpn(19, {{
62 NNPC = NNPC;//Don't do anything
63 }});
64 0x1: bpn(19, {{
65 NPC = xc->readNextPC() + 4;
66 NNPC = NPC + 4;
67 }}, ',a');
68 }
69 default: decode BPCC
70 {
71 0x0: bpcci(19, {{
72 if(passesCondition(Ccr<3:0>, COND2))
73 NNPC = xc->readPC() + disp;
74 else
75 handle_annul
76 }});
77 0x2: bpccx(19, {{
78 if(passesCondition(Ccr<7:4>, COND2))
79 {
80 //warn("Took branch!\n");
81 NNPC = xc->readPC() + disp;
82 }
83 else
84 {
85 //warn("Didn't take branch!\n");
86 handle_annul
87 }
88 }});
89 }
90 }
91 //bicc
92 0x2: decode COND2
93 {
94 //Branch Always
95 0x8: decode A
96 {
97 0x0: ba(22, {{
98 NNPC = xc->readPC() + disp;
99 }});
100 0x1: ba(22, {{
101 NPC = xc->readPC() + disp;
102 NNPC = NPC + 4;
103 }}, ',a');
104 }
105 //Branch Never
106 0x0: decode A
107 {
108 0x0: bn(22, {{
109 NNPC = NNPC;//Don't do anything
110 }});
111 0x1: bn(22, {{
112 NPC = xc->readNextPC() + 4;
113 NNPC = NPC + 4;
114 }}, ',a');
115 }
116 default: bicc(22, {{
117 if(passesCondition(Ccr<3:0>, COND2))
118 NNPC = xc->readPC() + disp;
119 else
120 handle_annul
121 }});
122 }
123 }
124 0x3: decode RCOND2
125 {
126 format BranchSplit
127 {
128 0x1: bpreq({{
129 if(Rs1.sdw == 0)
130 NNPC = xc->readPC() + disp;
131 else
132 handle_annul
133 }});
134 0x2: bprle({{
135 if(Rs1.sdw <= 0)
136 NNPC = xc->readPC() + disp;
137 else
138 handle_annul
139 }});
140 0x3: bprl({{
141 if(Rs1.sdw < 0)
142 NNPC = xc->readPC() + disp;
143 else
144 handle_annul
145 }});
146 0x5: bprne({{
147 if(Rs1.sdw != 0)
148 NNPC = xc->readPC() + disp;
149 else
150 handle_annul
151 }});
152 0x6: bprg({{
153 if(Rs1.sdw > 0)
154 NNPC = xc->readPC() + disp;
155 else
156 handle_annul
157 }});
158 0x7: bprge({{
159 if(Rs1.sdw >= 0)
160 NNPC = xc->readPC() + disp;
161 else
162 handle_annul
163 }});
164 }
165 }
166 //SETHI (or NOP if rd == 0 and imm == 0)
167 0x4: SetHi::sethi({{Rd.udw = imm;}});
168 0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
169 0x6: Trap::fbfcc({{fault = new FpDisabled;}});
170 }
171 0x1: BranchN::call(30, {{
172 if (Pstate<3:>)
173 R15 = (xc->readPC())<31:0>;
174 else
175 R15 = xc->readPC();
176 NNPC = R15 + disp;
177 }});
178 0x2: decode OP3 {
179 format IntOp {
180 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
181 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
182 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
183 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
184 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
185 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}});
186 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}});
187 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
188 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
189 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
190 0x0A: umul({{
191 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
192 Y = Rd<63:32>;
193 }});
194 0x0B: smul({{
| 1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OP default Unknown::unknown()
37{
38 0x0: decode OP2
39 {
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 //bpcc
45 0x1: decode COND2
46 {
47 //Branch Always
48 0x8: decode A
49 {
50 0x0: bpa(19, {{
51 NNPC = xc->readPC() + disp;
52 }});
53 0x1: bpa(19, {{
54 NPC = xc->readPC() + disp;
55 NNPC = NPC + 4;
56 }}, ',a');
57 }
58 //Branch Never
59 0x0: decode A
60 {
61 0x0: bpn(19, {{
62 NNPC = NNPC;//Don't do anything
63 }});
64 0x1: bpn(19, {{
65 NPC = xc->readNextPC() + 4;
66 NNPC = NPC + 4;
67 }}, ',a');
68 }
69 default: decode BPCC
70 {
71 0x0: bpcci(19, {{
72 if(passesCondition(Ccr<3:0>, COND2))
73 NNPC = xc->readPC() + disp;
74 else
75 handle_annul
76 }});
77 0x2: bpccx(19, {{
78 if(passesCondition(Ccr<7:4>, COND2))
79 {
80 //warn("Took branch!\n");
81 NNPC = xc->readPC() + disp;
82 }
83 else
84 {
85 //warn("Didn't take branch!\n");
86 handle_annul
87 }
88 }});
89 }
90 }
91 //bicc
92 0x2: decode COND2
93 {
94 //Branch Always
95 0x8: decode A
96 {
97 0x0: ba(22, {{
98 NNPC = xc->readPC() + disp;
99 }});
100 0x1: ba(22, {{
101 NPC = xc->readPC() + disp;
102 NNPC = NPC + 4;
103 }}, ',a');
104 }
105 //Branch Never
106 0x0: decode A
107 {
108 0x0: bn(22, {{
109 NNPC = NNPC;//Don't do anything
110 }});
111 0x1: bn(22, {{
112 NPC = xc->readNextPC() + 4;
113 NNPC = NPC + 4;
114 }}, ',a');
115 }
116 default: bicc(22, {{
117 if(passesCondition(Ccr<3:0>, COND2))
118 NNPC = xc->readPC() + disp;
119 else
120 handle_annul
121 }});
122 }
123 }
124 0x3: decode RCOND2
125 {
126 format BranchSplit
127 {
128 0x1: bpreq({{
129 if(Rs1.sdw == 0)
130 NNPC = xc->readPC() + disp;
131 else
132 handle_annul
133 }});
134 0x2: bprle({{
135 if(Rs1.sdw <= 0)
136 NNPC = xc->readPC() + disp;
137 else
138 handle_annul
139 }});
140 0x3: bprl({{
141 if(Rs1.sdw < 0)
142 NNPC = xc->readPC() + disp;
143 else
144 handle_annul
145 }});
146 0x5: bprne({{
147 if(Rs1.sdw != 0)
148 NNPC = xc->readPC() + disp;
149 else
150 handle_annul
151 }});
152 0x6: bprg({{
153 if(Rs1.sdw > 0)
154 NNPC = xc->readPC() + disp;
155 else
156 handle_annul
157 }});
158 0x7: bprge({{
159 if(Rs1.sdw >= 0)
160 NNPC = xc->readPC() + disp;
161 else
162 handle_annul
163 }});
164 }
165 }
166 //SETHI (or NOP if rd == 0 and imm == 0)
167 0x4: SetHi::sethi({{Rd.udw = imm;}});
168 0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
169 0x6: Trap::fbfcc({{fault = new FpDisabled;}});
170 }
171 0x1: BranchN::call(30, {{
172 if (Pstate<3:>)
173 R15 = (xc->readPC())<31:0>;
174 else
175 R15 = xc->readPC();
176 NNPC = R15 + disp;
177 }});
178 0x2: decode OP3 {
179 format IntOp {
180 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
181 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
182 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
183 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
184 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
185 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}});
186 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}});
187 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
188 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
189 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
190 0x0A: umul({{
191 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
192 Y = Rd<63:32>;
193 }});
194 0x0B: smul({{
|
195 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
| 195 Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
|
196 Y = Rd.sdw<63:32>;
197 }});
198 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
199 0x0D: udivx({{
200 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
201 else Rd.udw = Rs1.udw / Rs2_or_imm13;
202 }});
203 0x0E: udiv({{
204 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
205 else
206 {
207 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
208 if(Rd.udw >> 32 != 0)
209 Rd.udw = 0xFFFFFFFF;
210 }
211 }});
212 0x0F: sdiv({{
213 if(Rs2_or_imm13.sdw == 0)
214 fault = new DivisionByZero;
215 else
216 {
217 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
| 196 Y = Rd.sdw<63:32>;
197 }});
198 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
199 0x0D: udivx({{
200 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
201 else Rd.udw = Rs1.udw / Rs2_or_imm13;
202 }});
203 0x0E: udiv({{
204 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
205 else
206 {
207 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
208 if(Rd.udw >> 32 != 0)
209 Rd.udw = 0xFFFFFFFF;
210 }
211 }});
212 0x0F: sdiv({{
213 if(Rs2_or_imm13.sdw == 0)
214 fault = new DivisionByZero;
215 else
216 {
217 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
|
218 if(Rd.udw<63:31> != 0)
| 218 if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max())
|
219 Rd.udw = 0x7FFFFFFF;
| 219 Rd.udw = 0x7FFFFFFF;
|
220 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
221 Rd.udw = 0xFFFFFFFF80000000ULL;
| 220 else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min())
221 Rd.udw = ULL(0xFFFFFFFF80000000);
|
222 }
223 }});
224 }
225 format IntOpCc {
226 0x10: addcc({{
227 int64_t resTemp, val2 = Rs2_or_imm13;
228 Rd = resTemp = Rs1 + val2;}},
229 {{(Rs1<31:0> + val2<31:0>)<32:>}},
230 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
231 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
232 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
233 );
234 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
235 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
236 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
237 0x14: subcc({{
238 int64_t val2 = Rs2_or_imm13;
239 Rd = Rs1 - val2;}},
240 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
241 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
242 {{(~(Rs1<63:1> + (~val2)<63:1> +
243 (Rs1 | ~val2)<0:>))<63:>}},
244 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
245 );
246 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
247 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
248 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
249 0x18: addccc({{
250 int64_t resTemp, val2 = Rs2_or_imm13;
251 int64_t carryin = Ccr<0:0>;
252 Rd = resTemp = Rs1 + val2 + carryin;}},
253 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
254 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
| 222 }
223 }});
224 }
225 format IntOpCc {
226 0x10: addcc({{
227 int64_t resTemp, val2 = Rs2_or_imm13;
228 Rd = resTemp = Rs1 + val2;}},
229 {{(Rs1<31:0> + val2<31:0>)<32:>}},
230 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
231 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
232 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
233 );
234 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
235 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
236 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
237 0x14: subcc({{
238 int64_t val2 = Rs2_or_imm13;
239 Rd = Rs1 - val2;}},
240 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
241 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
242 {{(~(Rs1<63:1> + (~val2)<63:1> +
243 (Rs1 | ~val2)<0:>))<63:>}},
244 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
245 );
246 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
247 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
248 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
249 0x18: addccc({{
250 int64_t resTemp, val2 = Rs2_or_imm13;
251 int64_t carryin = Ccr<0:0>;
252 Rd = resTemp = Rs1 + val2 + carryin;}},
253 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
254 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
|
255 {{(Rs1<63:1> + val2<63:1> +
256 ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
| 255 {{((Rs1 & val2) | (~resTemp & (Rs1 | val2)))<63:>}},
|
257 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
258 );
259 0x1A: IntOpCcRes::umulcc({{
260 uint64_t resTemp;
261 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
262 Y = resTemp<63:32>;}});
263 0x1B: IntOpCcRes::smulcc({{
264 int64_t resTemp;
| 256 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
257 );
258 0x1A: IntOpCcRes::umulcc({{
259 uint64_t resTemp;
260 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
261 Y = resTemp<63:32>;}});
262 0x1B: IntOpCcRes::smulcc({{
263 int64_t resTemp;
|
265 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>;
| 264 Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
|
266 Y = resTemp<63:32>;}});
267 0x1C: subccc({{
268 int64_t resTemp, val2 = Rs2_or_imm13;
269 int64_t carryin = Ccr<0:0>;
270 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
| 265 Y = resTemp<63:32>;}});
266 0x1C: subccc({{
267 int64_t resTemp, val2 = Rs2_or_imm13;
268 int64_t carryin = Ccr<0:0>;
269 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
|
271 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
| 270 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<31:>}},
|
272 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
| 271 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
|
273 {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
| 272 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<63:>}},
|
274 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
275 );
276 0x1D: IntOpCcRes::udivxcc({{
277 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
278 else Rd = Rs1.udw / Rs2_or_imm13.udw;}});
279 0x1E: udivcc({{
280 uint32_t resTemp, val2 = Rs2_or_imm13.udw;
281 int32_t overflow = 0;
282 if(val2 == 0) fault = new DivisionByZero;
283 else
284 {
285 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
286 overflow = (resTemp<63:32> != 0);
287 if(overflow) Rd = resTemp = 0xFFFFFFFF;
288 else Rd = resTemp;
289 } }},
290 {{0}},
291 {{overflow}},
292 {{0}},
293 {{0}}
294 );
295 0x1F: sdivcc({{
296 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
297 bool overflow = false, underflow = false;
298 if(val2 == 0) fault = new DivisionByZero;
299 else
300 {
301 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
| 273 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
274 );
275 0x1D: IntOpCcRes::udivxcc({{
276 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
277 else Rd = Rs1.udw / Rs2_or_imm13.udw;}});
278 0x1E: udivcc({{
279 uint32_t resTemp, val2 = Rs2_or_imm13.udw;
280 int32_t overflow = 0;
281 if(val2 == 0) fault = new DivisionByZero;
282 else
283 {
284 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
285 overflow = (resTemp<63:32> != 0);
286 if(overflow) Rd = resTemp = 0xFFFFFFFF;
287 else Rd = resTemp;
288 } }},
289 {{0}},
290 {{overflow}},
291 {{0}},
292 {{0}}
293 );
294 0x1F: sdivcc({{
295 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
296 bool overflow = false, underflow = false;
297 if(val2 == 0) fault = new DivisionByZero;
298 else
299 {
300 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
|
302 overflow = (Rd<63:31> != 0);
303 underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF);
| 301 overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max());
302 underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min());
|
304 if(overflow) Rd = 0x7FFFFFFF;
| 303 if(overflow) Rd = 0x7FFFFFFF;
|
305 else if(underflow) Rd = 0xFFFFFFFF80000000ULL;
| 304 else if(underflow) Rd = ULL(0xFFFFFFFF80000000);
|
306 } }},
307 {{0}},
308 {{overflow || underflow}},
309 {{0}},
310 {{0}}
311 );
312 0x20: taddcc({{
313 int64_t resTemp, val2 = Rs2_or_imm13;
314 Rd = resTemp = Rs1 + val2;
315 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
316 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
317 {{overflow}},
318 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
319 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
320 );
321 0x21: tsubcc({{
322 int64_t resTemp, val2 = Rs2_or_imm13;
323 Rd = resTemp = Rs1 + val2;
324 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
325 {{(Rs1<31:0> + val2<31:0>)<32:0>}},
326 {{overflow}},
327 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
328 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
329 );
330 0x22: taddcctv({{
331 int64_t val2 = Rs2_or_imm13;
332 Rd = Rs1 + val2;
333 int32_t overflow = Rs1<1:0> || val2<1:0> ||
334 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
335 if(overflow) fault = new TagOverflow;}},
336 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
337 {{overflow}},
338 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
339 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}}
340 );
341 0x23: tsubcctv({{
342 int64_t resTemp, val2 = Rs2_or_imm13;
343 Rd = resTemp = Rs1 + val2;
344 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
345 if(overflow) fault = new TagOverflow;}},
346 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
347 {{overflow}},
348 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
349 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
350 );
351 0x24: mulscc({{
352 int64_t resTemp, multiplicand = Rs2_or_imm13;
353 int32_t multiplier = Rs1<31:0>;
354 int32_t savedLSB = Rs1<0:>;
355 multiplier = multiplier<31:1> |
356 ((Ccr<3:3> ^ Ccr<1:1>) << 32);
357 if(!Y<0:>)
358 multiplicand = 0;
359 Rd = resTemp = multiplicand + multiplier;
360 Y = Y<31:1> | (savedLSB << 31);}},
361 {{((multiplicand<31:0> + multiplier<31:0>)<32:0>)}},
362 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
363 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
364 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
365 );
366 }
367 format IntOp
368 {
369 0x25: decode X {
370 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
371 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
372 }
373 0x26: decode X {
374 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
375 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
376 }
377 0x27: decode X {
378 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
379 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
380 }
381 0x28: decode RS1 {
| 305 } }},
306 {{0}},
307 {{overflow || underflow}},
308 {{0}},
309 {{0}}
310 );
311 0x20: taddcc({{
312 int64_t resTemp, val2 = Rs2_or_imm13;
313 Rd = resTemp = Rs1 + val2;
314 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
315 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
316 {{overflow}},
317 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
318 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
319 );
320 0x21: tsubcc({{
321 int64_t resTemp, val2 = Rs2_or_imm13;
322 Rd = resTemp = Rs1 + val2;
323 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
324 {{(Rs1<31:0> + val2<31:0>)<32:0>}},
325 {{overflow}},
326 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
327 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
328 );
329 0x22: taddcctv({{
330 int64_t val2 = Rs2_or_imm13;
331 Rd = Rs1 + val2;
332 int32_t overflow = Rs1<1:0> || val2<1:0> ||
333 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
334 if(overflow) fault = new TagOverflow;}},
335 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
336 {{overflow}},
337 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
338 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}}
339 );
340 0x23: tsubcctv({{
341 int64_t resTemp, val2 = Rs2_or_imm13;
342 Rd = resTemp = Rs1 + val2;
343 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
344 if(overflow) fault = new TagOverflow;}},
345 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
346 {{overflow}},
347 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
348 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
349 );
350 0x24: mulscc({{
351 int64_t resTemp, multiplicand = Rs2_or_imm13;
352 int32_t multiplier = Rs1<31:0>;
353 int32_t savedLSB = Rs1<0:>;
354 multiplier = multiplier<31:1> |
355 ((Ccr<3:3> ^ Ccr<1:1>) << 32);
356 if(!Y<0:>)
357 multiplicand = 0;
358 Rd = resTemp = multiplicand + multiplier;
359 Y = Y<31:1> | (savedLSB << 31);}},
360 {{((multiplicand<31:0> + multiplier<31:0>)<32:0>)}},
361 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
362 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
363 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
364 );
365 }
366 format IntOp
367 {
368 0x25: decode X {
369 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
370 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
371 }
372 0x26: decode X {
373 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
374 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
375 }
376 0x27: decode X {
377 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
378 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
379 }
380 0x28: decode RS1 {
|
382 0x00: NoPriv::rdy({{Rd = Y;}});
| 381 0x00: NoPriv::rdy({{Rd = Y<31:0>;}});
|
383 //1 should cause an illegal instruction exception
384 0x02: NoPriv::rdccr({{Rd = Ccr;}});
385 0x03: NoPriv::rdasi({{Rd = Asi;}});
386 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
387 0x05: NoPriv::rdpc({{
388 if(Pstate<3:>)
389 Rd = (xc->readPC())<31:0>;
390 else
391 Rd = xc->readPC();}});
392 0x06: NoPriv::rdfprs({{
393 //Wait for all fpops to finish.
394 Rd = Fprs;
395 }});
396 //7-14 should cause an illegal instruction exception
397 0x0F: decode I {
398 0x0: Nop::stbar({{/*stuff*/}});
399 0x1: Nop::membar({{/*stuff*/}});
400 }
401 0x10: Priv::rdpcr({{Rd = Pcr;}});
402 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
403 //0x12 should cause an illegal instruction exception
404 0x13: NoPriv::rdgsr({{
405 if(Fprs<2:> == 0 || Pstate<4:> == 0)
406 Rd = Gsr;
407 else
408 fault = new FpDisabled;
409 }});
410 //0x14-0x15 should cause an illegal instruction exception
411 0x16: Priv::rdsoftint({{Rd = Softint;}});
412 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
413 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}});
414 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
415 0x1A: Priv::rdstrand_sts_reg({{
416 if(Pstate<2:> && !Hpstate<2:>)
417 Rd = StrandStsReg<0:>;
418 else
419 Rd = StrandStsReg;
420 }});
421 //0x1A is supposed to be reserved, but it reads the strand
422 //status register.
423 //0x1B-0x1F should cause an illegal instruction exception
424 }
425 0x29: decode RS1 {
426 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
427 0x01: HPriv::rdhprhtstate({{
428 if(Tl == 0)
429 return new IllegalInstruction;
430 Rd = Htstate;
431 }});
432 //0x02 should cause an illegal instruction exception
433 0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
434 //0x04 should cause an illegal instruction exception
435 0x05: HPriv::rdhprhtba({{Rd = Htba;}});
436 0x06: HPriv::rdhprhver({{Rd = Hver;}});
437 //0x07-0x1E should cause an illegal instruction exception
438 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
439 }
440 0x2A: decode RS1 {
441 0x00: Priv::rdprtpc({{
442 if(Tl == 0)
443 return new IllegalInstruction;
444 Rd = Tpc;
445 }});
446 0x01: Priv::rdprtnpc({{
447 if(Tl == 0)
448 return new IllegalInstruction;
449 Rd = Tnpc;
450 }});
451 0x02: Priv::rdprtstate({{
452 if(Tl == 0)
453 return new IllegalInstruction;
454 Rd = Tstate;
455 }});
456 0x03: Priv::rdprtt({{
457 if(Tl == 0)
458 return new IllegalInstruction;
459 Rd = Tt;
460 }});
461 0x04: Priv::rdprtick({{Rd = Tick;}});
462 0x05: Priv::rdprtba({{Rd = Tba;}});
463 0x06: Priv::rdprpstate({{Rd = Pstate;}});
464 0x07: Priv::rdprtl({{Rd = Tl;}});
465 0x08: Priv::rdprpil({{Rd = Pil;}});
466 0x09: Priv::rdprcwp({{Rd = Cwp;}});
467 0x0A: Priv::rdprcansave({{Rd = Cansave;}});
468 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});
469 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});
470 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}});
471 0x0E: Priv::rdprwstate({{Rd = Wstate;}});
472 //0x0F should cause an illegal instruction exception
473 0x10: Priv::rdprgl({{Rd = Gl;}});
474 //0x11-0x1F should cause an illegal instruction exception
475 }
476 0x2B: BasicOperate::flushw({{
477 if(NWindows - 2 - Cansave != 0)
478 {
479 if(Otherwin)
480 fault = new SpillNOther(4*Wstate<5:3>);
481 else
482 fault = new SpillNNormal(4*Wstate<2:0>);
483 }
484 }});
485 0x2C: decode MOVCC3
486 {
487 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
488 0x1: decode CC
489 {
490 0x0: movcci({{
491 if(passesCondition(Ccr<3:0>, COND4))
492 Rd = Rs2_or_imm11;
493 else
494 Rd = Rd;
495 }});
496 0x2: movccx({{
497 if(passesCondition(Ccr<7:4>, COND4))
498 Rd = Rs2_or_imm11;
499 else
500 Rd = Rd;
501 }});
502 }
503 }
504 0x2D: sdivx({{
505 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
506 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
507 }});
508 0x2E: decode RS1 {
509 0x0: IntOp::popc({{
510 int64_t count = 0;
511 uint64_t temp = Rs2_or_imm13;
512 //Count the 1s in the front 4bits until none are left
513 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
514 while(temp)
515 {
516 count += oneBits[temp & 0xF];
517 temp = temp >> 4;
518 }
519 Rd = count;
520 }});
521 }
522 0x2F: decode RCOND3
523 {
524 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
525 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
526 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
527 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
528 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
529 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
530 }
531 0x30: decode RD {
| 382 //1 should cause an illegal instruction exception
383 0x02: NoPriv::rdccr({{Rd = Ccr;}});
384 0x03: NoPriv::rdasi({{Rd = Asi;}});
385 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
386 0x05: NoPriv::rdpc({{
387 if(Pstate<3:>)
388 Rd = (xc->readPC())<31:0>;
389 else
390 Rd = xc->readPC();}});
391 0x06: NoPriv::rdfprs({{
392 //Wait for all fpops to finish.
393 Rd = Fprs;
394 }});
395 //7-14 should cause an illegal instruction exception
396 0x0F: decode I {
397 0x0: Nop::stbar({{/*stuff*/}});
398 0x1: Nop::membar({{/*stuff*/}});
399 }
400 0x10: Priv::rdpcr({{Rd = Pcr;}});
401 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
402 //0x12 should cause an illegal instruction exception
403 0x13: NoPriv::rdgsr({{
404 if(Fprs<2:> == 0 || Pstate<4:> == 0)
405 Rd = Gsr;
406 else
407 fault = new FpDisabled;
408 }});
409 //0x14-0x15 should cause an illegal instruction exception
410 0x16: Priv::rdsoftint({{Rd = Softint;}});
411 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
412 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}});
413 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
414 0x1A: Priv::rdstrand_sts_reg({{
415 if(Pstate<2:> && !Hpstate<2:>)
416 Rd = StrandStsReg<0:>;
417 else
418 Rd = StrandStsReg;
419 }});
420 //0x1A is supposed to be reserved, but it reads the strand
421 //status register.
422 //0x1B-0x1F should cause an illegal instruction exception
423 }
424 0x29: decode RS1 {
425 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
426 0x01: HPriv::rdhprhtstate({{
427 if(Tl == 0)
428 return new IllegalInstruction;
429 Rd = Htstate;
430 }});
431 //0x02 should cause an illegal instruction exception
432 0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
433 //0x04 should cause an illegal instruction exception
434 0x05: HPriv::rdhprhtba({{Rd = Htba;}});
435 0x06: HPriv::rdhprhver({{Rd = Hver;}});
436 //0x07-0x1E should cause an illegal instruction exception
437 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
438 }
439 0x2A: decode RS1 {
440 0x00: Priv::rdprtpc({{
441 if(Tl == 0)
442 return new IllegalInstruction;
443 Rd = Tpc;
444 }});
445 0x01: Priv::rdprtnpc({{
446 if(Tl == 0)
447 return new IllegalInstruction;
448 Rd = Tnpc;
449 }});
450 0x02: Priv::rdprtstate({{
451 if(Tl == 0)
452 return new IllegalInstruction;
453 Rd = Tstate;
454 }});
455 0x03: Priv::rdprtt({{
456 if(Tl == 0)
457 return new IllegalInstruction;
458 Rd = Tt;
459 }});
460 0x04: Priv::rdprtick({{Rd = Tick;}});
461 0x05: Priv::rdprtba({{Rd = Tba;}});
462 0x06: Priv::rdprpstate({{Rd = Pstate;}});
463 0x07: Priv::rdprtl({{Rd = Tl;}});
464 0x08: Priv::rdprpil({{Rd = Pil;}});
465 0x09: Priv::rdprcwp({{Rd = Cwp;}});
466 0x0A: Priv::rdprcansave({{Rd = Cansave;}});
467 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});
468 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});
469 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}});
470 0x0E: Priv::rdprwstate({{Rd = Wstate;}});
471 //0x0F should cause an illegal instruction exception
472 0x10: Priv::rdprgl({{Rd = Gl;}});
473 //0x11-0x1F should cause an illegal instruction exception
474 }
475 0x2B: BasicOperate::flushw({{
476 if(NWindows - 2 - Cansave != 0)
477 {
478 if(Otherwin)
479 fault = new SpillNOther(4*Wstate<5:3>);
480 else
481 fault = new SpillNNormal(4*Wstate<2:0>);
482 }
483 }});
484 0x2C: decode MOVCC3
485 {
486 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
487 0x1: decode CC
488 {
489 0x0: movcci({{
490 if(passesCondition(Ccr<3:0>, COND4))
491 Rd = Rs2_or_imm11;
492 else
493 Rd = Rd;
494 }});
495 0x2: movccx({{
496 if(passesCondition(Ccr<7:4>, COND4))
497 Rd = Rs2_or_imm11;
498 else
499 Rd = Rd;
500 }});
501 }
502 }
503 0x2D: sdivx({{
504 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
505 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
506 }});
507 0x2E: decode RS1 {
508 0x0: IntOp::popc({{
509 int64_t count = 0;
510 uint64_t temp = Rs2_or_imm13;
511 //Count the 1s in the front 4bits until none are left
512 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
513 while(temp)
514 {
515 count += oneBits[temp & 0xF];
516 temp = temp >> 4;
517 }
518 Rd = count;
519 }});
520 }
521 0x2F: decode RCOND3
522 {
523 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
524 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
525 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
526 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
527 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
528 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
529 }
530 0x30: decode RD {
|
532 0x00: NoPriv::wry({{Y = Rs1 ^ Rs2_or_imm13;}});
| 531 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}});
|
533 //0x01 should cause an illegal instruction exception
534 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
535 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
536 //0x04-0x05 should cause an illegal instruction exception
537 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
538 //0x07-0x0E should cause an illegal instruction exception
539 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
540 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
541 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
542 //0x12 should cause an illegal instruction exception
543 0x13: NoPriv::wrgsr({{
544 if(Fprs<2:> == 0 || Pstate<4:> == 0)
545 return new FpDisabled;
546 Gsr = Rs1 ^ Rs2_or_imm13;
547 }});
548 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
549 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});
550 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
551 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}});
552 0x18: NoPriv::wrstick({{
553 if(!Hpstate<2:>)
554 return new IllegalInstruction;
555 Stick = Rs1 ^ Rs2_or_imm13;
556 }});
557 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}});
558 0x1A: Priv::wrstrand_sts_reg({{
559 if(Pstate<2:> && !Hpstate<2:>)
560 StrandStsReg = StrandStsReg<63:1> |
561 (Rs1 ^ Rs2_or_imm13)<0:>;
562 else
563 StrandStsReg = Rs1 ^ Rs2_or_imm13;
564 }});
565 //0x1A is supposed to be reserved, but it writes the strand
566 //status register.
567 //0x1B-0x1F should cause an illegal instruction exception
568 }
569 0x31: decode FCN {
570 0x0: Priv::saved({{
571 assert(Cansave < NWindows - 2);
572 assert(Otherwin || Canrestore);
573 Cansave = Cansave + 1;
574 if(Otherwin == 0)
575 Canrestore = Canrestore - 1;
576 else
577 Otherwin = Otherwin - 1;
578 }});
579 0x1: Priv::restored({{
580 assert(Cansave || Otherwin);
581 assert(Canrestore < NWindows - 2);
582 Canrestore = Canrestore + 1;
583 if(Otherwin == 0)
584 Cansave = Cansave - 1;
585 else
586 Otherwin = Otherwin - 1;
587
588 if(Cleanwin < NWindows - 1)
589 Cleanwin = Cleanwin + 1;
590 }});
591 }
592 0x32: decode RD {
593 0x00: Priv::wrprtpc({{
594 if(Tl == 0)
595 return new IllegalInstruction;
596 else
597 Tpc = Rs1 ^ Rs2_or_imm13;
598 }});
599 0x01: Priv::wrprtnpc({{
600 if(Tl == 0)
601 return new IllegalInstruction;
602 else
603 Tnpc = Rs1 ^ Rs2_or_imm13;
604 }});
605 0x02: Priv::wrprtstate({{
606 if(Tl == 0)
607 return new IllegalInstruction;
608 else
609 Tstate = Rs1 ^ Rs2_or_imm13;
610 }});
611 0x03: Priv::wrprtt({{
612 if(Tl == 0)
613 return new IllegalInstruction;
614 else
615 Tt = Rs1 ^ Rs2_or_imm13;
616 }});
617 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
618 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
619 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
620 0x07: Priv::wrprtl({{
621 if(Pstate<2:> && !Hpstate<2:>)
622 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
623 else
624 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);
625 }});
626 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
627 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
628 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
629 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
630 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
631 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
632 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
633 //0x0F should cause an illegal instruction exception
634 0x10: Priv::wrprgl({{
635 if(Pstate<2:> && !Hpstate<2:>)
636 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL);
637 else
638 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
639 }});
640 //0x11-0x1F should cause an illegal instruction exception
641 }
642 0x33: decode RD {
643 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
644 0x01: HPriv::wrhprhtstate({{
645 if(Tl == 0)
646 return new IllegalInstruction;
647 Htstate = Rs1 ^ Rs2_or_imm13;
648 }});
649 //0x02 should cause an illegal instruction exception
650 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
651 //0x04 should cause an illegal instruction exception
652 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
653 //0x06-0x01D should cause an illegal instruction exception
654 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
655 }
656 0x34: decode OPF{
657 format BasicOperate{
658 0x01: fmovs({{
659 Frds.uw = Frs2s.uw;
660 //fsr.ftt = fsr.cexc = 0
661 Fsr &= ~(7 << 14);
662 Fsr &= ~(0x1F);
663 }});
664 0x02: fmovd({{
665 Frd.udw = Frs2.udw;
666 //fsr.ftt = fsr.cexc = 0
667 Fsr &= ~(7 << 14);
668 Fsr &= ~(0x1F);
669 }});
| 532 //0x01 should cause an illegal instruction exception
533 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
534 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
535 //0x04-0x05 should cause an illegal instruction exception
536 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
537 //0x07-0x0E should cause an illegal instruction exception
538 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
539 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
540 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
541 //0x12 should cause an illegal instruction exception
542 0x13: NoPriv::wrgsr({{
543 if(Fprs<2:> == 0 || Pstate<4:> == 0)
544 return new FpDisabled;
545 Gsr = Rs1 ^ Rs2_or_imm13;
546 }});
547 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
548 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});
549 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
550 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}});
551 0x18: NoPriv::wrstick({{
552 if(!Hpstate<2:>)
553 return new IllegalInstruction;
554 Stick = Rs1 ^ Rs2_or_imm13;
555 }});
556 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}});
557 0x1A: Priv::wrstrand_sts_reg({{
558 if(Pstate<2:> && !Hpstate<2:>)
559 StrandStsReg = StrandStsReg<63:1> |
560 (Rs1 ^ Rs2_or_imm13)<0:>;
561 else
562 StrandStsReg = Rs1 ^ Rs2_or_imm13;
563 }});
564 //0x1A is supposed to be reserved, but it writes the strand
565 //status register.
566 //0x1B-0x1F should cause an illegal instruction exception
567 }
568 0x31: decode FCN {
569 0x0: Priv::saved({{
570 assert(Cansave < NWindows - 2);
571 assert(Otherwin || Canrestore);
572 Cansave = Cansave + 1;
573 if(Otherwin == 0)
574 Canrestore = Canrestore - 1;
575 else
576 Otherwin = Otherwin - 1;
577 }});
578 0x1: Priv::restored({{
579 assert(Cansave || Otherwin);
580 assert(Canrestore < NWindows - 2);
581 Canrestore = Canrestore + 1;
582 if(Otherwin == 0)
583 Cansave = Cansave - 1;
584 else
585 Otherwin = Otherwin - 1;
586
587 if(Cleanwin < NWindows - 1)
588 Cleanwin = Cleanwin + 1;
589 }});
590 }
591 0x32: decode RD {
592 0x00: Priv::wrprtpc({{
593 if(Tl == 0)
594 return new IllegalInstruction;
595 else
596 Tpc = Rs1 ^ Rs2_or_imm13;
597 }});
598 0x01: Priv::wrprtnpc({{
599 if(Tl == 0)
600 return new IllegalInstruction;
601 else
602 Tnpc = Rs1 ^ Rs2_or_imm13;
603 }});
604 0x02: Priv::wrprtstate({{
605 if(Tl == 0)
606 return new IllegalInstruction;
607 else
608 Tstate = Rs1 ^ Rs2_or_imm13;
609 }});
610 0x03: Priv::wrprtt({{
611 if(Tl == 0)
612 return new IllegalInstruction;
613 else
614 Tt = Rs1 ^ Rs2_or_imm13;
615 }});
616 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
617 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
618 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
619 0x07: Priv::wrprtl({{
620 if(Pstate<2:> && !Hpstate<2:>)
621 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
622 else
623 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);
624 }});
625 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
626 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
627 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
628 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
629 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
630 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
631 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
632 //0x0F should cause an illegal instruction exception
633 0x10: Priv::wrprgl({{
634 if(Pstate<2:> && !Hpstate<2:>)
635 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL);
636 else
637 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
638 }});
639 //0x11-0x1F should cause an illegal instruction exception
640 }
641 0x33: decode RD {
642 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
643 0x01: HPriv::wrhprhtstate({{
644 if(Tl == 0)
645 return new IllegalInstruction;
646 Htstate = Rs1 ^ Rs2_or_imm13;
647 }});
648 //0x02 should cause an illegal instruction exception
649 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
650 //0x04 should cause an illegal instruction exception
651 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
652 //0x06-0x01D should cause an illegal instruction exception
653 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
654 }
655 0x34: decode OPF{
656 format BasicOperate{
657 0x01: fmovs({{
658 Frds.uw = Frs2s.uw;
659 //fsr.ftt = fsr.cexc = 0
660 Fsr &= ~(7 << 14);
661 Fsr &= ~(0x1F);
662 }});
663 0x02: fmovd({{
664 Frd.udw = Frs2.udw;
665 //fsr.ftt = fsr.cexc = 0
666 Fsr &= ~(7 << 14);
667 Fsr &= ~(0x1F);
668 }});
|
670 0x03: Trap::fmovq({{fault = new FpDisabled;}});
| 669 0x03: Trap::fmovq({{fault = new FpExceptionOther;}});
|
671 0x05: fnegs({{
672 Frds.uw = Frs2s.uw ^ (1UL << 31);
673 //fsr.ftt = fsr.cexc = 0
674 Fsr &= ~(7 << 14);
675 Fsr &= ~(0x1F);
676 }});
677 0x06: fnegd({{
678 Frd.udw = Frs2.udw ^ (1ULL << 63);
679 //fsr.ftt = fsr.cexc = 0
680 Fsr &= ~(7 << 14);
681 Fsr &= ~(0x1F);
682 }});
683 0x07: Trap::fnegq({{fault = new FpDisabled;}});
684 0x09: fabss({{
685 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;
686 //fsr.ftt = fsr.cexc = 0
687 Fsr &= ~(7 << 14);
688 Fsr &= ~(0x1F);
689 }});
690 0x0A: fabsd({{
691 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;
692 //fsr.ftt = fsr.cexc = 0
693 Fsr &= ~(7 << 14);
694 Fsr &= ~(0x1F);
695 }});
696 0x0B: Trap::fabsq({{fault = new FpDisabled;}});
| 670 0x05: fnegs({{
671 Frds.uw = Frs2s.uw ^ (1UL << 31);
672 //fsr.ftt = fsr.cexc = 0
673 Fsr &= ~(7 << 14);
674 Fsr &= ~(0x1F);
675 }});
676 0x06: fnegd({{
677 Frd.udw = Frs2.udw ^ (1ULL << 63);
678 //fsr.ftt = fsr.cexc = 0
679 Fsr &= ~(7 << 14);
680 Fsr &= ~(0x1F);
681 }});
682 0x07: Trap::fnegq({{fault = new FpDisabled;}});
683 0x09: fabss({{
684 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;
685 //fsr.ftt = fsr.cexc = 0
686 Fsr &= ~(7 << 14);
687 Fsr &= ~(0x1F);
688 }});
689 0x0A: fabsd({{
690 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;
691 //fsr.ftt = fsr.cexc = 0
692 Fsr &= ~(7 << 14);
693 Fsr &= ~(0x1F);
694 }});
695 0x0B: Trap::fabsq({{fault = new FpDisabled;}});
|
697 0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}});
698 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}});
| 696 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}});
697 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}});
|
699 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
700 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
701 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
702 0x43: Trap::faddq({{fault = new FpDisabled;}});
703 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
704 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
705 0x47: Trap::fsubq({{fault = new FpDisabled;}});
706 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
707 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
708 0x4B: Trap::fmulq({{fault = new FpDisabled;}});
709 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
710 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
711 0x4F: Trap::fdivq({{fault = new FpDisabled;}});
712 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
713 0x6E: Trap::fdmulq({{fault = new FpDisabled;}});
714 0x81: fstox({{
715 Frd.df = (double)static_cast<int64_t>(Frs2s.sf);
716 }});
717 0x82: fdtox({{
718 Frd.df = (double)static_cast<int64_t>(Frs2.df);
719 }});
720 0x83: Trap::fqtox({{fault = new FpDisabled;}});
721 0x84: fxtos({{
722 Frds.sf = static_cast<float>((int64_t)Frs2.df);
723 }});
724 0x88: fxtod({{
725 Frd.df = static_cast<double>((int64_t)Frs2.df);
726 }});
727 0x8C: Trap::fxtoq({{fault = new FpDisabled;}});
728 0xC4: fitos({{
729 Frds.sf = static_cast<float>((int32_t)Frs2s.sf);
730 }});
731 0xC6: fdtos({{Frds.sf = Frs2.df;}});
732 0xC7: Trap::fqtos({{fault = new FpDisabled;}});
733 0xC8: fitod({{
734 Frd.df = static_cast<double>((int32_t)Frs2s.sf);
735 }});
736 0xC9: fstod({{Frd.df = Frs2s.sf;}});
737 0xCB: Trap::fqtod({{fault = new FpDisabled;}});
738 0xCC: Trap::fitoq({{fault = new FpDisabled;}});
739 0xCD: Trap::fstoq({{fault = new FpDisabled;}});
740 0xCE: Trap::fdtoq({{fault = new FpDisabled;}});
741 0xD1: fstoi({{
742 Frds.sf = (float)static_cast<int32_t>(Frs2s.sf);
743 }});
744 0xD2: fdtoi({{
745 Frds.sf = (float)static_cast<int32_t>(Frs2.df);
746 }});
747 0xD3: Trap::fqtoi({{fault = new FpDisabled;}});
748 default: Trap::fpop1({{fault = new FpDisabled;}});
749 }
750 }
751 0x35: Trap::fpop2({{fault = new FpDisabled;}});
752 //This used to be just impdep1, but now it's a whole bunch
753 //of instructions
754 0x36: decode OPF{
755 0x00: Trap::edge8({{fault = new IllegalInstruction;}});
756 0x01: Trap::edge8n({{fault = new IllegalInstruction;}});
757 0x02: Trap::edge8l({{fault = new IllegalInstruction;}});
758 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}});
759 0x04: Trap::edge16({{fault = new IllegalInstruction;}});
760 0x05: Trap::edge16n({{fault = new IllegalInstruction;}});
761 0x06: Trap::edge16l({{fault = new IllegalInstruction;}});
762 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}});
763 0x08: Trap::edge32({{fault = new IllegalInstruction;}});
764 0x09: Trap::edge32n({{fault = new IllegalInstruction;}});
765 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}});
766 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}});
767 0x10: Trap::array8({{fault = new IllegalInstruction;}});
768 0x12: Trap::array16({{fault = new IllegalInstruction;}});
769 0x14: Trap::array32({{fault = new IllegalInstruction;}});
770 0x18: BasicOperate::alignaddr({{
771 uint64_t sum = Rs1 + Rs2;
772 Rd = sum & ~7;
773 Gsr = (Gsr & ~7) | (sum & 7);
774 }});
775 0x19: Trap::bmask({{fault = new IllegalInstruction;}});
776 0x1A: BasicOperate::alignaddresslittle({{
777 uint64_t sum = Rs1 + Rs2;
778 Rd = sum & ~7;
779 Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
780 }});
781 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}});
782 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}});
783 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}});
784 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}});
785 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}});
786 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}});
787 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}});
788 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}});
789 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}});
790 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}});
791 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}});
792 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}});
793 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}});
794 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}});
795 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}});
796 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
797 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
798 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
799 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
800 0x48: BasicOperate::faligndata({{
801 uint64_t msbX = Frs1.udw;
802 uint64_t lsbX = Frs2.udw;
803 //Some special cases need to be split out, first
804 //because they're the most likely to be used, and
805 //second because otherwise, we end up shifting by
806 //greater than the width of the type being shifted,
807 //namely 64, which produces undefined results according
808 //to the C standard.
809 switch(Gsr<2:0>)
810 {
811 case 0:
812 Frd.udw = msbX;
813 break;
814 case 8:
815 Frd.udw = lsbX;
816 break;
817 default:
818 uint64_t msbShift = Gsr<2:0> * 8;
819 uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
820 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
821 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
822 Frd.udw = ((msbX & msbMask) << msbShift) |
823 ((lsbX & lsbMask) >> lsbShift);
824 }
825 }});
826 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
827 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}});
828 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}});
829 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}});
830 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}});
831 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}});
832 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}});
833 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}});
834 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}});
835 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}});
836 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}});
837 0x60: BasicOperate::fzero({{Frd.df = 0;}});
838 0x61: BasicOperate::fzeros({{Frds.sf = 0;}});
839 0x62: Trap::fnor({{fault = new IllegalInstruction;}});
840 0x63: Trap::fnors({{fault = new IllegalInstruction;}});
841 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}});
842 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}});
843 0x66: BasicOperate::fnot2({{
844 Frd.df = (double)(~((uint64_t)Frs2.df));
845 }});
846 0x67: BasicOperate::fnot2s({{
847 Frds.sf = (float)(~((uint32_t)Frs2s.sf));
848 }});
849 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}});
850 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}});
851 0x6A: BasicOperate::fnot1({{
852 Frd.df = (double)(~((uint64_t)Frs1.df));
853 }});
854 0x6B: BasicOperate::fnot1s({{
855 Frds.sf = (float)(~((uint32_t)Frs1s.sf));
856 }});
857 0x6C: Trap::fxor({{fault = new IllegalInstruction;}});
858 0x6D: Trap::fxors({{fault = new IllegalInstruction;}});
859 0x6E: Trap::fnand({{fault = new IllegalInstruction;}});
860 0x6F: Trap::fnands({{fault = new IllegalInstruction;}});
861 0x70: Trap::fand({{fault = new IllegalInstruction;}});
862 0x71: Trap::fands({{fault = new IllegalInstruction;}});
863 0x72: Trap::fxnor({{fault = new IllegalInstruction;}});
864 0x73: Trap::fxnors({{fault = new IllegalInstruction;}});
865 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}});
| 698 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
699 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
700 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
701 0x43: Trap::faddq({{fault = new FpDisabled;}});
702 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
703 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
704 0x47: Trap::fsubq({{fault = new FpDisabled;}});
705 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
706 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
707 0x4B: Trap::fmulq({{fault = new FpDisabled;}});
708 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
709 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
710 0x4F: Trap::fdivq({{fault = new FpDisabled;}});
711 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
712 0x6E: Trap::fdmulq({{fault = new FpDisabled;}});
713 0x81: fstox({{
714 Frd.df = (double)static_cast<int64_t>(Frs2s.sf);
715 }});
716 0x82: fdtox({{
717 Frd.df = (double)static_cast<int64_t>(Frs2.df);
718 }});
719 0x83: Trap::fqtox({{fault = new FpDisabled;}});
720 0x84: fxtos({{
721 Frds.sf = static_cast<float>((int64_t)Frs2.df);
722 }});
723 0x88: fxtod({{
724 Frd.df = static_cast<double>((int64_t)Frs2.df);
725 }});
726 0x8C: Trap::fxtoq({{fault = new FpDisabled;}});
727 0xC4: fitos({{
728 Frds.sf = static_cast<float>((int32_t)Frs2s.sf);
729 }});
730 0xC6: fdtos({{Frds.sf = Frs2.df;}});
731 0xC7: Trap::fqtos({{fault = new FpDisabled;}});
732 0xC8: fitod({{
733 Frd.df = static_cast<double>((int32_t)Frs2s.sf);
734 }});
735 0xC9: fstod({{Frd.df = Frs2s.sf;}});
736 0xCB: Trap::fqtod({{fault = new FpDisabled;}});
737 0xCC: Trap::fitoq({{fault = new FpDisabled;}});
738 0xCD: Trap::fstoq({{fault = new FpDisabled;}});
739 0xCE: Trap::fdtoq({{fault = new FpDisabled;}});
740 0xD1: fstoi({{
741 Frds.sf = (float)static_cast<int32_t>(Frs2s.sf);
742 }});
743 0xD2: fdtoi({{
744 Frds.sf = (float)static_cast<int32_t>(Frs2.df);
745 }});
746 0xD3: Trap::fqtoi({{fault = new FpDisabled;}});
747 default: Trap::fpop1({{fault = new FpDisabled;}});
748 }
749 }
750 0x35: Trap::fpop2({{fault = new FpDisabled;}});
751 //This used to be just impdep1, but now it's a whole bunch
752 //of instructions
753 0x36: decode OPF{
754 0x00: Trap::edge8({{fault = new IllegalInstruction;}});
755 0x01: Trap::edge8n({{fault = new IllegalInstruction;}});
756 0x02: Trap::edge8l({{fault = new IllegalInstruction;}});
757 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}});
758 0x04: Trap::edge16({{fault = new IllegalInstruction;}});
759 0x05: Trap::edge16n({{fault = new IllegalInstruction;}});
760 0x06: Trap::edge16l({{fault = new IllegalInstruction;}});
761 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}});
762 0x08: Trap::edge32({{fault = new IllegalInstruction;}});
763 0x09: Trap::edge32n({{fault = new IllegalInstruction;}});
764 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}});
765 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}});
766 0x10: Trap::array8({{fault = new IllegalInstruction;}});
767 0x12: Trap::array16({{fault = new IllegalInstruction;}});
768 0x14: Trap::array32({{fault = new IllegalInstruction;}});
769 0x18: BasicOperate::alignaddr({{
770 uint64_t sum = Rs1 + Rs2;
771 Rd = sum & ~7;
772 Gsr = (Gsr & ~7) | (sum & 7);
773 }});
774 0x19: Trap::bmask({{fault = new IllegalInstruction;}});
775 0x1A: BasicOperate::alignaddresslittle({{
776 uint64_t sum = Rs1 + Rs2;
777 Rd = sum & ~7;
778 Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
779 }});
780 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}});
781 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}});
782 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}});
783 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}});
784 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}});
785 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}});
786 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}});
787 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}});
788 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}});
789 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}});
790 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}});
791 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}});
792 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}});
793 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}});
794 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}});
795 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
796 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
797 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
798 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
799 0x48: BasicOperate::faligndata({{
800 uint64_t msbX = Frs1.udw;
801 uint64_t lsbX = Frs2.udw;
802 //Some special cases need to be split out, first
803 //because they're the most likely to be used, and
804 //second because otherwise, we end up shifting by
805 //greater than the width of the type being shifted,
806 //namely 64, which produces undefined results according
807 //to the C standard.
808 switch(Gsr<2:0>)
809 {
810 case 0:
811 Frd.udw = msbX;
812 break;
813 case 8:
814 Frd.udw = lsbX;
815 break;
816 default:
817 uint64_t msbShift = Gsr<2:0> * 8;
818 uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
819 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
820 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
821 Frd.udw = ((msbX & msbMask) << msbShift) |
822 ((lsbX & lsbMask) >> lsbShift);
823 }
824 }});
825 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
826 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}});
827 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}});
828 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}});
829 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}});
830 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}});
831 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}});
832 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}});
833 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}});
834 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}});
835 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}});
836 0x60: BasicOperate::fzero({{Frd.df = 0;}});
837 0x61: BasicOperate::fzeros({{Frds.sf = 0;}});
838 0x62: Trap::fnor({{fault = new IllegalInstruction;}});
839 0x63: Trap::fnors({{fault = new IllegalInstruction;}});
840 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}});
841 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}});
842 0x66: BasicOperate::fnot2({{
843 Frd.df = (double)(~((uint64_t)Frs2.df));
844 }});
845 0x67: BasicOperate::fnot2s({{
846 Frds.sf = (float)(~((uint32_t)Frs2s.sf));
847 }});
848 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}});
849 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}});
850 0x6A: BasicOperate::fnot1({{
851 Frd.df = (double)(~((uint64_t)Frs1.df));
852 }});
853 0x6B: BasicOperate::fnot1s({{
854 Frds.sf = (float)(~((uint32_t)Frs1s.sf));
855 }});
856 0x6C: Trap::fxor({{fault = new IllegalInstruction;}});
857 0x6D: Trap::fxors({{fault = new IllegalInstruction;}});
858 0x6E: Trap::fnand({{fault = new IllegalInstruction;}});
859 0x6F: Trap::fnands({{fault = new IllegalInstruction;}});
860 0x70: Trap::fand({{fault = new IllegalInstruction;}});
861 0x71: Trap::fands({{fault = new IllegalInstruction;}});
862 0x72: Trap::fxnor({{fault = new IllegalInstruction;}});
863 0x73: Trap::fxnors({{fault = new IllegalInstruction;}});
864 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}});
|
866 0x75: BasicOperate::fsrc1s({{Frd.uw = Frs1.uw;}});
| 865 0x75: BasicOperate::fsrc1s({{Frds.uw = Frs1s.uw;}});
|
867 0x76: Trap::fornot2({{fault = new IllegalInstruction;}});
868 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}});
869 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}});
| 866 0x76: Trap::fornot2({{fault = new IllegalInstruction;}});
867 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}});
868 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}});
|
870 0x79: BasicOperate::fsrc2s({{Frd.uw = Frs2.uw;}});
| 869 0x79: BasicOperate::fsrc2s({{Frds.uw = Frs2s.uw;}});
|
871 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}});
872 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}});
873 0x7C: Trap::for({{fault = new IllegalInstruction;}});
874 0x7D: Trap::fors({{fault = new IllegalInstruction;}});
875 0x7E: Trap::fone({{fault = new IllegalInstruction;}});
876 0x7F: Trap::fones({{fault = new IllegalInstruction;}});
877 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
878 0x81: Trap::siam({{fault = new IllegalInstruction;}});
879 }
880 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
881 0x38: Branch::jmpl({{
882 Addr target = Rs1 + Rs2_or_imm13;
883 if(target & 0x3)
884 fault = new MemAddressNotAligned;
885 else
886 {
887 if (Pstate<3:>)
| 870 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}});
871 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}});
872 0x7C: Trap::for({{fault = new IllegalInstruction;}});
873 0x7D: Trap::fors({{fault = new IllegalInstruction;}});
874 0x7E: Trap::fone({{fault = new IllegalInstruction;}});
875 0x7F: Trap::fones({{fault = new IllegalInstruction;}});
876 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
877 0x81: Trap::siam({{fault = new IllegalInstruction;}});
878 }
879 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
880 0x38: Branch::jmpl({{
881 Addr target = Rs1 + Rs2_or_imm13;
882 if(target & 0x3)
883 fault = new MemAddressNotAligned;
884 else
885 {
886 if (Pstate<3:>)
|
888 (Rd = xc->readPC())<31:0>;
| 887 Rd = (xc->readPC())<31:0>;
|
889 else
890 Rd = xc->readPC();
891 NNPC = target;
892 }
893 }});
894 0x39: Branch::return({{
895 Addr target = Rs1 + Rs2_or_imm13;
896 if(fault == NoFault)
897 {
898 //Check for fills which are higher priority than alignment
899 //faults.
900 if(Canrestore == 0)
901 {
902 if(Otherwin)
903 fault = new FillNOther(4*Wstate<5:3>);
904 else
905 fault = new FillNNormal(4*Wstate<2:0>);
906 }
907 //Check for alignment faults
908 else if(target & 0x3)
909 fault = new MemAddressNotAligned;
910 else
911 {
912 NNPC = target;
913 Cwp = (Cwp - 1 + NWindows) % NWindows;
914 Cansave = Cansave + 1;
915 Canrestore = Canrestore - 1;
916 }
917 }
918 }});
919 0x3A: decode CC
920 {
921 0x0: Trap::tcci({{
922 if(passesCondition(Ccr<3:0>, COND2))
923 {
924#if FULL_SYSTEM
925 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
926 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
927 fault = new TrapInstruction(lTrapNum);
928#else
929 DPRINTF(Sparc, "The syscall number is %d\n", R1);
930 xc->syscall(R1);
931#endif
932 }
933 }}, IsSerializeAfter, IsNonSpeculative);
934 0x2: Trap::tccx({{
935 if(passesCondition(Ccr<7:4>, COND2))
936 {
937#if FULL_SYSTEM
938 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
939 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
940 fault = new TrapInstruction(lTrapNum);
941#else
942 DPRINTF(Sparc, "The syscall number is %d\n", R1);
943 xc->syscall(R1);
944#endif
945 }
946 }}, IsSerializeAfter, IsNonSpeculative);
947 }
948 0x3B: Nop::flush({{/*Instruction memory flush*/}});
949 0x3C: save({{
950 if(Cansave == 0)
951 {
952 if(Otherwin)
953 fault = new SpillNOther(4*Wstate<5:3>);
954 else
955 fault = new SpillNNormal(4*Wstate<2:0>);
956 }
957 else if(Cleanwin - Canrestore == 0)
958 {
959 fault = new CleanWindow;
960 }
961 else
962 {
963 Cwp = (Cwp + 1) % NWindows;
964 Rd_next = Rs1 + Rs2_or_imm13;
965 Cansave = Cansave - 1;
966 Canrestore = Canrestore + 1;
967 }
968 }});
969 0x3D: restore({{
970 if(Canrestore == 0)
971 {
972 if(Otherwin)
973 fault = new FillNOther(4*Wstate<5:3>);
974 else
975 fault = new FillNNormal(4*Wstate<2:0>);
976 }
977 else
978 {
979 Cwp = (Cwp - 1 + NWindows) % NWindows;
980 Rd_prev = Rs1 + Rs2_or_imm13;
981 Cansave = Cansave + 1;
982 Canrestore = Canrestore - 1;
983 }
984 }});
985 0x3E: decode FCN {
986 0x0: Priv::done({{
987 if(Tl == 0)
988 return new IllegalInstruction;
989
990 Cwp = Tstate<4:0>;
991 Pstate = Tstate<20:8>;
992 Asi = Tstate<31:24>;
993 Ccr = Tstate<39:32>;
994 Gl = Tstate<42:40>;
995 Hpstate = Htstate;
996 NPC = Tnpc;
997 NNPC = Tnpc + 4;
998 Tl = Tl - 1;
999 }});
1000 0x1: Priv::retry({{
1001 if(Tl == 0)
1002 return new IllegalInstruction;
1003 Cwp = Tstate<4:0>;
1004 Pstate = Tstate<20:8>;
1005 Asi = Tstate<31:24>;
1006 Ccr = Tstate<39:32>;
1007 Gl = Tstate<42:40>;
1008 Hpstate = Htstate;
1009 NPC = Tpc;
1010 NNPC = Tnpc;
1011 Tl = Tl - 1;
1012 }});
1013 }
1014 }
1015 }
1016 0x3: decode OP3 {
1017 format Load {
1018 0x00: lduw({{Rd = Mem.uw;}});
1019 0x01: ldub({{Rd = Mem.ub;}});
1020 0x02: lduh({{Rd = Mem.uhw;}});
1021 0x03: ldtw({{
1022 uint64_t val = Mem.udw;
1023 RdLow = val<31:0>;
1024 RdHigh = val<63:32>;
1025 }});
1026 }
1027 format Store {
1028 0x04: stw({{Mem.uw = Rd.sw;}});
1029 0x05: stb({{Mem.ub = Rd.sb;}});
1030 0x06: sth({{Mem.uhw = Rd.shw;}});
1031 0x07: sttw({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
1032 }
1033 format Load {
1034 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
1035 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
1036 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
1037 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
1038 }
1039 0x0D: LoadStore::ldstub(
| 888 else
889 Rd = xc->readPC();
890 NNPC = target;
891 }
892 }});
893 0x39: Branch::return({{
894 Addr target = Rs1 + Rs2_or_imm13;
895 if(fault == NoFault)
896 {
897 //Check for fills which are higher priority than alignment
898 //faults.
899 if(Canrestore == 0)
900 {
901 if(Otherwin)
902 fault = new FillNOther(4*Wstate<5:3>);
903 else
904 fault = new FillNNormal(4*Wstate<2:0>);
905 }
906 //Check for alignment faults
907 else if(target & 0x3)
908 fault = new MemAddressNotAligned;
909 else
910 {
911 NNPC = target;
912 Cwp = (Cwp - 1 + NWindows) % NWindows;
913 Cansave = Cansave + 1;
914 Canrestore = Canrestore - 1;
915 }
916 }
917 }});
918 0x3A: decode CC
919 {
920 0x0: Trap::tcci({{
921 if(passesCondition(Ccr<3:0>, COND2))
922 {
923#if FULL_SYSTEM
924 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
925 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
926 fault = new TrapInstruction(lTrapNum);
927#else
928 DPRINTF(Sparc, "The syscall number is %d\n", R1);
929 xc->syscall(R1);
930#endif
931 }
932 }}, IsSerializeAfter, IsNonSpeculative);
933 0x2: Trap::tccx({{
934 if(passesCondition(Ccr<7:4>, COND2))
935 {
936#if FULL_SYSTEM
937 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
938 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
939 fault = new TrapInstruction(lTrapNum);
940#else
941 DPRINTF(Sparc, "The syscall number is %d\n", R1);
942 xc->syscall(R1);
943#endif
944 }
945 }}, IsSerializeAfter, IsNonSpeculative);
946 }
947 0x3B: Nop::flush({{/*Instruction memory flush*/}});
948 0x3C: save({{
949 if(Cansave == 0)
950 {
951 if(Otherwin)
952 fault = new SpillNOther(4*Wstate<5:3>);
953 else
954 fault = new SpillNNormal(4*Wstate<2:0>);
955 }
956 else if(Cleanwin - Canrestore == 0)
957 {
958 fault = new CleanWindow;
959 }
960 else
961 {
962 Cwp = (Cwp + 1) % NWindows;
963 Rd_next = Rs1 + Rs2_or_imm13;
964 Cansave = Cansave - 1;
965 Canrestore = Canrestore + 1;
966 }
967 }});
968 0x3D: restore({{
969 if(Canrestore == 0)
970 {
971 if(Otherwin)
972 fault = new FillNOther(4*Wstate<5:3>);
973 else
974 fault = new FillNNormal(4*Wstate<2:0>);
975 }
976 else
977 {
978 Cwp = (Cwp - 1 + NWindows) % NWindows;
979 Rd_prev = Rs1 + Rs2_or_imm13;
980 Cansave = Cansave + 1;
981 Canrestore = Canrestore - 1;
982 }
983 }});
984 0x3E: decode FCN {
985 0x0: Priv::done({{
986 if(Tl == 0)
987 return new IllegalInstruction;
988
989 Cwp = Tstate<4:0>;
990 Pstate = Tstate<20:8>;
991 Asi = Tstate<31:24>;
992 Ccr = Tstate<39:32>;
993 Gl = Tstate<42:40>;
994 Hpstate = Htstate;
995 NPC = Tnpc;
996 NNPC = Tnpc + 4;
997 Tl = Tl - 1;
998 }});
999 0x1: Priv::retry({{
1000 if(Tl == 0)
1001 return new IllegalInstruction;
1002 Cwp = Tstate<4:0>;
1003 Pstate = Tstate<20:8>;
1004 Asi = Tstate<31:24>;
1005 Ccr = Tstate<39:32>;
1006 Gl = Tstate<42:40>;
1007 Hpstate = Htstate;
1008 NPC = Tpc;
1009 NNPC = Tnpc;
1010 Tl = Tl - 1;
1011 }});
1012 }
1013 }
1014 }
1015 0x3: decode OP3 {
1016 format Load {
1017 0x00: lduw({{Rd = Mem.uw;}});
1018 0x01: ldub({{Rd = Mem.ub;}});
1019 0x02: lduh({{Rd = Mem.uhw;}});
1020 0x03: ldtw({{
1021 uint64_t val = Mem.udw;
1022 RdLow = val<31:0>;
1023 RdHigh = val<63:32>;
1024 }});
1025 }
1026 format Store {
1027 0x04: stw({{Mem.uw = Rd.sw;}});
1028 0x05: stb({{Mem.ub = Rd.sb;}});
1029 0x06: sth({{Mem.uhw = Rd.shw;}});
1030 0x07: sttw({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
1031 }
1032 format Load {
1033 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
1034 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
1035 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
1036 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
1037 }
1038 0x0D: LoadStore::ldstub(
|
1040 {{Rd = Mem.ub;}},
1041 {{Mem.ub = 0xFF;}});
| 1039 {{uReg0 = Mem.ub;}},
1040 {{Rd.ub = uReg0;
1041 Mem.ub = 0xFF;}});
|
1042 0x0E: Store::stx({{Mem.udw = Rd}});
1043 0x0F: LoadStore::swap(
| 1042 0x0E: Store::stx({{Mem.udw = Rd}});
1043 0x0F: LoadStore::swap(
|
1044 {{uReg0 = Rd.uw;
1045 Rd.uw = Mem.uw;}},
1046 {{Mem.uw = uReg0;}});
| 1044 {{ uReg0 = Mem.uw}},
1045 {{ Mem.uw = Rd.uw;
1046 Rd.uw = uReg0;}});
|
1047 format LoadAlt {
1048 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
1049 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
1050 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
1051 0x13: decode EXT_ASI {
1052 //ASI_LDTD_AIUP
1053 0x22: TwinLoad::ldtx_aiup(
| 1047 format LoadAlt {
1048 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
1049 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
1050 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
1051 0x13: decode EXT_ASI {
1052 //ASI_LDTD_AIUP
1053 0x22: TwinLoad::ldtx_aiup(
|
1054 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
| 1054 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
|
1055 //ASI_LDTD_AIUS
1056 0x23: TwinLoad::ldtx_aius(
| 1055 //ASI_LDTD_AIUS
1056 0x23: TwinLoad::ldtx_aius(
|
1057 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
| 1057 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
|
1058 //ASI_QUAD_LDD
1059 0x24: TwinLoad::ldtx_quad_ldd(
| 1058 //ASI_QUAD_LDD
1059 0x24: TwinLoad::ldtx_quad_ldd(
|
1060 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
| 1060 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
|
1061 //ASI_LDTX_REAL
1062 0x26: TwinLoad::ldtx_real(
| 1061 //ASI_LDTX_REAL
1062 0x26: TwinLoad::ldtx_real(
|
1063 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
| 1063 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
|
1064 //ASI_LDTX_N
1065 0x27: TwinLoad::ldtx_n(
| 1064 //ASI_LDTX_N
1065 0x27: TwinLoad::ldtx_n(
|
1066 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
| 1066 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
|
1067 //ASI_LDTX_L
1068 0x2C: TwinLoad::ldtx_l(
| 1067 //ASI_LDTX_L
1068 0x2C: TwinLoad::ldtx_l(
|
1069 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
| 1069 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
|
1070 //ASI_LDTX_REAL_L
1071 0x2E: TwinLoad::ldtx_real_l(
| 1070 //ASI_LDTX_REAL_L
1071 0x2E: TwinLoad::ldtx_real_l(
|
1072 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
| 1072 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
|
1073 //ASI_LDTX_N_L
1074 0x2F: TwinLoad::ldtx_n_l(
| 1073 //ASI_LDTX_N_L
1074 0x2F: TwinLoad::ldtx_n_l(
|
1075 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
| 1075 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
|
1076 //ASI_LDTX_P
1077 0xE2: TwinLoad::ldtx_p(
| 1076 //ASI_LDTX_P
1077 0xE2: TwinLoad::ldtx_p(
|
1078 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
| 1078 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
|
1079 //ASI_LDTX_S
1080 0xE3: TwinLoad::ldtx_s(
| 1079 //ASI_LDTX_S
1080 0xE3: TwinLoad::ldtx_s(
|
1081 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
| 1081 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
|
1082 default: ldtwa({{
1083 uint64_t val = Mem.udw;
1084 RdLow = val<31:0>;
1085 RdHigh = val<63:32>;
1086 }}, {{EXT_ASI}});
1087 }
1088 }
1089 format StoreAlt {
1090 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
1091 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
1092 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
1093 0x17: sttwa({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}});
1094 }
1095 format LoadAlt {
1096 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
1097 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}});
1098 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}});
1099 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}});
1100 }
1101 0x1D: LoadStoreAlt::ldstuba(
| 1082 default: ldtwa({{
1083 uint64_t val = Mem.udw;
1084 RdLow = val<31:0>;
1085 RdHigh = val<63:32>;
1086 }}, {{EXT_ASI}});
1087 }
1088 }
1089 format StoreAlt {
1090 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
1091 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
1092 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
1093 0x17: sttwa({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}});
1094 }
1095 format LoadAlt {
1096 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
1097 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}});
1098 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}});
1099 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}});
1100 }
1101 0x1D: LoadStoreAlt::ldstuba(
|
1102 {{Rd = Mem.ub;}},
1103 {{Mem.ub = 0xFF}}, {{EXT_ASI}});
| 1102 {{uReg0 = Mem.ub;}},
1103 {{Rd.ub = uReg0;
1104 Mem.ub = 0xFF;}}, {{EXT_ASI}});
|
1104 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}});
1105 0x1F: LoadStoreAlt::swapa(
| 1105 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}});
1106 0x1F: LoadStoreAlt::swapa(
|
1106 {{uReg0 = Rd.uw;
1107 Rd.uw = Mem.uw;}},
1108 {{Mem.uw = uReg0;}}, {{EXT_ASI}});
| 1107 {{ uReg0 = Mem.uw}},
1108 {{ Mem.uw = Rd.uw;
1109 Rd.uw = uReg0;}}, {{EXT_ASI}});
|
1109 format Trap {
| 1110 format Trap {
|
1110 0x20: Load::ldf({{Frd.uw = Mem.uw;}});
| 1111 0x20: Load::ldf({{Frds.uw = Mem.uw;}});
|
1111 0x21: decode X {
1112 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}});
1113 0x1: Load::ldxfsr({{Fsr = Mem.udw;}});
1114 }
1115 0x22: ldqf({{fault = new FpDisabled;}});
1116 0x23: Load::lddf({{Frd.udw = Mem.udw;}});
| 1112 0x21: decode X {
1113 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}});
1114 0x1: Load::ldxfsr({{Fsr = Mem.udw;}});
1115 }
1116 0x22: ldqf({{fault = new FpDisabled;}});
1117 0x23: Load::lddf({{Frd.udw = Mem.udw;}});
|
1117 0x24: Store::stf({{Mem.uw = Frd.uw;}});
| 1118 0x24: Store::stf({{Mem.uw = Frds.uw;}});
|
1118 0x25: decode X {
1119 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}});
1120 0x1: Store::stxfsr({{Mem.udw = Fsr;}});
1121 }
1122 0x26: stqf({{fault = new FpDisabled;}});
1123 0x27: Store::stdf({{Mem.udw = Frd.udw;}});
1124 0x2D: Nop::prefetch({{ }});
| 1119 0x25: decode X {
1120 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}});
1121 0x1: Store::stxfsr({{Mem.udw = Fsr;}});
1122 }
1123 0x26: stqf({{fault = new FpDisabled;}});
1124 0x27: Store::stdf({{Mem.udw = Frd.udw;}});
1125 0x2D: Nop::prefetch({{ }});
|
1125 0x30: LoadAlt::ldfa({{Frd.uw = Mem.uw;}}, {{EXT_ASI}});
| 1126 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}});
|
1126 0x32: ldqfa({{fault = new FpDisabled;}});
1127 format LoadAlt {
1128 0x33: decode EXT_ASI {
1129 //ASI_NUCLEUS
1130 0x04: FailUnimpl::lddfa_n();
1131 //ASI_NUCLEUS_LITTLE
1132 0x0C: FailUnimpl::lddfa_nl();
1133 //ASI_AS_IF_USER_PRIMARY
1134 0x10: FailUnimpl::lddfa_aiup();
1135 //ASI_AS_IF_USER_PRIMARY_LITTLE
1136 0x18: FailUnimpl::lddfa_aiupl();
1137 //ASI_AS_IF_USER_SECONDARY
1138 0x11: FailUnimpl::lddfa_aius();
1139 //ASI_AS_IF_USER_SECONDARY_LITTLE
1140 0x19: FailUnimpl::lddfa_aiusl();
1141 //ASI_REAL
1142 0x14: FailUnimpl::lddfa_real();
1143 //ASI_REAL_LITTLE
1144 0x1C: FailUnimpl::lddfa_real_l();
1145 //ASI_REAL_IO
1146 0x15: FailUnimpl::lddfa_real_io();
1147 //ASI_REAL_IO_LITTLE
1148 0x1D: FailUnimpl::lddfa_real_io_l();
1149 //ASI_PRIMARY
1150 0x80: FailUnimpl::lddfa_p();
1151 //ASI_PRIMARY_LITTLE
1152 0x88: FailUnimpl::lddfa_pl();
1153 //ASI_SECONDARY
1154 0x81: FailUnimpl::lddfa_s();
1155 //ASI_SECONDARY_LITTLE
1156 0x89: FailUnimpl::lddfa_sl();
1157 //ASI_PRIMARY_NO_FAULT
1158 0x82: FailUnimpl::lddfa_pnf();
1159 //ASI_PRIMARY_NO_FAULT_LITTLE
1160 0x8A: FailUnimpl::lddfa_pnfl();
1161 //ASI_SECONDARY_NO_FAULT
1162 0x83: FailUnimpl::lddfa_snf();
1163 //ASI_SECONDARY_NO_FAULT_LITTLE
1164 0x8B: FailUnimpl::lddfa_snfl();
1165
1166 format BlockLoad {
1167 // LDBLOCKF
1168 //ASI_BLOCK_AS_IF_USER_PRIMARY
1169 0x16: FailUnimpl::ldblockf_aiup();
1170 //ASI_BLOCK_AS_IF_USER_SECONDARY
1171 0x17: FailUnimpl::ldblockf_aius();
1172 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1173 0x1E: FailUnimpl::ldblockf_aiupl();
1174 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1175 0x1F: FailUnimpl::ldblockf_aiusl();
1176 //ASI_BLOCK_PRIMARY
1177 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}});
1178 //ASI_BLOCK_SECONDARY
1179 0xF1: FailUnimpl::ldblockf_s();
1180 //ASI_BLOCK_PRIMARY_LITTLE
1181 0xF8: FailUnimpl::ldblockf_pl();
1182 //ASI_BLOCK_SECONDARY_LITTLE
1183 0xF9: FailUnimpl::ldblockf_sl();
1184 }
1185
1186 //LDSHORTF
1187 //ASI_FL8_PRIMARY
1188 0xD0: FailUnimpl::ldshortf_8p();
1189 //ASI_FL8_SECONDARY
1190 0xD1: FailUnimpl::ldshortf_8s();
1191 //ASI_FL8_PRIMARY_LITTLE
1192 0xD8: FailUnimpl::ldshortf_8pl();
1193 //ASI_FL8_SECONDARY_LITTLE
1194 0xD9: FailUnimpl::ldshortf_8sl();
1195 //ASI_FL16_PRIMARY
1196 0xD2: FailUnimpl::ldshortf_16p();
1197 //ASI_FL16_SECONDARY
1198 0xD3: FailUnimpl::ldshortf_16s();
1199 //ASI_FL16_PRIMARY_LITTLE
1200 0xDA: FailUnimpl::ldshortf_16pl();
1201 //ASI_FL16_SECONDARY_LITTLE
1202 0xDB: FailUnimpl::ldshortf_16sl();
1203 //Not an ASI which is legal with lddfa
1204 default: Trap::lddfa_bad_asi(
1205 {{fault = new DataAccessException;}});
1206 }
1207 }
| 1127 0x32: ldqfa({{fault = new FpDisabled;}});
1128 format LoadAlt {
1129 0x33: decode EXT_ASI {
1130 //ASI_NUCLEUS
1131 0x04: FailUnimpl::lddfa_n();
1132 //ASI_NUCLEUS_LITTLE
1133 0x0C: FailUnimpl::lddfa_nl();
1134 //ASI_AS_IF_USER_PRIMARY
1135 0x10: FailUnimpl::lddfa_aiup();
1136 //ASI_AS_IF_USER_PRIMARY_LITTLE
1137 0x18: FailUnimpl::lddfa_aiupl();
1138 //ASI_AS_IF_USER_SECONDARY
1139 0x11: FailUnimpl::lddfa_aius();
1140 //ASI_AS_IF_USER_SECONDARY_LITTLE
1141 0x19: FailUnimpl::lddfa_aiusl();
1142 //ASI_REAL
1143 0x14: FailUnimpl::lddfa_real();
1144 //ASI_REAL_LITTLE
1145 0x1C: FailUnimpl::lddfa_real_l();
1146 //ASI_REAL_IO
1147 0x15: FailUnimpl::lddfa_real_io();
1148 //ASI_REAL_IO_LITTLE
1149 0x1D: FailUnimpl::lddfa_real_io_l();
1150 //ASI_PRIMARY
1151 0x80: FailUnimpl::lddfa_p();
1152 //ASI_PRIMARY_LITTLE
1153 0x88: FailUnimpl::lddfa_pl();
1154 //ASI_SECONDARY
1155 0x81: FailUnimpl::lddfa_s();
1156 //ASI_SECONDARY_LITTLE
1157 0x89: FailUnimpl::lddfa_sl();
1158 //ASI_PRIMARY_NO_FAULT
1159 0x82: FailUnimpl::lddfa_pnf();
1160 //ASI_PRIMARY_NO_FAULT_LITTLE
1161 0x8A: FailUnimpl::lddfa_pnfl();
1162 //ASI_SECONDARY_NO_FAULT
1163 0x83: FailUnimpl::lddfa_snf();
1164 //ASI_SECONDARY_NO_FAULT_LITTLE
1165 0x8B: FailUnimpl::lddfa_snfl();
1166
1167 format BlockLoad {
1168 // LDBLOCKF
1169 //ASI_BLOCK_AS_IF_USER_PRIMARY
1170 0x16: FailUnimpl::ldblockf_aiup();
1171 //ASI_BLOCK_AS_IF_USER_SECONDARY
1172 0x17: FailUnimpl::ldblockf_aius();
1173 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1174 0x1E: FailUnimpl::ldblockf_aiupl();
1175 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1176 0x1F: FailUnimpl::ldblockf_aiusl();
1177 //ASI_BLOCK_PRIMARY
1178 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}});
1179 //ASI_BLOCK_SECONDARY
1180 0xF1: FailUnimpl::ldblockf_s();
1181 //ASI_BLOCK_PRIMARY_LITTLE
1182 0xF8: FailUnimpl::ldblockf_pl();
1183 //ASI_BLOCK_SECONDARY_LITTLE
1184 0xF9: FailUnimpl::ldblockf_sl();
1185 }
1186
1187 //LDSHORTF
1188 //ASI_FL8_PRIMARY
1189 0xD0: FailUnimpl::ldshortf_8p();
1190 //ASI_FL8_SECONDARY
1191 0xD1: FailUnimpl::ldshortf_8s();
1192 //ASI_FL8_PRIMARY_LITTLE
1193 0xD8: FailUnimpl::ldshortf_8pl();
1194 //ASI_FL8_SECONDARY_LITTLE
1195 0xD9: FailUnimpl::ldshortf_8sl();
1196 //ASI_FL16_PRIMARY
1197 0xD2: FailUnimpl::ldshortf_16p();
1198 //ASI_FL16_SECONDARY
1199 0xD3: FailUnimpl::ldshortf_16s();
1200 //ASI_FL16_PRIMARY_LITTLE
1201 0xDA: FailUnimpl::ldshortf_16pl();
1202 //ASI_FL16_SECONDARY_LITTLE
1203 0xDB: FailUnimpl::ldshortf_16sl();
1204 //Not an ASI which is legal with lddfa
1205 default: Trap::lddfa_bad_asi(
1206 {{fault = new DataAccessException;}});
1207 }
1208 }
|
1208 0x34: Store::stfa({{Mem.uw = Frd.uw;}});
| 1209 0x34: Store::stfa({{Mem.uw = Frds.uw;}});
|
1209 0x36: stqfa({{fault = new FpDisabled;}});
1210 format StoreAlt {
1211 0x37: decode EXT_ASI {
1212 //ASI_NUCLEUS
1213 0x04: FailUnimpl::stdfa_n();
1214 //ASI_NUCLEUS_LITTLE
1215 0x0C: FailUnimpl::stdfa_nl();
1216 //ASI_AS_IF_USER_PRIMARY
1217 0x10: FailUnimpl::stdfa_aiup();
1218 //ASI_AS_IF_USER_PRIMARY_LITTLE
1219 0x18: FailUnimpl::stdfa_aiupl();
1220 //ASI_AS_IF_USER_SECONDARY
1221 0x11: FailUnimpl::stdfa_aius();
1222 //ASI_AS_IF_USER_SECONDARY_LITTLE
1223 0x19: FailUnimpl::stdfa_aiusl();
1224 //ASI_REAL
1225 0x14: FailUnimpl::stdfa_real();
1226 //ASI_REAL_LITTLE
1227 0x1C: FailUnimpl::stdfa_real_l();
1228 //ASI_REAL_IO
1229 0x15: FailUnimpl::stdfa_real_io();
1230 //ASI_REAL_IO_LITTLE
1231 0x1D: FailUnimpl::stdfa_real_io_l();
1232 //ASI_PRIMARY
1233 0x80: FailUnimpl::stdfa_p();
1234 //ASI_PRIMARY_LITTLE
1235 0x88: FailUnimpl::stdfa_pl();
1236 //ASI_SECONDARY
1237 0x81: FailUnimpl::stdfa_s();
1238 //ASI_SECONDARY_LITTLE
1239 0x89: FailUnimpl::stdfa_sl();
1240 //ASI_PRIMARY_NO_FAULT
1241 0x82: FailUnimpl::stdfa_pnf();
1242 //ASI_PRIMARY_NO_FAULT_LITTLE
1243 0x8A: FailUnimpl::stdfa_pnfl();
1244 //ASI_SECONDARY_NO_FAULT
1245 0x83: FailUnimpl::stdfa_snf();
1246 //ASI_SECONDARY_NO_FAULT_LITTLE
1247 0x8B: FailUnimpl::stdfa_snfl();
1248
1249 format BlockStore {
1250 // STBLOCKF
1251 //ASI_BLOCK_AS_IF_USER_PRIMARY
1252 0x16: FailUnimpl::stblockf_aiup();
1253 //ASI_BLOCK_AS_IF_USER_SECONDARY
1254 0x17: FailUnimpl::stblockf_aius();
1255 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1256 0x1E: FailUnimpl::stblockf_aiupl();
1257 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1258 0x1F: FailUnimpl::stblockf_aiusl();
1259 //ASI_BLOCK_PRIMARY
1260 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}});
1261 //ASI_BLOCK_SECONDARY
1262 0xF1: FailUnimpl::stblockf_s();
1263 //ASI_BLOCK_PRIMARY_LITTLE
1264 0xF8: FailUnimpl::stblockf_pl();
1265 //ASI_BLOCK_SECONDARY_LITTLE
1266 0xF9: FailUnimpl::stblockf_sl();
1267 }
1268
1269 //STSHORTF
1270 //ASI_FL8_PRIMARY
1271 0xD0: FailUnimpl::stshortf_8p();
1272 //ASI_FL8_SECONDARY
1273 0xD1: FailUnimpl::stshortf_8s();
1274 //ASI_FL8_PRIMARY_LITTLE
1275 0xD8: FailUnimpl::stshortf_8pl();
1276 //ASI_FL8_SECONDARY_LITTLE
1277 0xD9: FailUnimpl::stshortf_8sl();
1278 //ASI_FL16_PRIMARY
1279 0xD2: FailUnimpl::stshortf_16p();
1280 //ASI_FL16_SECONDARY
1281 0xD3: FailUnimpl::stshortf_16s();
1282 //ASI_FL16_PRIMARY_LITTLE
1283 0xDA: FailUnimpl::stshortf_16pl();
1284 //ASI_FL16_SECONDARY_LITTLE
1285 0xDB: FailUnimpl::stshortf_16sl();
1286 //Not an ASI which is legal with lddfa
1287 default: Trap::stdfa_bad_asi(
1288 {{fault = new DataAccessException;}});
1289 }
1290 }
1291 0x3C: Cas::casa(
1292 {{uReg0 = Mem.uw;}},
1293 {{if(Rs2.uw == uReg0)
1294 Mem.uw = Rd.uw;
1295 else
1296 storeCond = false;
1297 Rd.uw = uReg0;}}, {{EXT_ASI}});
1298 0x3D: Nop::prefetcha({{ }});
1299 0x3E: Cas::casxa(
1300 {{uReg0 = Mem.udw;}},
1301 {{if(Rs2 == uReg0)
1302 Mem.udw = Rd;
1303 else
1304 storeCond = false;
1305 Rd = uReg0;}}, {{EXT_ASI}});
1306 }
1307 }
1308}
| 1210 0x36: stqfa({{fault = new FpDisabled;}});
1211 format StoreAlt {
1212 0x37: decode EXT_ASI {
1213 //ASI_NUCLEUS
1214 0x04: FailUnimpl::stdfa_n();
1215 //ASI_NUCLEUS_LITTLE
1216 0x0C: FailUnimpl::stdfa_nl();
1217 //ASI_AS_IF_USER_PRIMARY
1218 0x10: FailUnimpl::stdfa_aiup();
1219 //ASI_AS_IF_USER_PRIMARY_LITTLE
1220 0x18: FailUnimpl::stdfa_aiupl();
1221 //ASI_AS_IF_USER_SECONDARY
1222 0x11: FailUnimpl::stdfa_aius();
1223 //ASI_AS_IF_USER_SECONDARY_LITTLE
1224 0x19: FailUnimpl::stdfa_aiusl();
1225 //ASI_REAL
1226 0x14: FailUnimpl::stdfa_real();
1227 //ASI_REAL_LITTLE
1228 0x1C: FailUnimpl::stdfa_real_l();
1229 //ASI_REAL_IO
1230 0x15: FailUnimpl::stdfa_real_io();
1231 //ASI_REAL_IO_LITTLE
1232 0x1D: FailUnimpl::stdfa_real_io_l();
1233 //ASI_PRIMARY
1234 0x80: FailUnimpl::stdfa_p();
1235 //ASI_PRIMARY_LITTLE
1236 0x88: FailUnimpl::stdfa_pl();
1237 //ASI_SECONDARY
1238 0x81: FailUnimpl::stdfa_s();
1239 //ASI_SECONDARY_LITTLE
1240 0x89: FailUnimpl::stdfa_sl();
1241 //ASI_PRIMARY_NO_FAULT
1242 0x82: FailUnimpl::stdfa_pnf();
1243 //ASI_PRIMARY_NO_FAULT_LITTLE
1244 0x8A: FailUnimpl::stdfa_pnfl();
1245 //ASI_SECONDARY_NO_FAULT
1246 0x83: FailUnimpl::stdfa_snf();
1247 //ASI_SECONDARY_NO_FAULT_LITTLE
1248 0x8B: FailUnimpl::stdfa_snfl();
1249
1250 format BlockStore {
1251 // STBLOCKF
1252 //ASI_BLOCK_AS_IF_USER_PRIMARY
1253 0x16: FailUnimpl::stblockf_aiup();
1254 //ASI_BLOCK_AS_IF_USER_SECONDARY
1255 0x17: FailUnimpl::stblockf_aius();
1256 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1257 0x1E: FailUnimpl::stblockf_aiupl();
1258 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1259 0x1F: FailUnimpl::stblockf_aiusl();
1260 //ASI_BLOCK_PRIMARY
1261 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}});
1262 //ASI_BLOCK_SECONDARY
1263 0xF1: FailUnimpl::stblockf_s();
1264 //ASI_BLOCK_PRIMARY_LITTLE
1265 0xF8: FailUnimpl::stblockf_pl();
1266 //ASI_BLOCK_SECONDARY_LITTLE
1267 0xF9: FailUnimpl::stblockf_sl();
1268 }
1269
1270 //STSHORTF
1271 //ASI_FL8_PRIMARY
1272 0xD0: FailUnimpl::stshortf_8p();
1273 //ASI_FL8_SECONDARY
1274 0xD1: FailUnimpl::stshortf_8s();
1275 //ASI_FL8_PRIMARY_LITTLE
1276 0xD8: FailUnimpl::stshortf_8pl();
1277 //ASI_FL8_SECONDARY_LITTLE
1278 0xD9: FailUnimpl::stshortf_8sl();
1279 //ASI_FL16_PRIMARY
1280 0xD2: FailUnimpl::stshortf_16p();
1281 //ASI_FL16_SECONDARY
1282 0xD3: FailUnimpl::stshortf_16s();
1283 //ASI_FL16_PRIMARY_LITTLE
1284 0xDA: FailUnimpl::stshortf_16pl();
1285 //ASI_FL16_SECONDARY_LITTLE
1286 0xDB: FailUnimpl::stshortf_16sl();
1287 //Not an ASI which is legal with lddfa
1288 default: Trap::stdfa_bad_asi(
1289 {{fault = new DataAccessException;}});
1290 }
1291 }
1292 0x3C: Cas::casa(
1293 {{uReg0 = Mem.uw;}},
1294 {{if(Rs2.uw == uReg0)
1295 Mem.uw = Rd.uw;
1296 else
1297 storeCond = false;
1298 Rd.uw = uReg0;}}, {{EXT_ASI}});
1299 0x3D: Nop::prefetcha({{ }});
1300 0x3E: Cas::casxa(
1301 {{uReg0 = Mem.udw;}},
1302 {{if(Rs2 == uReg0)
1303 Mem.udw = Rd;
1304 else
1305 storeCond = false;
1306 Rd = uReg0;}}, {{EXT_ASI}});
1307 }
1308 }
1309}
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