2// All rights reserved.
3//
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5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OP default Unknown::unknown()
37{
38 0x0: decode OP2
39 {
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 //bpcc
45 0x1: decode COND2
46 {
47 //Branch Always
48 0x8: decode A
49 {
50 0x0: bpa(19, {{
51 NNPC = xc->readPC() + disp;
52 }});
53 0x1: bpa(19, {{
54 NPC = xc->readPC() + disp;
55 NNPC = NPC + 4;
56 }}, ',a');
57 }
58 //Branch Never
59 0x0: decode A
60 {
61 0x0: bpn(19, {{
62 NNPC = NNPC;//Don't do anything
63 }});
64 0x1: bpn(19, {{
65 NPC = xc->readNextPC() + 4;
66 NNPC = NPC + 4;
67 }}, ',a');
68 }
69 default: decode BPCC
70 {
71 0x0: bpcci(19, {{
72 if(passesCondition(Ccr<3:0>, COND2))
73 NNPC = xc->readPC() + disp;
74 else
75 handle_annul
76 }});
77 0x2: bpccx(19, {{
78 if(passesCondition(Ccr<7:4>, COND2))
79 {
80 //warn("Took branch!\n");
81 NNPC = xc->readPC() + disp;
82 }
83 else
84 {
85 //warn("Didn't take branch!\n");
86 handle_annul
87 }
88 }});
89 }
90 }
91 //bicc
92 0x2: decode COND2
93 {
94 //Branch Always
95 0x8: decode A
96 {
97 0x0: ba(22, {{
98 NNPC = xc->readPC() + disp;
99 }});
100 0x1: ba(22, {{
101 NPC = xc->readPC() + disp;
102 NNPC = NPC + 4;
103 }}, ',a');
104 }
105 //Branch Never
106 0x0: decode A
107 {
108 0x0: bn(22, {{
109 NNPC = NNPC;//Don't do anything
110 }});
111 0x1: bn(22, {{
112 NPC = xc->readNextPC() + 4;
113 NNPC = NPC + 4;
114 }}, ',a');
115 }
116 default: bicc(22, {{
117 if(passesCondition(Ccr<3:0>, COND2))
118 NNPC = xc->readPC() + disp;
119 else
120 handle_annul
121 }});
122 }
123 }
124 0x3: decode RCOND2
125 {
126 format BranchSplit
127 {
128 0x1: bpreq({{
129 if(Rs1.sdw == 0)
130 NNPC = xc->readPC() + disp;
131 else
132 handle_annul
133 }});
134 0x2: bprle({{
135 if(Rs1.sdw <= 0)
136 NNPC = xc->readPC() + disp;
137 else
138 handle_annul
139 }});
140 0x3: bprl({{
141 if(Rs1.sdw < 0)
142 NNPC = xc->readPC() + disp;
143 else
144 handle_annul
145 }});
146 0x5: bprne({{
147 if(Rs1.sdw != 0)
148 NNPC = xc->readPC() + disp;
149 else
150 handle_annul
151 }});
152 0x6: bprg({{
153 if(Rs1.sdw > 0)
154 NNPC = xc->readPC() + disp;
155 else
156 handle_annul
157 }});
158 0x7: bprge({{
159 if(Rs1.sdw >= 0)
160 NNPC = xc->readPC() + disp;
161 else
162 handle_annul
163 }});
164 }
165 }
166 //SETHI (or NOP if rd == 0 and imm == 0)
167 0x4: SetHi::sethi({{Rd.udw = imm;}});
168 0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
169 0x6: Trap::fbfcc({{fault = new FpDisabled;}});
170 }
171 0x1: BranchN::call(30, {{
172 R15 = xc->readPC();
173 NNPC = R15 + disp;
174 }});
175 0x2: decode OP3 {
176 format IntOp {
177 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
178 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
179 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
180 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
181 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
182 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}});
183 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}});
184 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
185 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
186 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
187 0x0A: umul({{
188 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
189 Y = Rd<63:32>;
190 }});
191 0x0B: smul({{
192 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
193 Y = Rd.sdw;
194 }});
195 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
196 0x0D: udivx({{
197 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
198 else Rd.udw = Rs1.udw / Rs2_or_imm13;
199 }});
200 0x0E: udiv({{
201 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
202 else
203 {
204 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
205 if(Rd.udw >> 32 != 0)
206 Rd.udw = 0xFFFFFFFF;
207 }
208 }});
209 0x0F: sdiv({{
210 if(Rs2_or_imm13.sdw == 0)
211 fault = new DivisionByZero;
212 else
213 {
214 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
215 if(Rd.udw<63:31> != 0)
216 Rd.udw = 0x7FFFFFFF;
217 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
218 Rd.udw = 0xFFFFFFFF80000000ULL;
219 }
220 }});
221 }
222 format IntOpCc {
223 0x10: addcc({{
224 int64_t resTemp, val2 = Rs2_or_imm13;
225 Rd = resTemp = Rs1 + val2;}},
226 {{(Rs1<31:0> + val2<31:0>)<32:>}},
227 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
228 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
229 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
230 );
231 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
232 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
233 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
234 0x14: subcc({{
235 int64_t val2 = Rs2_or_imm13;
236 Rd = Rs1 - val2;}},
237 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
238 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
239 {{(~(Rs1<63:1> + (~val2)<63:1> +
240 (Rs1 | ~val2)<0:>))<63:>}},
241 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
242 );
243 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
244 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
245 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
246 0x18: addccc({{
247 int64_t resTemp, val2 = Rs2_or_imm13;
248 int64_t carryin = Ccr<0:0>;
249 Rd = resTemp = Rs1 + val2 + carryin;}},
250 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
251 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
252 {{(Rs1<63:1> + val2<63:1> +
253 ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
254 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
255 );
256 0x1A: IntOpCcRes::umulcc({{
257 uint64_t resTemp;
258 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
259 Y = resTemp<63:32>;}});
260 0x1B: IntOpCcRes::smulcc({{
261 int64_t resTemp;
262 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>;
263 Y = resTemp<63:32>;}});
264 0x1C: subccc({{
265 int64_t resTemp, val2 = Rs2_or_imm13;
266 int64_t carryin = Ccr<0:0>;
267 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
268 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
269 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
270 {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
271 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
272 );
273 0x1D: IntOpCcRes::udivxcc({{
274 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
275 else Rd = Rs1.udw / Rs2_or_imm13.udw;}});
276 0x1E: udivcc({{
277 uint32_t resTemp, val2 = Rs2_or_imm13.udw;
278 int32_t overflow = 0;
279 if(val2 == 0) fault = new DivisionByZero;
280 else
281 {
282 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
283 overflow = (resTemp<63:32> != 0);
284 if(overflow) Rd = resTemp = 0xFFFFFFFF;
285 else Rd = resTemp;
286 } }},
287 {{0}},
288 {{overflow}},
289 {{0}},
290 {{0}}
291 );
292 0x1F: sdivcc({{
293 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
294 bool overflow = false, underflow = false;
295 if(val2 == 0) fault = new DivisionByZero;
296 else
297 {
298 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
299 overflow = (Rd<63:31> != 0);
300 underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF);
301 if(overflow) Rd = 0x7FFFFFFF;
302 else if(underflow) Rd = 0xFFFFFFFF80000000ULL;
303 } }},
304 {{0}},
305 {{overflow || underflow}},
306 {{0}},
307 {{0}}
308 );
309 0x20: taddcc({{
310 int64_t resTemp, val2 = Rs2_or_imm13;
311 Rd = resTemp = Rs1 + val2;
312 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
313 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
314 {{overflow}},
315 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
316 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
317 );
318 0x21: tsubcc({{
319 int64_t resTemp, val2 = Rs2_or_imm13;
320 Rd = resTemp = Rs1 + val2;
321 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
322 {{(Rs1<31:0> + val2<31:0>)<32:0>}},
323 {{overflow}},
324 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
325 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
326 );
327 0x22: taddcctv({{
328 int64_t val2 = Rs2_or_imm13;
329 Rd = Rs1 + val2;
330 int32_t overflow = Rs1<1:0> || val2<1:0> ||
331 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
332 if(overflow) fault = new TagOverflow;}},
333 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
334 {{overflow}},
335 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
336 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}}
337 );
338 0x23: tsubcctv({{
339 int64_t resTemp, val2 = Rs2_or_imm13;
340 Rd = resTemp = Rs1 + val2;
341 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
342 if(overflow) fault = new TagOverflow;}},
343 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
344 {{overflow}},
345 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
346 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
347 );
348 0x24: mulscc({{
349 int64_t resTemp, multiplicand = Rs2_or_imm13;
350 int32_t multiplier = Rs1<31:0>;
351 int32_t savedLSB = Rs1<0:>;
352 multiplier = multiplier<31:1> |
353 ((Ccr<3:3> ^ Ccr<1:1>) << 32);
354 if(!Y<0:>)
355 multiplicand = 0;
356 Rd = resTemp = multiplicand + multiplier;
357 Y = Y<31:1> | (savedLSB << 31);}},
358 {{((multiplicand<31:0> + multiplier<31:0>)<32:0>)}},
359 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
360 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
361 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
362 );
363 }
364 format IntOp
365 {
366 0x25: decode X {
367 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
368 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
369 }
370 0x26: decode X {
371 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
372 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
373 }
374 0x27: decode X {
375 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
376 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
377 }
378 0x28: decode RS1 {
379 0x00: NoPriv::rdy({{Rd = Y;}});
380 //1 should cause an illegal instruction exception
381 0x02: NoPriv::rdccr({{Rd = Ccr;}});
382 0x03: NoPriv::rdasi({{Rd = Asi;}});
383 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
384 0x05: NoPriv::rdpc({{
385 if(Pstate<3:>)
386 Rd = (xc->readPC())<31:0>;
387 else
388 Rd = xc->readPC();}});
389 0x06: NoPriv::rdfprs({{
390 //Wait for all fpops to finish.
391 Rd = Fprs;
392 }});
393 //7-14 should cause an illegal instruction exception
394 0x0F: decode I {
395 0x0: Nop::stbar({{/*stuff*/}});
396 0x1: Nop::membar({{/*stuff*/}});
397 }
398 0x10: Priv::rdpcr({{Rd = Pcr;}});
399 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
400 //0x12 should cause an illegal instruction exception
401 0x13: NoPriv::rdgsr({{
402 if(Fprs<2:> == 0 || Pstate<4:> == 0)
403 Rd = Gsr;
404 else
405 fault = new FpDisabled;
406 }});
407 //0x14-0x15 should cause an illegal instruction exception
408 0x16: Priv::rdsoftint({{Rd = Softint;}});
409 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
410 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}});
411 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
412 0x1A: Priv::rdstrand_sts_reg({{
413 if(Pstate<2:> && !Hpstate<2:>)
414 Rd = StrandStsReg<0:>;
415 else
416 Rd = StrandStsReg;
417 }});
418 //0x1A is supposed to be reserved, but it reads the strand
419 //status register.
420 //0x1B-0x1F should cause an illegal instruction exception
421 }
422 0x29: decode RS1 {
423 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
424 0x01: HPriv::rdhprhtstate({{
425 if(Tl == 0)
426 return new IllegalInstruction;
427 Rd = Htstate;
428 }});
429 //0x02 should cause an illegal instruction exception
430 0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
431 //0x04 should cause an illegal instruction exception
432 0x05: HPriv::rdhprhtba({{Rd = Htba;}});
433 0x06: HPriv::rdhprhver({{Rd = Hver;}});
434 //0x07-0x1E should cause an illegal instruction exception
435 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
436 }
437 0x2A: decode RS1 {
438 0x00: Priv::rdprtpc({{
439 if(Tl == 0)
440 return new IllegalInstruction;
441 Rd = Tpc;
442 }});
443 0x01: Priv::rdprtnpc({{
444 if(Tl == 0)
445 return new IllegalInstruction;
446 Rd = Tnpc;
447 }});
448 0x02: Priv::rdprtstate({{
449 if(Tl == 0)
450 return new IllegalInstruction;
451 Rd = Tstate;
452 }});
453 0x03: Priv::rdprtt({{
454 if(Tl == 0)
455 return new IllegalInstruction;
456 Rd = Tt;
457 }});
458 0x04: Priv::rdprtick({{Rd = Tick;}});
459 0x05: Priv::rdprtba({{Rd = Tba;}});
460 0x06: Priv::rdprpstate({{Rd = Pstate;}});
461 0x07: Priv::rdprtl({{Rd = Tl;}});
462 0x08: Priv::rdprpil({{Rd = Pil;}});
463 0x09: Priv::rdprcwp({{Rd = Cwp;}});
464 0x0A: Priv::rdprcansave({{Rd = Cansave;}});
465 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});
466 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});
467 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}});
468 0x0E: Priv::rdprwstate({{Rd = Wstate;}});
469 //0x0F should cause an illegal instruction exception
470 0x10: Priv::rdprgl({{Rd = Gl;}});
471 //0x11-0x1F should cause an illegal instruction exception
472 }
473 0x2B: BasicOperate::flushw({{
474 if(NWindows - 2 - Cansave == 0)
475 {
476 if(Otherwin)
477 fault = new SpillNOther(Wstate<5:3>);
478 else
479 fault = new SpillNNormal(Wstate<2:0>);
480 }
481 }});
482 0x2C: decode MOVCC3
483 {
484 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
485 0x1: decode CC
486 {
487 0x0: movcci({{
488 if(passesCondition(Ccr<3:0>, COND4))
489 Rd = Rs2_or_imm11;
490 else
491 Rd = Rd;
492 }});
493 0x2: movccx({{
494 if(passesCondition(Ccr<7:4>, COND4))
495 Rd = Rs2_or_imm11;
496 else
497 Rd = Rd;
498 }});
499 }
500 }
501 0x2D: sdivx({{
502 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
503 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
504 }});
505 0x2E: decode RS1 {
506 0x0: IntOp::popc({{
507 int64_t count = 0;
508 uint64_t temp = Rs2_or_imm13;
509 //Count the 1s in the front 4bits until none are left
510 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
511 while(temp)
512 {
513 count += oneBits[temp & 0xF];
514 temp = temp >> 4;
515 }
516 Rd = count;
517 }});
518 }
519 0x2F: decode RCOND3
520 {
521 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
522 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
523 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
524 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
525 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
526 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
527 }
528 0x30: decode RD {
529 0x00: NoPriv::wry({{Y = Rs1 ^ Rs2_or_imm13;}});
530 //0x01 should cause an illegal instruction exception
531 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
532 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
533 //0x04-0x05 should cause an illegal instruction exception
534 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
535 //0x07-0x0E should cause an illegal instruction exception
536 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
537 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
538 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
539 //0x12 should cause an illegal instruction exception
540 0x13: NoPriv::wrgsr({{
541 if(Fprs<2:> == 0 || Pstate<4:> == 0)
542 return new FpDisabled;
543 Gsr = Rs1 ^ Rs2_or_imm13;
544 }});
545 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
546 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});
547 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
548 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}});
549 0x18: NoPriv::wrstick({{
550 if(!Hpstate<2:>)
551 return new IllegalInstruction;
552 Stick = Rs1 ^ Rs2_or_imm13;
553 }});
554 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}});
555 0x1A: Priv::wrstrand_sts_reg({{
556 if(Pstate<2:> && !Hpstate<2:>)
557 StrandStsReg = StrandStsReg<63:1> |
558 (Rs1 ^ Rs2_or_imm13)<0:>;
559 else
560 StrandStsReg = Rs1 ^ Rs2_or_imm13;
561 }});
562 //0x1A is supposed to be reserved, but it writes the strand
563 //status register.
564 //0x1B-0x1F should cause an illegal instruction exception
565 }
566 0x31: decode FCN {
567 0x0: Priv::saved({{
568 assert(Cansave < NWindows - 2);
569 assert(Otherwin || Canrestore);
570 Cansave = Cansave + 1;
571 if(Otherwin == 0)
572 Canrestore = Canrestore - 1;
573 else
574 Otherwin = Otherwin - 1;
575 }});
576 0x1: Priv::restored({{
577 assert(Cansave || Otherwin);
578 assert(Canrestore < NWindows - 2);
579 Canrestore = Canrestore + 1;
580 if(Otherwin == 0)
581 Cansave = Cansave - 1;
582 else
583 Otherwin = Otherwin - 1;
584 }});
585 }
586 0x32: decode RD {
587 0x00: Priv::wrprtpc({{
588 if(Tl == 0)
589 return new IllegalInstruction;
590 else
591 Tpc = Rs1 ^ Rs2_or_imm13;
592 }});
593 0x01: Priv::wrprtnpc({{
594 if(Tl == 0)
595 return new IllegalInstruction;
596 else
597 Tnpc = Rs1 ^ Rs2_or_imm13;
598 }});
599 0x02: Priv::wrprtstate({{
600 if(Tl == 0)
601 return new IllegalInstruction;
602 else
603 Tstate = Rs1 ^ Rs2_or_imm13;
604 }});
605 0x03: Priv::wrprtt({{
606 if(Tl == 0)
607 return new IllegalInstruction;
608 else
609 Tt = Rs1 ^ Rs2_or_imm13;
610 }});
611 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
612 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
613 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
614 0x07: Priv::wrprtl({{
615 if(Pstate<2:> && !Hpstate<2:>)
616 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
617 else
618 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);
619 }});
620 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
621 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
622 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
623 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
624 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
625 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
626 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
627 //0x0F should cause an illegal instruction exception
628 0x10: Priv::wrprgl({{
629 if(Pstate<2:> && !Hpstate<2:>)
630 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL);
631 else
632 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
633 }});
634 //0x11-0x1F should cause an illegal instruction exception
635 }
636 0x33: decode RD {
637 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
638 0x01: HPriv::wrhprhtstate({{
639 if(Tl == 0)
640 return new IllegalInstruction;
641 Htstate = Rs1 ^ Rs2_or_imm13;
642 }});
643 //0x02 should cause an illegal instruction exception
644 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
645 //0x04 should cause an illegal instruction exception
646 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
647 //0x06-0x01D should cause an illegal instruction exception
648 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
649 }
650 0x34: decode OPF{
651 format BasicOperate{
652 0x01: fmovs({{
653 Frds.uw = Frs2s.uw;
654 //fsr.ftt = fsr.cexc = 0
655 Fsr &= ~(7 << 14);
656 Fsr &= ~(0x1F);
657 }});
658 0x02: fmovd({{
659 Frd.udw = Frs2.udw;
660 //fsr.ftt = fsr.cexc = 0
661 Fsr &= ~(7 << 14);
662 Fsr &= ~(0x1F);
663 }});
664 0x03: Trap::fmovq({{fault = new FpDisabled;}});
665 0x05: fnegs({{
666 Frds.uw = Frs2s.uw ^ (1UL << 31);
667 //fsr.ftt = fsr.cexc = 0
668 Fsr &= ~(7 << 14);
669 Fsr &= ~(0x1F);
670 }});
671 0x06: fnegd({{
672 Frd.udw = Frs2.udw ^ (1ULL << 63);
673 //fsr.ftt = fsr.cexc = 0
674 Fsr &= ~(7 << 14);
675 Fsr &= ~(0x1F);
676 }});
677 0x07: Trap::fnegq({{fault = new FpDisabled;}});
678 0x09: fabss({{
679 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;
680 //fsr.ftt = fsr.cexc = 0
681 Fsr &= ~(7 << 14);
682 Fsr &= ~(0x1F);
683 }});
684 0x0A: fabsd({{
685 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;
686 //fsr.ftt = fsr.cexc = 0
687 Fsr &= ~(7 << 14);
688 Fsr &= ~(0x1F);
689 }});
690 0x0B: Trap::fabsq({{fault = new FpDisabled;}});
691 0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}});
692 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}});
693 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
694 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
695 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
696 0x43: Trap::faddq({{fault = new FpDisabled;}});
697 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
698 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
699 0x47: Trap::fsubq({{fault = new FpDisabled;}});
700 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
701 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
702 0x4B: Trap::fmulq({{fault = new FpDisabled;}});
703 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
704 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
705 0x4F: Trap::fdivq({{fault = new FpDisabled;}});
706 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
707 0x6E: Trap::fdmulq({{fault = new FpDisabled;}});
708 0x81: fstox({{
709 Frd.df = (double)static_cast<int64_t>(Frs2s.sf);
710 }});
711 0x82: fdtox({{
712 Frd.df = (double)static_cast<int64_t>(Frs2.df);
713 }});
714 0x83: Trap::fqtox({{fault = new FpDisabled;}});
715 0x84: fxtos({{
716 Frds.sf = static_cast<float>((int64_t)Frs2.df);
717 }});
718 0x88: fxtod({{
719 Frd.df = static_cast<double>((int64_t)Frs2.df);
720 }});
721 0x8C: Trap::fxtoq({{fault = new FpDisabled;}});
722 0xC4: fitos({{
723 Frds.sf = static_cast<float>((int32_t)Frs2s.sf);
724 }});
725 0xC6: fdtos({{Frds.sf = Frs2.df;}});
726 0xC7: Trap::fqtos({{fault = new FpDisabled;}});
727 0xC8: fitod({{
728 Frd.df = static_cast<double>((int32_t)Frs2s.sf);
729 }});
730 0xC9: fstod({{Frd.df = Frs2s.sf;}});
731 0xCB: Trap::fqtod({{fault = new FpDisabled;}});
732 0xCC: Trap::fitoq({{fault = new FpDisabled;}});
733 0xCD: Trap::fstoq({{fault = new FpDisabled;}});
734 0xCE: Trap::fdtoq({{fault = new FpDisabled;}});
735 0xD1: fstoi({{
736 Frds.sf = (float)static_cast<int32_t>(Frs2s.sf);
737 }});
738 0xD2: fdtoi({{
739 Frds.sf = (float)static_cast<int32_t>(Frs2.df);
740 }});
741 0xD3: Trap::fqtoi({{fault = new FpDisabled;}});
742 default: Trap::fpop1({{fault = new FpDisabled;}});
743 }
744 }
745 0x35: Trap::fpop2({{fault = new FpDisabled;}});
746 //This used to be just impdep1, but now it's a whole bunch
747 //of instructions
748 0x36: decode OPF{
749 0x00: Trap::edge8({{fault = new IllegalInstruction;}});
750 0x01: Trap::edge8n({{fault = new IllegalInstruction;}});
751 0x02: Trap::edge8l({{fault = new IllegalInstruction;}});
752 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}});
753 0x04: Trap::edge16({{fault = new IllegalInstruction;}});
754 0x05: Trap::edge16n({{fault = new IllegalInstruction;}});
755 0x06: Trap::edge16l({{fault = new IllegalInstruction;}});
756 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}});
757 0x08: Trap::edge32({{fault = new IllegalInstruction;}});
758 0x09: Trap::edge32n({{fault = new IllegalInstruction;}});
759 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}});
760 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}});
761 0x10: Trap::array8({{fault = new IllegalInstruction;}});
762 0x12: Trap::array16({{fault = new IllegalInstruction;}});
763 0x14: Trap::array32({{fault = new IllegalInstruction;}});
764 0x18: BasicOperate::alignaddr({{
765 uint64_t sum = Rs1 + Rs2;
766 Rd = sum & ~7;
767 Gsr = (Gsr & ~7) | (sum & 7);
768 }});
769 0x19: Trap::bmask({{fault = new IllegalInstruction;}});
770 0x1A: BasicOperate::alignaddresslittle({{
771 uint64_t sum = Rs1 + Rs2;
772 Rd = sum & ~7;
773 Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
774 }});
775 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}});
776 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}});
777 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}});
778 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}});
779 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}});
780 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}});
781 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}});
782 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}});
783 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}});
784 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}});
785 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}});
786 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}});
787 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}});
788 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}});
789 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}});
790 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
791 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
792 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
793 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
794 0x48: BasicOperate::faligndata({{
795 uint64_t msbX = Frs1.udw;
796 uint64_t lsbX = Frs2.udw;
797 //Some special cases need to be split out, first
798 //because they're the most likely to be used, and
799 //second because otherwise, we end up shifting by
800 //greater than the width of the type being shifted,
801 //namely 64, which produces undefined results according
802 //to the C standard.
803 switch(Gsr<2:0>)
804 {
805 case 0:
806 Frd.udw = msbX;
807 break;
808 case 8:
809 Frd.udw = lsbX;
810 break;
811 default:
812 uint64_t msbShift = Gsr<2:0> * 8;
813 uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
814 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
815 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
816 Frd.udw = ((msbX & msbMask) << msbShift) |
817 ((lsbX & lsbMask) >> lsbShift);
818 }
819 }});
820 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
821 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}});
822 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}});
823 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}});
824 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}});
825 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}});
826 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}});
827 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}});
828 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}});
829 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}});
830 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}});
831 0x60: BasicOperate::fzero({{Frd.df = 0;}});
832 0x61: BasicOperate::fzeros({{Frds.sf = 0;}});
833 0x62: Trap::fnor({{fault = new IllegalInstruction;}});
834 0x63: Trap::fnors({{fault = new IllegalInstruction;}});
835 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}});
836 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}});
837 0x66: BasicOperate::fnot2({{
838 Frd.df = (double)(~((uint64_t)Frs2.df));
839 }});
840 0x67: BasicOperate::fnot2s({{
841 Frds.sf = (float)(~((uint32_t)Frs2s.sf));
842 }});
843 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}});
844 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}});
845 0x6A: BasicOperate::fnot1({{
846 Frd.df = (double)(~((uint64_t)Frs1.df));
847 }});
848 0x6B: BasicOperate::fnot1s({{
849 Frds.sf = (float)(~((uint32_t)Frs1s.sf));
850 }});
851 0x6C: Trap::fxor({{fault = new IllegalInstruction;}});
852 0x6D: Trap::fxors({{fault = new IllegalInstruction;}});
853 0x6E: Trap::fnand({{fault = new IllegalInstruction;}});
854 0x6F: Trap::fnands({{fault = new IllegalInstruction;}});
855 0x70: Trap::fand({{fault = new IllegalInstruction;}});
856 0x71: Trap::fands({{fault = new IllegalInstruction;}});
857 0x72: Trap::fxnor({{fault = new IllegalInstruction;}});
858 0x73: Trap::fxnors({{fault = new IllegalInstruction;}});
859 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}});
860 0x75: BasicOperate::fsrc1s({{Frd.uw = Frs1.uw;}});
861 0x76: Trap::fornot2({{fault = new IllegalInstruction;}});
862 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}});
863 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}});
864 0x79: BasicOperate::fsrc2s({{Frd.uw = Frs2.uw;}});
865 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}});
866 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}});
867 0x7C: Trap::for({{fault = new IllegalInstruction;}});
868 0x7D: Trap::fors({{fault = new IllegalInstruction;}});
869 0x7E: Trap::fone({{fault = new IllegalInstruction;}});
870 0x7F: Trap::fones({{fault = new IllegalInstruction;}});
871 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
872 0x81: Trap::siam({{fault = new IllegalInstruction;}});
873 }
874 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
875 0x38: Branch::jmpl({{
876 Addr target = Rs1 + Rs2_or_imm13;
877 if(target & 0x3)
878 fault = new MemAddressNotAligned;
879 else
880 {
881 Rd = xc->readPC();
882 NNPC = target;
883 }
884 }});
885 0x39: Branch::return({{
886 Addr target = Rs1 + Rs2_or_imm13;
887 if(fault == NoFault)
888 {
889 //Check for fills which are higher priority than alignment
890 //faults.
891 if(Canrestore == 0)
892 {
893 if(Otherwin)
894 fault = new FillNOther(Wstate<5:3>);
895 else
896 fault = new FillNNormal(Wstate<2:0>);
897 }
898 //Check for alignment faults
899 else if(target & 0x3)
900 fault = new MemAddressNotAligned;
901 else
902 {
903 NNPC = target;
904 Cwp = (Cwp - 1 + NWindows) % NWindows;
905 Cansave = Cansave + 1;
906 Canrestore = Canrestore - 1;
907 }
908 }
909 }});
910 0x3A: decode CC
911 {
912 0x0: Trap::tcci({{
913 if(passesCondition(Ccr<3:0>, COND2))
914 {
915#if FULL_SYSTEM
916 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
917 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
918 fault = new TrapInstruction(lTrapNum);
919#else
920 DPRINTF(Sparc, "The syscall number is %d\n", R1);
921 xc->syscall(R1);
922#endif
923 }
924 }}, IsSerializeAfter, IsNonSpeculative);
925 0x2: Trap::tccx({{
926 if(passesCondition(Ccr<7:4>, COND2))
927 {
928#if FULL_SYSTEM
929 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
930 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
931 fault = new TrapInstruction(lTrapNum);
932#else
933 DPRINTF(Sparc, "The syscall number is %d\n", R1);
934 xc->syscall(R1);
935#endif
936 }
937 }}, IsSerializeAfter, IsNonSpeculative);
938 }
939 0x3B: Nop::flush({{/*Instruction memory flush*/}});
940 0x3C: save({{
941 if(Cansave == 0)
942 {
943 if(Otherwin)
944 fault = new SpillNOther(Wstate<5:3>);
945 else
946 fault = new SpillNNormal(Wstate<2:0>);
947 }
948 else if(Cleanwin - Canrestore == 0)
949 {
950 fault = new CleanWindow;
951 }
952 else
953 {
954 Cwp = (Cwp + 1) % NWindows;
955 Rd_next = Rs1 + Rs2_or_imm13;
956 Cansave = Cansave - 1;
957 Canrestore = Canrestore + 1;
958 }
959 }});
960 0x3D: restore({{
961 if(Canrestore == 0)
962 {
963 if(Otherwin)
964 fault = new FillNOther(Wstate<5:3>);
965 else
966 fault = new FillNNormal(Wstate<2:0>);
967 }
968 else
969 {
970 Cwp = (Cwp - 1 + NWindows) % NWindows;
971 Rd_prev = Rs1 + Rs2_or_imm13;
972 Cansave = Cansave + 1;
973 Canrestore = Canrestore - 1;
974 }
975 }});
976 0x3E: decode FCN {
977 0x0: Priv::done({{
978 if(Tl == 0)
979 return new IllegalInstruction;
980
981 Cwp = Tstate<4:0>;
982 Pstate = Tstate<20:8>;
983 Asi = Tstate<31:24>;
984 Ccr = Tstate<39:32>;
985 Gl = Tstate<42:40>;
986 Hpstate = Htstate;
987 NPC = Tnpc;
988 NNPC = Tnpc + 4;
989 Tl = Tl - 1;
990 }});
991 0x1: Priv::retry({{
992 if(Tl == 0)
993 return new IllegalInstruction;
994 Cwp = Tstate<4:0>;
995 Pstate = Tstate<20:8>;
996 Asi = Tstate<31:24>;
997 Ccr = Tstate<39:32>;
998 Gl = Tstate<42:40>;
999 Hpstate = Htstate;
1000 NPC = Tpc;
1001 NNPC = Tnpc;
1002 Tl = Tl - 1;
1003 }});
1004 }
1005 }
1006 }
1007 0x3: decode OP3 {
1008 format Load {
1009 0x00: lduw({{Rd = Mem.uw;}});
1010 0x01: ldub({{Rd = Mem.ub;}});
1011 0x02: lduh({{Rd = Mem.uhw;}});
1012 0x03: ldtw({{
1013 uint64_t val = Mem.udw;
1014 RdLow = val<31:0>;
1015 RdHigh = val<63:32>;
1016 }});
1017 }
1018 format Store {
1019 0x04: stw({{Mem.uw = Rd.sw;}});
1020 0x05: stb({{Mem.ub = Rd.sb;}});
1021 0x06: sth({{Mem.uhw = Rd.shw;}});
1022 0x07: sttw({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
1023 }
1024 format Load {
1025 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
1026 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
1027 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
1028 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
1029 }
1030 0x0D: LoadStore::ldstub(
1031 {{Rd = Mem.ub;}},
1032 {{Mem.ub = 0xFF;}});
1033 0x0E: Store::stx({{Mem.udw = Rd}});
1034 0x0F: LoadStore::swap(
1035 {{uReg0 = Rd.uw;
1036 Rd.uw = Mem.uw;}},
1037 {{Mem.uw = uReg0;}});
1038 format LoadAlt {
1039 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
1040 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
1041 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
| 2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OP default Unknown::unknown()
37{
38 0x0: decode OP2
39 {
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 //bpcc
45 0x1: decode COND2
46 {
47 //Branch Always
48 0x8: decode A
49 {
50 0x0: bpa(19, {{
51 NNPC = xc->readPC() + disp;
52 }});
53 0x1: bpa(19, {{
54 NPC = xc->readPC() + disp;
55 NNPC = NPC + 4;
56 }}, ',a');
57 }
58 //Branch Never
59 0x0: decode A
60 {
61 0x0: bpn(19, {{
62 NNPC = NNPC;//Don't do anything
63 }});
64 0x1: bpn(19, {{
65 NPC = xc->readNextPC() + 4;
66 NNPC = NPC + 4;
67 }}, ',a');
68 }
69 default: decode BPCC
70 {
71 0x0: bpcci(19, {{
72 if(passesCondition(Ccr<3:0>, COND2))
73 NNPC = xc->readPC() + disp;
74 else
75 handle_annul
76 }});
77 0x2: bpccx(19, {{
78 if(passesCondition(Ccr<7:4>, COND2))
79 {
80 //warn("Took branch!\n");
81 NNPC = xc->readPC() + disp;
82 }
83 else
84 {
85 //warn("Didn't take branch!\n");
86 handle_annul
87 }
88 }});
89 }
90 }
91 //bicc
92 0x2: decode COND2
93 {
94 //Branch Always
95 0x8: decode A
96 {
97 0x0: ba(22, {{
98 NNPC = xc->readPC() + disp;
99 }});
100 0x1: ba(22, {{
101 NPC = xc->readPC() + disp;
102 NNPC = NPC + 4;
103 }}, ',a');
104 }
105 //Branch Never
106 0x0: decode A
107 {
108 0x0: bn(22, {{
109 NNPC = NNPC;//Don't do anything
110 }});
111 0x1: bn(22, {{
112 NPC = xc->readNextPC() + 4;
113 NNPC = NPC + 4;
114 }}, ',a');
115 }
116 default: bicc(22, {{
117 if(passesCondition(Ccr<3:0>, COND2))
118 NNPC = xc->readPC() + disp;
119 else
120 handle_annul
121 }});
122 }
123 }
124 0x3: decode RCOND2
125 {
126 format BranchSplit
127 {
128 0x1: bpreq({{
129 if(Rs1.sdw == 0)
130 NNPC = xc->readPC() + disp;
131 else
132 handle_annul
133 }});
134 0x2: bprle({{
135 if(Rs1.sdw <= 0)
136 NNPC = xc->readPC() + disp;
137 else
138 handle_annul
139 }});
140 0x3: bprl({{
141 if(Rs1.sdw < 0)
142 NNPC = xc->readPC() + disp;
143 else
144 handle_annul
145 }});
146 0x5: bprne({{
147 if(Rs1.sdw != 0)
148 NNPC = xc->readPC() + disp;
149 else
150 handle_annul
151 }});
152 0x6: bprg({{
153 if(Rs1.sdw > 0)
154 NNPC = xc->readPC() + disp;
155 else
156 handle_annul
157 }});
158 0x7: bprge({{
159 if(Rs1.sdw >= 0)
160 NNPC = xc->readPC() + disp;
161 else
162 handle_annul
163 }});
164 }
165 }
166 //SETHI (or NOP if rd == 0 and imm == 0)
167 0x4: SetHi::sethi({{Rd.udw = imm;}});
168 0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
169 0x6: Trap::fbfcc({{fault = new FpDisabled;}});
170 }
171 0x1: BranchN::call(30, {{
172 R15 = xc->readPC();
173 NNPC = R15 + disp;
174 }});
175 0x2: decode OP3 {
176 format IntOp {
177 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
178 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
179 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
180 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
181 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
182 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}});
183 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}});
184 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
185 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
186 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
187 0x0A: umul({{
188 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
189 Y = Rd<63:32>;
190 }});
191 0x0B: smul({{
192 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
193 Y = Rd.sdw;
194 }});
195 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
196 0x0D: udivx({{
197 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
198 else Rd.udw = Rs1.udw / Rs2_or_imm13;
199 }});
200 0x0E: udiv({{
201 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
202 else
203 {
204 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
205 if(Rd.udw >> 32 != 0)
206 Rd.udw = 0xFFFFFFFF;
207 }
208 }});
209 0x0F: sdiv({{
210 if(Rs2_or_imm13.sdw == 0)
211 fault = new DivisionByZero;
212 else
213 {
214 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
215 if(Rd.udw<63:31> != 0)
216 Rd.udw = 0x7FFFFFFF;
217 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
218 Rd.udw = 0xFFFFFFFF80000000ULL;
219 }
220 }});
221 }
222 format IntOpCc {
223 0x10: addcc({{
224 int64_t resTemp, val2 = Rs2_or_imm13;
225 Rd = resTemp = Rs1 + val2;}},
226 {{(Rs1<31:0> + val2<31:0>)<32:>}},
227 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
228 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
229 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
230 );
231 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
232 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
233 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
234 0x14: subcc({{
235 int64_t val2 = Rs2_or_imm13;
236 Rd = Rs1 - val2;}},
237 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
238 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
239 {{(~(Rs1<63:1> + (~val2)<63:1> +
240 (Rs1 | ~val2)<0:>))<63:>}},
241 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
242 );
243 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
244 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
245 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
246 0x18: addccc({{
247 int64_t resTemp, val2 = Rs2_or_imm13;
248 int64_t carryin = Ccr<0:0>;
249 Rd = resTemp = Rs1 + val2 + carryin;}},
250 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
251 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
252 {{(Rs1<63:1> + val2<63:1> +
253 ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
254 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
255 );
256 0x1A: IntOpCcRes::umulcc({{
257 uint64_t resTemp;
258 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
259 Y = resTemp<63:32>;}});
260 0x1B: IntOpCcRes::smulcc({{
261 int64_t resTemp;
262 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>;
263 Y = resTemp<63:32>;}});
264 0x1C: subccc({{
265 int64_t resTemp, val2 = Rs2_or_imm13;
266 int64_t carryin = Ccr<0:0>;
267 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
268 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
269 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
270 {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
271 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
272 );
273 0x1D: IntOpCcRes::udivxcc({{
274 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
275 else Rd = Rs1.udw / Rs2_or_imm13.udw;}});
276 0x1E: udivcc({{
277 uint32_t resTemp, val2 = Rs2_or_imm13.udw;
278 int32_t overflow = 0;
279 if(val2 == 0) fault = new DivisionByZero;
280 else
281 {
282 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
283 overflow = (resTemp<63:32> != 0);
284 if(overflow) Rd = resTemp = 0xFFFFFFFF;
285 else Rd = resTemp;
286 } }},
287 {{0}},
288 {{overflow}},
289 {{0}},
290 {{0}}
291 );
292 0x1F: sdivcc({{
293 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
294 bool overflow = false, underflow = false;
295 if(val2 == 0) fault = new DivisionByZero;
296 else
297 {
298 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
299 overflow = (Rd<63:31> != 0);
300 underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF);
301 if(overflow) Rd = 0x7FFFFFFF;
302 else if(underflow) Rd = 0xFFFFFFFF80000000ULL;
303 } }},
304 {{0}},
305 {{overflow || underflow}},
306 {{0}},
307 {{0}}
308 );
309 0x20: taddcc({{
310 int64_t resTemp, val2 = Rs2_or_imm13;
311 Rd = resTemp = Rs1 + val2;
312 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
313 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
314 {{overflow}},
315 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
316 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
317 );
318 0x21: tsubcc({{
319 int64_t resTemp, val2 = Rs2_or_imm13;
320 Rd = resTemp = Rs1 + val2;
321 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
322 {{(Rs1<31:0> + val2<31:0>)<32:0>}},
323 {{overflow}},
324 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
325 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
326 );
327 0x22: taddcctv({{
328 int64_t val2 = Rs2_or_imm13;
329 Rd = Rs1 + val2;
330 int32_t overflow = Rs1<1:0> || val2<1:0> ||
331 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
332 if(overflow) fault = new TagOverflow;}},
333 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
334 {{overflow}},
335 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
336 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}}
337 );
338 0x23: tsubcctv({{
339 int64_t resTemp, val2 = Rs2_or_imm13;
340 Rd = resTemp = Rs1 + val2;
341 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
342 if(overflow) fault = new TagOverflow;}},
343 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
344 {{overflow}},
345 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
346 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
347 );
348 0x24: mulscc({{
349 int64_t resTemp, multiplicand = Rs2_or_imm13;
350 int32_t multiplier = Rs1<31:0>;
351 int32_t savedLSB = Rs1<0:>;
352 multiplier = multiplier<31:1> |
353 ((Ccr<3:3> ^ Ccr<1:1>) << 32);
354 if(!Y<0:>)
355 multiplicand = 0;
356 Rd = resTemp = multiplicand + multiplier;
357 Y = Y<31:1> | (savedLSB << 31);}},
358 {{((multiplicand<31:0> + multiplier<31:0>)<32:0>)}},
359 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
360 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
361 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
362 );
363 }
364 format IntOp
365 {
366 0x25: decode X {
367 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
368 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
369 }
370 0x26: decode X {
371 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
372 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
373 }
374 0x27: decode X {
375 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
376 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
377 }
378 0x28: decode RS1 {
379 0x00: NoPriv::rdy({{Rd = Y;}});
380 //1 should cause an illegal instruction exception
381 0x02: NoPriv::rdccr({{Rd = Ccr;}});
382 0x03: NoPriv::rdasi({{Rd = Asi;}});
383 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
384 0x05: NoPriv::rdpc({{
385 if(Pstate<3:>)
386 Rd = (xc->readPC())<31:0>;
387 else
388 Rd = xc->readPC();}});
389 0x06: NoPriv::rdfprs({{
390 //Wait for all fpops to finish.
391 Rd = Fprs;
392 }});
393 //7-14 should cause an illegal instruction exception
394 0x0F: decode I {
395 0x0: Nop::stbar({{/*stuff*/}});
396 0x1: Nop::membar({{/*stuff*/}});
397 }
398 0x10: Priv::rdpcr({{Rd = Pcr;}});
399 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
400 //0x12 should cause an illegal instruction exception
401 0x13: NoPriv::rdgsr({{
402 if(Fprs<2:> == 0 || Pstate<4:> == 0)
403 Rd = Gsr;
404 else
405 fault = new FpDisabled;
406 }});
407 //0x14-0x15 should cause an illegal instruction exception
408 0x16: Priv::rdsoftint({{Rd = Softint;}});
409 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
410 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}});
411 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
412 0x1A: Priv::rdstrand_sts_reg({{
413 if(Pstate<2:> && !Hpstate<2:>)
414 Rd = StrandStsReg<0:>;
415 else
416 Rd = StrandStsReg;
417 }});
418 //0x1A is supposed to be reserved, but it reads the strand
419 //status register.
420 //0x1B-0x1F should cause an illegal instruction exception
421 }
422 0x29: decode RS1 {
423 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
424 0x01: HPriv::rdhprhtstate({{
425 if(Tl == 0)
426 return new IllegalInstruction;
427 Rd = Htstate;
428 }});
429 //0x02 should cause an illegal instruction exception
430 0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
431 //0x04 should cause an illegal instruction exception
432 0x05: HPriv::rdhprhtba({{Rd = Htba;}});
433 0x06: HPriv::rdhprhver({{Rd = Hver;}});
434 //0x07-0x1E should cause an illegal instruction exception
435 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
436 }
437 0x2A: decode RS1 {
438 0x00: Priv::rdprtpc({{
439 if(Tl == 0)
440 return new IllegalInstruction;
441 Rd = Tpc;
442 }});
443 0x01: Priv::rdprtnpc({{
444 if(Tl == 0)
445 return new IllegalInstruction;
446 Rd = Tnpc;
447 }});
448 0x02: Priv::rdprtstate({{
449 if(Tl == 0)
450 return new IllegalInstruction;
451 Rd = Tstate;
452 }});
453 0x03: Priv::rdprtt({{
454 if(Tl == 0)
455 return new IllegalInstruction;
456 Rd = Tt;
457 }});
458 0x04: Priv::rdprtick({{Rd = Tick;}});
459 0x05: Priv::rdprtba({{Rd = Tba;}});
460 0x06: Priv::rdprpstate({{Rd = Pstate;}});
461 0x07: Priv::rdprtl({{Rd = Tl;}});
462 0x08: Priv::rdprpil({{Rd = Pil;}});
463 0x09: Priv::rdprcwp({{Rd = Cwp;}});
464 0x0A: Priv::rdprcansave({{Rd = Cansave;}});
465 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});
466 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});
467 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}});
468 0x0E: Priv::rdprwstate({{Rd = Wstate;}});
469 //0x0F should cause an illegal instruction exception
470 0x10: Priv::rdprgl({{Rd = Gl;}});
471 //0x11-0x1F should cause an illegal instruction exception
472 }
473 0x2B: BasicOperate::flushw({{
474 if(NWindows - 2 - Cansave == 0)
475 {
476 if(Otherwin)
477 fault = new SpillNOther(Wstate<5:3>);
478 else
479 fault = new SpillNNormal(Wstate<2:0>);
480 }
481 }});
482 0x2C: decode MOVCC3
483 {
484 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
485 0x1: decode CC
486 {
487 0x0: movcci({{
488 if(passesCondition(Ccr<3:0>, COND4))
489 Rd = Rs2_or_imm11;
490 else
491 Rd = Rd;
492 }});
493 0x2: movccx({{
494 if(passesCondition(Ccr<7:4>, COND4))
495 Rd = Rs2_or_imm11;
496 else
497 Rd = Rd;
498 }});
499 }
500 }
501 0x2D: sdivx({{
502 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
503 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
504 }});
505 0x2E: decode RS1 {
506 0x0: IntOp::popc({{
507 int64_t count = 0;
508 uint64_t temp = Rs2_or_imm13;
509 //Count the 1s in the front 4bits until none are left
510 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
511 while(temp)
512 {
513 count += oneBits[temp & 0xF];
514 temp = temp >> 4;
515 }
516 Rd = count;
517 }});
518 }
519 0x2F: decode RCOND3
520 {
521 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
522 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
523 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
524 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
525 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
526 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
527 }
528 0x30: decode RD {
529 0x00: NoPriv::wry({{Y = Rs1 ^ Rs2_or_imm13;}});
530 //0x01 should cause an illegal instruction exception
531 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
532 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
533 //0x04-0x05 should cause an illegal instruction exception
534 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
535 //0x07-0x0E should cause an illegal instruction exception
536 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
537 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
538 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
539 //0x12 should cause an illegal instruction exception
540 0x13: NoPriv::wrgsr({{
541 if(Fprs<2:> == 0 || Pstate<4:> == 0)
542 return new FpDisabled;
543 Gsr = Rs1 ^ Rs2_or_imm13;
544 }});
545 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
546 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});
547 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
548 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}});
549 0x18: NoPriv::wrstick({{
550 if(!Hpstate<2:>)
551 return new IllegalInstruction;
552 Stick = Rs1 ^ Rs2_or_imm13;
553 }});
554 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}});
555 0x1A: Priv::wrstrand_sts_reg({{
556 if(Pstate<2:> && !Hpstate<2:>)
557 StrandStsReg = StrandStsReg<63:1> |
558 (Rs1 ^ Rs2_or_imm13)<0:>;
559 else
560 StrandStsReg = Rs1 ^ Rs2_or_imm13;
561 }});
562 //0x1A is supposed to be reserved, but it writes the strand
563 //status register.
564 //0x1B-0x1F should cause an illegal instruction exception
565 }
566 0x31: decode FCN {
567 0x0: Priv::saved({{
568 assert(Cansave < NWindows - 2);
569 assert(Otherwin || Canrestore);
570 Cansave = Cansave + 1;
571 if(Otherwin == 0)
572 Canrestore = Canrestore - 1;
573 else
574 Otherwin = Otherwin - 1;
575 }});
576 0x1: Priv::restored({{
577 assert(Cansave || Otherwin);
578 assert(Canrestore < NWindows - 2);
579 Canrestore = Canrestore + 1;
580 if(Otherwin == 0)
581 Cansave = Cansave - 1;
582 else
583 Otherwin = Otherwin - 1;
584 }});
585 }
586 0x32: decode RD {
587 0x00: Priv::wrprtpc({{
588 if(Tl == 0)
589 return new IllegalInstruction;
590 else
591 Tpc = Rs1 ^ Rs2_or_imm13;
592 }});
593 0x01: Priv::wrprtnpc({{
594 if(Tl == 0)
595 return new IllegalInstruction;
596 else
597 Tnpc = Rs1 ^ Rs2_or_imm13;
598 }});
599 0x02: Priv::wrprtstate({{
600 if(Tl == 0)
601 return new IllegalInstruction;
602 else
603 Tstate = Rs1 ^ Rs2_or_imm13;
604 }});
605 0x03: Priv::wrprtt({{
606 if(Tl == 0)
607 return new IllegalInstruction;
608 else
609 Tt = Rs1 ^ Rs2_or_imm13;
610 }});
611 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
612 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
613 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
614 0x07: Priv::wrprtl({{
615 if(Pstate<2:> && !Hpstate<2:>)
616 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
617 else
618 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);
619 }});
620 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
621 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
622 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
623 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
624 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
625 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
626 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
627 //0x0F should cause an illegal instruction exception
628 0x10: Priv::wrprgl({{
629 if(Pstate<2:> && !Hpstate<2:>)
630 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL);
631 else
632 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
633 }});
634 //0x11-0x1F should cause an illegal instruction exception
635 }
636 0x33: decode RD {
637 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
638 0x01: HPriv::wrhprhtstate({{
639 if(Tl == 0)
640 return new IllegalInstruction;
641 Htstate = Rs1 ^ Rs2_or_imm13;
642 }});
643 //0x02 should cause an illegal instruction exception
644 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
645 //0x04 should cause an illegal instruction exception
646 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
647 //0x06-0x01D should cause an illegal instruction exception
648 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
649 }
650 0x34: decode OPF{
651 format BasicOperate{
652 0x01: fmovs({{
653 Frds.uw = Frs2s.uw;
654 //fsr.ftt = fsr.cexc = 0
655 Fsr &= ~(7 << 14);
656 Fsr &= ~(0x1F);
657 }});
658 0x02: fmovd({{
659 Frd.udw = Frs2.udw;
660 //fsr.ftt = fsr.cexc = 0
661 Fsr &= ~(7 << 14);
662 Fsr &= ~(0x1F);
663 }});
664 0x03: Trap::fmovq({{fault = new FpDisabled;}});
665 0x05: fnegs({{
666 Frds.uw = Frs2s.uw ^ (1UL << 31);
667 //fsr.ftt = fsr.cexc = 0
668 Fsr &= ~(7 << 14);
669 Fsr &= ~(0x1F);
670 }});
671 0x06: fnegd({{
672 Frd.udw = Frs2.udw ^ (1ULL << 63);
673 //fsr.ftt = fsr.cexc = 0
674 Fsr &= ~(7 << 14);
675 Fsr &= ~(0x1F);
676 }});
677 0x07: Trap::fnegq({{fault = new FpDisabled;}});
678 0x09: fabss({{
679 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;
680 //fsr.ftt = fsr.cexc = 0
681 Fsr &= ~(7 << 14);
682 Fsr &= ~(0x1F);
683 }});
684 0x0A: fabsd({{
685 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;
686 //fsr.ftt = fsr.cexc = 0
687 Fsr &= ~(7 << 14);
688 Fsr &= ~(0x1F);
689 }});
690 0x0B: Trap::fabsq({{fault = new FpDisabled;}});
691 0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}});
692 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}});
693 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
694 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
695 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
696 0x43: Trap::faddq({{fault = new FpDisabled;}});
697 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
698 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
699 0x47: Trap::fsubq({{fault = new FpDisabled;}});
700 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
701 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
702 0x4B: Trap::fmulq({{fault = new FpDisabled;}});
703 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
704 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
705 0x4F: Trap::fdivq({{fault = new FpDisabled;}});
706 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
707 0x6E: Trap::fdmulq({{fault = new FpDisabled;}});
708 0x81: fstox({{
709 Frd.df = (double)static_cast<int64_t>(Frs2s.sf);
710 }});
711 0x82: fdtox({{
712 Frd.df = (double)static_cast<int64_t>(Frs2.df);
713 }});
714 0x83: Trap::fqtox({{fault = new FpDisabled;}});
715 0x84: fxtos({{
716 Frds.sf = static_cast<float>((int64_t)Frs2.df);
717 }});
718 0x88: fxtod({{
719 Frd.df = static_cast<double>((int64_t)Frs2.df);
720 }});
721 0x8C: Trap::fxtoq({{fault = new FpDisabled;}});
722 0xC4: fitos({{
723 Frds.sf = static_cast<float>((int32_t)Frs2s.sf);
724 }});
725 0xC6: fdtos({{Frds.sf = Frs2.df;}});
726 0xC7: Trap::fqtos({{fault = new FpDisabled;}});
727 0xC8: fitod({{
728 Frd.df = static_cast<double>((int32_t)Frs2s.sf);
729 }});
730 0xC9: fstod({{Frd.df = Frs2s.sf;}});
731 0xCB: Trap::fqtod({{fault = new FpDisabled;}});
732 0xCC: Trap::fitoq({{fault = new FpDisabled;}});
733 0xCD: Trap::fstoq({{fault = new FpDisabled;}});
734 0xCE: Trap::fdtoq({{fault = new FpDisabled;}});
735 0xD1: fstoi({{
736 Frds.sf = (float)static_cast<int32_t>(Frs2s.sf);
737 }});
738 0xD2: fdtoi({{
739 Frds.sf = (float)static_cast<int32_t>(Frs2.df);
740 }});
741 0xD3: Trap::fqtoi({{fault = new FpDisabled;}});
742 default: Trap::fpop1({{fault = new FpDisabled;}});
743 }
744 }
745 0x35: Trap::fpop2({{fault = new FpDisabled;}});
746 //This used to be just impdep1, but now it's a whole bunch
747 //of instructions
748 0x36: decode OPF{
749 0x00: Trap::edge8({{fault = new IllegalInstruction;}});
750 0x01: Trap::edge8n({{fault = new IllegalInstruction;}});
751 0x02: Trap::edge8l({{fault = new IllegalInstruction;}});
752 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}});
753 0x04: Trap::edge16({{fault = new IllegalInstruction;}});
754 0x05: Trap::edge16n({{fault = new IllegalInstruction;}});
755 0x06: Trap::edge16l({{fault = new IllegalInstruction;}});
756 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}});
757 0x08: Trap::edge32({{fault = new IllegalInstruction;}});
758 0x09: Trap::edge32n({{fault = new IllegalInstruction;}});
759 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}});
760 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}});
761 0x10: Trap::array8({{fault = new IllegalInstruction;}});
762 0x12: Trap::array16({{fault = new IllegalInstruction;}});
763 0x14: Trap::array32({{fault = new IllegalInstruction;}});
764 0x18: BasicOperate::alignaddr({{
765 uint64_t sum = Rs1 + Rs2;
766 Rd = sum & ~7;
767 Gsr = (Gsr & ~7) | (sum & 7);
768 }});
769 0x19: Trap::bmask({{fault = new IllegalInstruction;}});
770 0x1A: BasicOperate::alignaddresslittle({{
771 uint64_t sum = Rs1 + Rs2;
772 Rd = sum & ~7;
773 Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
774 }});
775 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}});
776 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}});
777 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}});
778 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}});
779 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}});
780 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}});
781 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}});
782 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}});
783 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}});
784 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}});
785 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}});
786 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}});
787 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}});
788 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}});
789 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}});
790 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
791 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
792 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
793 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
794 0x48: BasicOperate::faligndata({{
795 uint64_t msbX = Frs1.udw;
796 uint64_t lsbX = Frs2.udw;
797 //Some special cases need to be split out, first
798 //because they're the most likely to be used, and
799 //second because otherwise, we end up shifting by
800 //greater than the width of the type being shifted,
801 //namely 64, which produces undefined results according
802 //to the C standard.
803 switch(Gsr<2:0>)
804 {
805 case 0:
806 Frd.udw = msbX;
807 break;
808 case 8:
809 Frd.udw = lsbX;
810 break;
811 default:
812 uint64_t msbShift = Gsr<2:0> * 8;
813 uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
814 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
815 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
816 Frd.udw = ((msbX & msbMask) << msbShift) |
817 ((lsbX & lsbMask) >> lsbShift);
818 }
819 }});
820 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
821 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}});
822 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}});
823 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}});
824 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}});
825 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}});
826 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}});
827 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}});
828 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}});
829 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}});
830 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}});
831 0x60: BasicOperate::fzero({{Frd.df = 0;}});
832 0x61: BasicOperate::fzeros({{Frds.sf = 0;}});
833 0x62: Trap::fnor({{fault = new IllegalInstruction;}});
834 0x63: Trap::fnors({{fault = new IllegalInstruction;}});
835 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}});
836 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}});
837 0x66: BasicOperate::fnot2({{
838 Frd.df = (double)(~((uint64_t)Frs2.df));
839 }});
840 0x67: BasicOperate::fnot2s({{
841 Frds.sf = (float)(~((uint32_t)Frs2s.sf));
842 }});
843 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}});
844 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}});
845 0x6A: BasicOperate::fnot1({{
846 Frd.df = (double)(~((uint64_t)Frs1.df));
847 }});
848 0x6B: BasicOperate::fnot1s({{
849 Frds.sf = (float)(~((uint32_t)Frs1s.sf));
850 }});
851 0x6C: Trap::fxor({{fault = new IllegalInstruction;}});
852 0x6D: Trap::fxors({{fault = new IllegalInstruction;}});
853 0x6E: Trap::fnand({{fault = new IllegalInstruction;}});
854 0x6F: Trap::fnands({{fault = new IllegalInstruction;}});
855 0x70: Trap::fand({{fault = new IllegalInstruction;}});
856 0x71: Trap::fands({{fault = new IllegalInstruction;}});
857 0x72: Trap::fxnor({{fault = new IllegalInstruction;}});
858 0x73: Trap::fxnors({{fault = new IllegalInstruction;}});
859 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}});
860 0x75: BasicOperate::fsrc1s({{Frd.uw = Frs1.uw;}});
861 0x76: Trap::fornot2({{fault = new IllegalInstruction;}});
862 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}});
863 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}});
864 0x79: BasicOperate::fsrc2s({{Frd.uw = Frs2.uw;}});
865 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}});
866 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}});
867 0x7C: Trap::for({{fault = new IllegalInstruction;}});
868 0x7D: Trap::fors({{fault = new IllegalInstruction;}});
869 0x7E: Trap::fone({{fault = new IllegalInstruction;}});
870 0x7F: Trap::fones({{fault = new IllegalInstruction;}});
871 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
872 0x81: Trap::siam({{fault = new IllegalInstruction;}});
873 }
874 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
875 0x38: Branch::jmpl({{
876 Addr target = Rs1 + Rs2_or_imm13;
877 if(target & 0x3)
878 fault = new MemAddressNotAligned;
879 else
880 {
881 Rd = xc->readPC();
882 NNPC = target;
883 }
884 }});
885 0x39: Branch::return({{
886 Addr target = Rs1 + Rs2_or_imm13;
887 if(fault == NoFault)
888 {
889 //Check for fills which are higher priority than alignment
890 //faults.
891 if(Canrestore == 0)
892 {
893 if(Otherwin)
894 fault = new FillNOther(Wstate<5:3>);
895 else
896 fault = new FillNNormal(Wstate<2:0>);
897 }
898 //Check for alignment faults
899 else if(target & 0x3)
900 fault = new MemAddressNotAligned;
901 else
902 {
903 NNPC = target;
904 Cwp = (Cwp - 1 + NWindows) % NWindows;
905 Cansave = Cansave + 1;
906 Canrestore = Canrestore - 1;
907 }
908 }
909 }});
910 0x3A: decode CC
911 {
912 0x0: Trap::tcci({{
913 if(passesCondition(Ccr<3:0>, COND2))
914 {
915#if FULL_SYSTEM
916 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
917 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
918 fault = new TrapInstruction(lTrapNum);
919#else
920 DPRINTF(Sparc, "The syscall number is %d\n", R1);
921 xc->syscall(R1);
922#endif
923 }
924 }}, IsSerializeAfter, IsNonSpeculative);
925 0x2: Trap::tccx({{
926 if(passesCondition(Ccr<7:4>, COND2))
927 {
928#if FULL_SYSTEM
929 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
930 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
931 fault = new TrapInstruction(lTrapNum);
932#else
933 DPRINTF(Sparc, "The syscall number is %d\n", R1);
934 xc->syscall(R1);
935#endif
936 }
937 }}, IsSerializeAfter, IsNonSpeculative);
938 }
939 0x3B: Nop::flush({{/*Instruction memory flush*/}});
940 0x3C: save({{
941 if(Cansave == 0)
942 {
943 if(Otherwin)
944 fault = new SpillNOther(Wstate<5:3>);
945 else
946 fault = new SpillNNormal(Wstate<2:0>);
947 }
948 else if(Cleanwin - Canrestore == 0)
949 {
950 fault = new CleanWindow;
951 }
952 else
953 {
954 Cwp = (Cwp + 1) % NWindows;
955 Rd_next = Rs1 + Rs2_or_imm13;
956 Cansave = Cansave - 1;
957 Canrestore = Canrestore + 1;
958 }
959 }});
960 0x3D: restore({{
961 if(Canrestore == 0)
962 {
963 if(Otherwin)
964 fault = new FillNOther(Wstate<5:3>);
965 else
966 fault = new FillNNormal(Wstate<2:0>);
967 }
968 else
969 {
970 Cwp = (Cwp - 1 + NWindows) % NWindows;
971 Rd_prev = Rs1 + Rs2_or_imm13;
972 Cansave = Cansave + 1;
973 Canrestore = Canrestore - 1;
974 }
975 }});
976 0x3E: decode FCN {
977 0x0: Priv::done({{
978 if(Tl == 0)
979 return new IllegalInstruction;
980
981 Cwp = Tstate<4:0>;
982 Pstate = Tstate<20:8>;
983 Asi = Tstate<31:24>;
984 Ccr = Tstate<39:32>;
985 Gl = Tstate<42:40>;
986 Hpstate = Htstate;
987 NPC = Tnpc;
988 NNPC = Tnpc + 4;
989 Tl = Tl - 1;
990 }});
991 0x1: Priv::retry({{
992 if(Tl == 0)
993 return new IllegalInstruction;
994 Cwp = Tstate<4:0>;
995 Pstate = Tstate<20:8>;
996 Asi = Tstate<31:24>;
997 Ccr = Tstate<39:32>;
998 Gl = Tstate<42:40>;
999 Hpstate = Htstate;
1000 NPC = Tpc;
1001 NNPC = Tnpc;
1002 Tl = Tl - 1;
1003 }});
1004 }
1005 }
1006 }
1007 0x3: decode OP3 {
1008 format Load {
1009 0x00: lduw({{Rd = Mem.uw;}});
1010 0x01: ldub({{Rd = Mem.ub;}});
1011 0x02: lduh({{Rd = Mem.uhw;}});
1012 0x03: ldtw({{
1013 uint64_t val = Mem.udw;
1014 RdLow = val<31:0>;
1015 RdHigh = val<63:32>;
1016 }});
1017 }
1018 format Store {
1019 0x04: stw({{Mem.uw = Rd.sw;}});
1020 0x05: stb({{Mem.ub = Rd.sb;}});
1021 0x06: sth({{Mem.uhw = Rd.shw;}});
1022 0x07: sttw({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
1023 }
1024 format Load {
1025 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
1026 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
1027 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
1028 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
1029 }
1030 0x0D: LoadStore::ldstub(
1031 {{Rd = Mem.ub;}},
1032 {{Mem.ub = 0xFF;}});
1033 0x0E: Store::stx({{Mem.udw = Rd}});
1034 0x0F: LoadStore::swap(
1035 {{uReg0 = Rd.uw;
1036 Rd.uw = Mem.uw;}},
1037 {{Mem.uw = uReg0;}});
1038 format LoadAlt {
1039 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
1040 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
1041 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
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