1// Copyright (c) 2006-2007 The Regents of The University of Michigan
| 1// Copyright (c) 2006 The Regents of The University of Michigan
|
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OP default Unknown::unknown()
37{
38 0x0: decode OP2
39 {
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 //bpcc
45 0x1: decode COND2
46 {
47 //Branch Always
48 0x8: decode A
49 {
50 0x0: bpa(19, {{
51 NNPC = xc->readPC() + disp;
52 }});
53 0x1: bpa(19, {{
54 NPC = xc->readPC() + disp;
55 NNPC = NPC + 4;
56 }}, ',a');
57 }
58 //Branch Never
59 0x0: decode A
60 {
61 0x0: bpn(19, {{
62 NNPC = NNPC;//Don't do anything
63 }});
64 0x1: bpn(19, {{
65 NPC = xc->readNextPC() + 4;
66 NNPC = NPC + 4;
67 }}, ',a');
68 }
69 default: decode BPCC
70 {
71 0x0: bpcci(19, {{
72 if(passesCondition(Ccr<3:0>, COND2))
73 NNPC = xc->readPC() + disp;
74 else
75 handle_annul
76 }});
77 0x2: bpccx(19, {{
78 if(passesCondition(Ccr<7:4>, COND2))
| 2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OP default Unknown::unknown()
37{
38 0x0: decode OP2
39 {
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 //bpcc
45 0x1: decode COND2
46 {
47 //Branch Always
48 0x8: decode A
49 {
50 0x0: bpa(19, {{
51 NNPC = xc->readPC() + disp;
52 }});
53 0x1: bpa(19, {{
54 NPC = xc->readPC() + disp;
55 NNPC = NPC + 4;
56 }}, ',a');
57 }
58 //Branch Never
59 0x0: decode A
60 {
61 0x0: bpn(19, {{
62 NNPC = NNPC;//Don't do anything
63 }});
64 0x1: bpn(19, {{
65 NPC = xc->readNextPC() + 4;
66 NNPC = NPC + 4;
67 }}, ',a');
68 }
69 default: decode BPCC
70 {
71 0x0: bpcci(19, {{
72 if(passesCondition(Ccr<3:0>, COND2))
73 NNPC = xc->readPC() + disp;
74 else
75 handle_annul
76 }});
77 0x2: bpccx(19, {{
78 if(passesCondition(Ccr<7:4>, COND2))
|
| 79 {
80 //warn("Took branch!\n");
|
79 NNPC = xc->readPC() + disp;
| 81 NNPC = xc->readPC() + disp;
|
| 82 }
|
80 else
| 83 else
|
| 84 {
85 //warn("Didn't take branch!\n");
|
81 handle_annul
| 86 handle_annul
|
| 87 }
|
82 }});
83 }
84 }
85 //bicc
86 0x2: decode COND2
87 {
88 //Branch Always
89 0x8: decode A
90 {
91 0x0: ba(22, {{
92 NNPC = xc->readPC() + disp;
93 }});
94 0x1: ba(22, {{
95 NPC = xc->readPC() + disp;
96 NNPC = NPC + 4;
97 }}, ',a');
98 }
99 //Branch Never
100 0x0: decode A
101 {
102 0x0: bn(22, {{
103 NNPC = NNPC;//Don't do anything
104 }});
105 0x1: bn(22, {{
106 NPC = xc->readNextPC() + 4;
107 NNPC = NPC + 4;
108 }}, ',a');
109 }
110 default: bicc(22, {{
111 if(passesCondition(Ccr<3:0>, COND2))
112 NNPC = xc->readPC() + disp;
113 else
114 handle_annul
115 }});
116 }
117 }
118 0x3: decode RCOND2
119 {
120 format BranchSplit
121 {
122 0x1: bpreq({{
123 if(Rs1.sdw == 0)
124 NNPC = xc->readPC() + disp;
125 else
126 handle_annul
127 }});
128 0x2: bprle({{
129 if(Rs1.sdw <= 0)
130 NNPC = xc->readPC() + disp;
131 else
132 handle_annul
133 }});
134 0x3: bprl({{
135 if(Rs1.sdw < 0)
136 NNPC = xc->readPC() + disp;
137 else
138 handle_annul
139 }});
140 0x5: bprne({{
141 if(Rs1.sdw != 0)
142 NNPC = xc->readPC() + disp;
143 else
144 handle_annul
145 }});
146 0x6: bprg({{
147 if(Rs1.sdw > 0)
148 NNPC = xc->readPC() + disp;
149 else
150 handle_annul
151 }});
152 0x7: bprge({{
153 if(Rs1.sdw >= 0)
154 NNPC = xc->readPC() + disp;
155 else
156 handle_annul
157 }});
158 }
159 }
160 //SETHI (or NOP if rd == 0 and imm == 0)
161 0x4: SetHi::sethi({{Rd.udw = imm;}});
| 88 }});
89 }
90 }
91 //bicc
92 0x2: decode COND2
93 {
94 //Branch Always
95 0x8: decode A
96 {
97 0x0: ba(22, {{
98 NNPC = xc->readPC() + disp;
99 }});
100 0x1: ba(22, {{
101 NPC = xc->readPC() + disp;
102 NNPC = NPC + 4;
103 }}, ',a');
104 }
105 //Branch Never
106 0x0: decode A
107 {
108 0x0: bn(22, {{
109 NNPC = NNPC;//Don't do anything
110 }});
111 0x1: bn(22, {{
112 NPC = xc->readNextPC() + 4;
113 NNPC = NPC + 4;
114 }}, ',a');
115 }
116 default: bicc(22, {{
117 if(passesCondition(Ccr<3:0>, COND2))
118 NNPC = xc->readPC() + disp;
119 else
120 handle_annul
121 }});
122 }
123 }
124 0x3: decode RCOND2
125 {
126 format BranchSplit
127 {
128 0x1: bpreq({{
129 if(Rs1.sdw == 0)
130 NNPC = xc->readPC() + disp;
131 else
132 handle_annul
133 }});
134 0x2: bprle({{
135 if(Rs1.sdw <= 0)
136 NNPC = xc->readPC() + disp;
137 else
138 handle_annul
139 }});
140 0x3: bprl({{
141 if(Rs1.sdw < 0)
142 NNPC = xc->readPC() + disp;
143 else
144 handle_annul
145 }});
146 0x5: bprne({{
147 if(Rs1.sdw != 0)
148 NNPC = xc->readPC() + disp;
149 else
150 handle_annul
151 }});
152 0x6: bprg({{
153 if(Rs1.sdw > 0)
154 NNPC = xc->readPC() + disp;
155 else
156 handle_annul
157 }});
158 0x7: bprge({{
159 if(Rs1.sdw >= 0)
160 NNPC = xc->readPC() + disp;
161 else
162 handle_annul
163 }});
164 }
165 }
166 //SETHI (or NOP if rd == 0 and imm == 0)
167 0x4: SetHi::sethi({{Rd.udw = imm;}});
|
162 0x5: FailUnimpl::fbpfcc();
163 0x6: FailUnimpl::fbfcc();
| 168 0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
169 0x6: Trap::fbfcc({{fault = new FpDisabled;}});
|
164 }
165 0x1: BranchN::call(30, {{
| 170 }
171 0x1: BranchN::call(30, {{
|
166 if (Pstate<3:>)
167 R15 = (xc->readPC())<31:0>;
168 else
169 R15 = xc->readPC();
| 172 R15 = xc->readPC();
|
170 NNPC = R15 + disp;
171 }});
172 0x2: decode OP3 {
173 format IntOp {
174 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
175 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
176 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
177 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
178 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
179 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}});
180 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}});
181 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
182 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
183 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
184 0x0A: umul({{
185 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
186 Y = Rd<63:32>;
187 }});
188 0x0B: smul({{
| 173 NNPC = R15 + disp;
174 }});
175 0x2: decode OP3 {
176 format IntOp {
177 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
178 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
179 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
180 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
181 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
182 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}});
183 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}});
184 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
185 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
186 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
187 0x0A: umul({{
188 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
189 Y = Rd<63:32>;
190 }});
191 0x0B: smul({{
|
189 Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
190 Y = Rd.sdw<63:32>;
| 192 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
193 Y = Rd.sdw;
|
191 }});
192 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
193 0x0D: udivx({{
194 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
195 else Rd.udw = Rs1.udw / Rs2_or_imm13;
196 }});
197 0x0E: udiv({{
198 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
199 else
200 {
201 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
202 if(Rd.udw >> 32 != 0)
203 Rd.udw = 0xFFFFFFFF;
204 }
205 }});
206 0x0F: sdiv({{
207 if(Rs2_or_imm13.sdw == 0)
208 fault = new DivisionByZero;
209 else
210 {
211 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
| 194 }});
195 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
196 0x0D: udivx({{
197 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
198 else Rd.udw = Rs1.udw / Rs2_or_imm13;
199 }});
200 0x0E: udiv({{
201 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
202 else
203 {
204 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
205 if(Rd.udw >> 32 != 0)
206 Rd.udw = 0xFFFFFFFF;
207 }
208 }});
209 0x0F: sdiv({{
210 if(Rs2_or_imm13.sdw == 0)
211 fault = new DivisionByZero;
212 else
213 {
214 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
|
212 if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max())
| 215 if(Rd.udw<63:31> != 0)
|
213 Rd.udw = 0x7FFFFFFF;
| 216 Rd.udw = 0x7FFFFFFF;
|
214 else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min())
215 Rd.udw = ULL(0xFFFFFFFF80000000);
| 217 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
218 Rd.udw = 0xFFFFFFFF80000000ULL;
|
216 }
217 }});
218 }
219 format IntOpCc {
220 0x10: addcc({{
221 int64_t resTemp, val2 = Rs2_or_imm13;
222 Rd = resTemp = Rs1 + val2;}},
223 {{(Rs1<31:0> + val2<31:0>)<32:>}},
224 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
225 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
226 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
227 );
228 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
229 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
230 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
231 0x14: subcc({{
232 int64_t val2 = Rs2_or_imm13;
233 Rd = Rs1 - val2;}},
234 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
235 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
236 {{(~(Rs1<63:1> + (~val2)<63:1> +
237 (Rs1 | ~val2)<0:>))<63:>}},
238 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
239 );
240 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
241 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
242 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
243 0x18: addccc({{
244 int64_t resTemp, val2 = Rs2_or_imm13;
245 int64_t carryin = Ccr<0:0>;
246 Rd = resTemp = Rs1 + val2 + carryin;}},
247 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
248 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
| 219 }
220 }});
221 }
222 format IntOpCc {
223 0x10: addcc({{
224 int64_t resTemp, val2 = Rs2_or_imm13;
225 Rd = resTemp = Rs1 + val2;}},
226 {{(Rs1<31:0> + val2<31:0>)<32:>}},
227 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
228 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
229 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
230 );
231 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
232 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
233 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
234 0x14: subcc({{
235 int64_t val2 = Rs2_or_imm13;
236 Rd = Rs1 - val2;}},
237 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
238 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
239 {{(~(Rs1<63:1> + (~val2)<63:1> +
240 (Rs1 | ~val2)<0:>))<63:>}},
241 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
242 );
243 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
244 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
245 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
246 0x18: addccc({{
247 int64_t resTemp, val2 = Rs2_or_imm13;
248 int64_t carryin = Ccr<0:0>;
249 Rd = resTemp = Rs1 + val2 + carryin;}},
250 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
251 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
|
249 {{((Rs1 & val2) | (~resTemp & (Rs1 | val2)))<63:>}},
| 252 {{(Rs1<63:1> + val2<63:1> +
253 ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
|
250 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
251 );
| 254 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
255 );
|
252 0x1A: umulcc({{
| 256 0x1A: IntOpCcRes::umulcc({{
|
253 uint64_t resTemp;
254 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
| 257 uint64_t resTemp;
258 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
|
255 Y = resTemp<63:32>;}},
256 {{0}},{{0}},{{0}},{{0}});
257 0x1B: smulcc({{
| 259 Y = resTemp<63:32>;}});
260 0x1B: IntOpCcRes::smulcc({{
|
258 int64_t resTemp;
| 261 int64_t resTemp;
|
259 Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
260 Y = resTemp<63:32>;}},
261 {{0}},{{0}},{{0}},{{0}});
| 262 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>;
263 Y = resTemp<63:32>;}});
|
262 0x1C: subccc({{
263 int64_t resTemp, val2 = Rs2_or_imm13;
264 int64_t carryin = Ccr<0:0>;
265 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
| 264 0x1C: subccc({{
265 int64_t resTemp, val2 = Rs2_or_imm13;
266 int64_t carryin = Ccr<0:0>;
267 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
|
266 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<31:>}},
| 268 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
|
267 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
| 269 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
|
268 {{((~Rs1 & val2) | (resTemp & (~Rs1 | val2)))<63:>}},
| 270 {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
|
269 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
270 );
| 271 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
272 );
|
271 0x1D: udivxcc({{
| 273 0x1D: IntOpCcRes::udivxcc({{
|
272 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
| 274 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
|
273 else Rd = Rs1.udw / Rs2_or_imm13.udw;}}
274 ,{{0}},{{0}},{{0}},{{0}});
| 275 else Rd = Rs1.udw / Rs2_or_imm13.udw;}});
|
275 0x1E: udivcc({{
276 uint32_t resTemp, val2 = Rs2_or_imm13.udw;
277 int32_t overflow = 0;
278 if(val2 == 0) fault = new DivisionByZero;
279 else
280 {
281 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
282 overflow = (resTemp<63:32> != 0);
283 if(overflow) Rd = resTemp = 0xFFFFFFFF;
284 else Rd = resTemp;
285 } }},
286 {{0}},
287 {{overflow}},
288 {{0}},
289 {{0}}
290 );
291 0x1F: sdivcc({{
292 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
293 bool overflow = false, underflow = false;
294 if(val2 == 0) fault = new DivisionByZero;
295 else
296 {
297 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
| 276 0x1E: udivcc({{
277 uint32_t resTemp, val2 = Rs2_or_imm13.udw;
278 int32_t overflow = 0;
279 if(val2 == 0) fault = new DivisionByZero;
280 else
281 {
282 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
283 overflow = (resTemp<63:32> != 0);
284 if(overflow) Rd = resTemp = 0xFFFFFFFF;
285 else Rd = resTemp;
286 } }},
287 {{0}},
288 {{overflow}},
289 {{0}},
290 {{0}}
291 );
292 0x1F: sdivcc({{
293 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
294 bool overflow = false, underflow = false;
295 if(val2 == 0) fault = new DivisionByZero;
296 else
297 {
298 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
|
298 overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max());
299 underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min());
| 299 overflow = (Rd<63:31> != 0);
300 underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF);
|
300 if(overflow) Rd = 0x7FFFFFFF;
| 301 if(overflow) Rd = 0x7FFFFFFF;
|
301 else if(underflow) Rd = ULL(0xFFFFFFFF80000000);
| 302 else if(underflow) Rd = 0xFFFFFFFF80000000ULL;
|
302 } }},
303 {{0}},
304 {{overflow || underflow}},
305 {{0}},
306 {{0}}
307 );
308 0x20: taddcc({{
309 int64_t resTemp, val2 = Rs2_or_imm13;
310 Rd = resTemp = Rs1 + val2;
311 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
312 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
313 {{overflow}},
314 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
315 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
316 );
317 0x21: tsubcc({{
318 int64_t resTemp, val2 = Rs2_or_imm13;
319 Rd = resTemp = Rs1 + val2;
320 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
321 {{(Rs1<31:0> + val2<31:0>)<32:0>}},
322 {{overflow}},
323 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
324 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
325 );
326 0x22: taddcctv({{
327 int64_t val2 = Rs2_or_imm13;
328 Rd = Rs1 + val2;
329 int32_t overflow = Rs1<1:0> || val2<1:0> ||
330 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
331 if(overflow) fault = new TagOverflow;}},
332 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
333 {{overflow}},
334 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
335 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}}
336 );
337 0x23: tsubcctv({{
338 int64_t resTemp, val2 = Rs2_or_imm13;
339 Rd = resTemp = Rs1 + val2;
340 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
341 if(overflow) fault = new TagOverflow;}},
342 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
343 {{overflow}},
344 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
345 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
346 );
347 0x24: mulscc({{
348 int64_t resTemp, multiplicand = Rs2_or_imm13;
349 int32_t multiplier = Rs1<31:0>;
350 int32_t savedLSB = Rs1<0:>;
351 multiplier = multiplier<31:1> |
352 ((Ccr<3:3> ^ Ccr<1:1>) << 32);
353 if(!Y<0:>)
354 multiplicand = 0;
355 Rd = resTemp = multiplicand + multiplier;
356 Y = Y<31:1> | (savedLSB << 31);}},
357 {{((multiplicand<31:0> + multiplier<31:0>)<32:0>)}},
358 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
359 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
360 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
361 );
362 }
363 format IntOp
364 {
365 0x25: decode X {
366 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
367 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
368 }
369 0x26: decode X {
370 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
371 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
372 }
373 0x27: decode X {
374 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
375 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
376 }
377 0x28: decode RS1 {
| 303 } }},
304 {{0}},
305 {{overflow || underflow}},
306 {{0}},
307 {{0}}
308 );
309 0x20: taddcc({{
310 int64_t resTemp, val2 = Rs2_or_imm13;
311 Rd = resTemp = Rs1 + val2;
312 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
313 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
314 {{overflow}},
315 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
316 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
317 );
318 0x21: tsubcc({{
319 int64_t resTemp, val2 = Rs2_or_imm13;
320 Rd = resTemp = Rs1 + val2;
321 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
322 {{(Rs1<31:0> + val2<31:0>)<32:0>}},
323 {{overflow}},
324 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
325 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
326 );
327 0x22: taddcctv({{
328 int64_t val2 = Rs2_or_imm13;
329 Rd = Rs1 + val2;
330 int32_t overflow = Rs1<1:0> || val2<1:0> ||
331 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
332 if(overflow) fault = new TagOverflow;}},
333 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
334 {{overflow}},
335 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
336 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}}
337 );
338 0x23: tsubcctv({{
339 int64_t resTemp, val2 = Rs2_or_imm13;
340 Rd = resTemp = Rs1 + val2;
341 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
342 if(overflow) fault = new TagOverflow;}},
343 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
344 {{overflow}},
345 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
346 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
347 );
348 0x24: mulscc({{
349 int64_t resTemp, multiplicand = Rs2_or_imm13;
350 int32_t multiplier = Rs1<31:0>;
351 int32_t savedLSB = Rs1<0:>;
352 multiplier = multiplier<31:1> |
353 ((Ccr<3:3> ^ Ccr<1:1>) << 32);
354 if(!Y<0:>)
355 multiplicand = 0;
356 Rd = resTemp = multiplicand + multiplier;
357 Y = Y<31:1> | (savedLSB << 31);}},
358 {{((multiplicand<31:0> + multiplier<31:0>)<32:0>)}},
359 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
360 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
361 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
362 );
363 }
364 format IntOp
365 {
366 0x25: decode X {
367 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
368 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
369 }
370 0x26: decode X {
371 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
372 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
373 }
374 0x27: decode X {
375 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
376 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
377 }
378 0x28: decode RS1 {
|
378 0x00: NoPriv::rdy({{Rd = Y<31:0>;}});
| 379 0x00: NoPriv::rdy({{Rd = Y;}});
|
379 //1 should cause an illegal instruction exception
380 0x02: NoPriv::rdccr({{Rd = Ccr;}});
381 0x03: NoPriv::rdasi({{Rd = Asi;}});
382 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
383 0x05: NoPriv::rdpc({{
384 if(Pstate<3:>)
385 Rd = (xc->readPC())<31:0>;
386 else
387 Rd = xc->readPC();}});
388 0x06: NoPriv::rdfprs({{
389 //Wait for all fpops to finish.
390 Rd = Fprs;
391 }});
392 //7-14 should cause an illegal instruction exception
393 0x0F: decode I {
394 0x0: Nop::stbar({{/*stuff*/}});
395 0x1: Nop::membar({{/*stuff*/}});
396 }
397 0x10: Priv::rdpcr({{Rd = Pcr;}});
398 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
399 //0x12 should cause an illegal instruction exception
400 0x13: NoPriv::rdgsr({{
401 if(Fprs<2:> == 0 || Pstate<4:> == 0)
402 Rd = Gsr;
403 else
404 fault = new FpDisabled;
405 }});
406 //0x14-0x15 should cause an illegal instruction exception
407 0x16: Priv::rdsoftint({{Rd = Softint;}});
408 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
409 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}});
410 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
411 0x1A: Priv::rdstrand_sts_reg({{
412 if(Pstate<2:> && !Hpstate<2:>)
413 Rd = StrandStsReg<0:>;
414 else
415 Rd = StrandStsReg;
416 }});
417 //0x1A is supposed to be reserved, but it reads the strand
418 //status register.
419 //0x1B-0x1F should cause an illegal instruction exception
420 }
421 0x29: decode RS1 {
422 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
423 0x01: HPriv::rdhprhtstate({{
424 if(Tl == 0)
425 return new IllegalInstruction;
426 Rd = Htstate;
427 }});
428 //0x02 should cause an illegal instruction exception
429 0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
430 //0x04 should cause an illegal instruction exception
431 0x05: HPriv::rdhprhtba({{Rd = Htba;}});
432 0x06: HPriv::rdhprhver({{Rd = Hver;}});
433 //0x07-0x1E should cause an illegal instruction exception
434 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
435 }
436 0x2A: decode RS1 {
437 0x00: Priv::rdprtpc({{
438 if(Tl == 0)
439 return new IllegalInstruction;
440 Rd = Tpc;
441 }});
442 0x01: Priv::rdprtnpc({{
443 if(Tl == 0)
444 return new IllegalInstruction;
445 Rd = Tnpc;
446 }});
447 0x02: Priv::rdprtstate({{
448 if(Tl == 0)
449 return new IllegalInstruction;
450 Rd = Tstate;
451 }});
452 0x03: Priv::rdprtt({{
453 if(Tl == 0)
454 return new IllegalInstruction;
455 Rd = Tt;
456 }});
457 0x04: Priv::rdprtick({{Rd = Tick;}});
458 0x05: Priv::rdprtba({{Rd = Tba;}});
459 0x06: Priv::rdprpstate({{Rd = Pstate;}});
460 0x07: Priv::rdprtl({{Rd = Tl;}});
461 0x08: Priv::rdprpil({{Rd = Pil;}});
462 0x09: Priv::rdprcwp({{Rd = Cwp;}});
463 0x0A: Priv::rdprcansave({{Rd = Cansave;}});
464 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});
465 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});
466 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}});
467 0x0E: Priv::rdprwstate({{Rd = Wstate;}});
468 //0x0F should cause an illegal instruction exception
469 0x10: Priv::rdprgl({{Rd = Gl;}});
470 //0x11-0x1F should cause an illegal instruction exception
471 }
472 0x2B: BasicOperate::flushw({{
| 380 //1 should cause an illegal instruction exception
381 0x02: NoPriv::rdccr({{Rd = Ccr;}});
382 0x03: NoPriv::rdasi({{Rd = Asi;}});
383 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
384 0x05: NoPriv::rdpc({{
385 if(Pstate<3:>)
386 Rd = (xc->readPC())<31:0>;
387 else
388 Rd = xc->readPC();}});
389 0x06: NoPriv::rdfprs({{
390 //Wait for all fpops to finish.
391 Rd = Fprs;
392 }});
393 //7-14 should cause an illegal instruction exception
394 0x0F: decode I {
395 0x0: Nop::stbar({{/*stuff*/}});
396 0x1: Nop::membar({{/*stuff*/}});
397 }
398 0x10: Priv::rdpcr({{Rd = Pcr;}});
399 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
400 //0x12 should cause an illegal instruction exception
401 0x13: NoPriv::rdgsr({{
402 if(Fprs<2:> == 0 || Pstate<4:> == 0)
403 Rd = Gsr;
404 else
405 fault = new FpDisabled;
406 }});
407 //0x14-0x15 should cause an illegal instruction exception
408 0x16: Priv::rdsoftint({{Rd = Softint;}});
409 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
410 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}});
411 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
412 0x1A: Priv::rdstrand_sts_reg({{
413 if(Pstate<2:> && !Hpstate<2:>)
414 Rd = StrandStsReg<0:>;
415 else
416 Rd = StrandStsReg;
417 }});
418 //0x1A is supposed to be reserved, but it reads the strand
419 //status register.
420 //0x1B-0x1F should cause an illegal instruction exception
421 }
422 0x29: decode RS1 {
423 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
424 0x01: HPriv::rdhprhtstate({{
425 if(Tl == 0)
426 return new IllegalInstruction;
427 Rd = Htstate;
428 }});
429 //0x02 should cause an illegal instruction exception
430 0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
431 //0x04 should cause an illegal instruction exception
432 0x05: HPriv::rdhprhtba({{Rd = Htba;}});
433 0x06: HPriv::rdhprhver({{Rd = Hver;}});
434 //0x07-0x1E should cause an illegal instruction exception
435 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
436 }
437 0x2A: decode RS1 {
438 0x00: Priv::rdprtpc({{
439 if(Tl == 0)
440 return new IllegalInstruction;
441 Rd = Tpc;
442 }});
443 0x01: Priv::rdprtnpc({{
444 if(Tl == 0)
445 return new IllegalInstruction;
446 Rd = Tnpc;
447 }});
448 0x02: Priv::rdprtstate({{
449 if(Tl == 0)
450 return new IllegalInstruction;
451 Rd = Tstate;
452 }});
453 0x03: Priv::rdprtt({{
454 if(Tl == 0)
455 return new IllegalInstruction;
456 Rd = Tt;
457 }});
458 0x04: Priv::rdprtick({{Rd = Tick;}});
459 0x05: Priv::rdprtba({{Rd = Tba;}});
460 0x06: Priv::rdprpstate({{Rd = Pstate;}});
461 0x07: Priv::rdprtl({{Rd = Tl;}});
462 0x08: Priv::rdprpil({{Rd = Pil;}});
463 0x09: Priv::rdprcwp({{Rd = Cwp;}});
464 0x0A: Priv::rdprcansave({{Rd = Cansave;}});
465 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});
466 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});
467 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}});
468 0x0E: Priv::rdprwstate({{Rd = Wstate;}});
469 //0x0F should cause an illegal instruction exception
470 0x10: Priv::rdprgl({{Rd = Gl;}});
471 //0x11-0x1F should cause an illegal instruction exception
472 }
473 0x2B: BasicOperate::flushw({{
|
473 if(NWindows - 2 - Cansave != 0)
| 474 if(NWindows - 2 - Cansave == 0)
|
474 {
475 if(Otherwin)
| 475 {
476 if(Otherwin)
|
476 fault = new SpillNOther(4*Wstate<5:3>);
| 477 fault = new SpillNOther(Wstate<5:3>);
|
477 else
| 478 else
|
478 fault = new SpillNNormal(4*Wstate<2:0>);
| 479 fault = new SpillNNormal(Wstate<2:0>);
|
479 }
480 }});
481 0x2C: decode MOVCC3
482 {
483 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
484 0x1: decode CC
485 {
486 0x0: movcci({{
487 if(passesCondition(Ccr<3:0>, COND4))
488 Rd = Rs2_or_imm11;
489 else
490 Rd = Rd;
491 }});
492 0x2: movccx({{
493 if(passesCondition(Ccr<7:4>, COND4))
494 Rd = Rs2_or_imm11;
495 else
496 Rd = Rd;
497 }});
498 }
499 }
500 0x2D: sdivx({{
501 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
502 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
503 }});
| 480 }
481 }});
482 0x2C: decode MOVCC3
483 {
484 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
485 0x1: decode CC
486 {
487 0x0: movcci({{
488 if(passesCondition(Ccr<3:0>, COND4))
489 Rd = Rs2_or_imm11;
490 else
491 Rd = Rd;
492 }});
493 0x2: movccx({{
494 if(passesCondition(Ccr<7:4>, COND4))
495 Rd = Rs2_or_imm11;
496 else
497 Rd = Rd;
498 }});
499 }
500 }
501 0x2D: sdivx({{
502 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
503 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
504 }});
|
504 0x2E: Trap::popc({{fault = new IllegalInstruction;}});
| 505 0x2E: decode RS1 {
506 0x0: IntOp::popc({{
507 int64_t count = 0;
508 uint64_t temp = Rs2_or_imm13;
509 //Count the 1s in the front 4bits until none are left
510 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
511 while(temp)
512 {
513 count += oneBits[temp & 0xF];
514 temp = temp >> 4;
515 }
516 Rd = count;
517 }});
518 }
|
505 0x2F: decode RCOND3
506 {
507 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
508 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
509 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
510 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
511 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
512 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
513 }
514 0x30: decode RD {
| 519 0x2F: decode RCOND3
520 {
521 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
522 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
523 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
524 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
525 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
526 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
527 }
528 0x30: decode RD {
|
515 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}});
| 529 0x00: NoPriv::wry({{Y = Rs1 ^ Rs2_or_imm13;}});
|
516 //0x01 should cause an illegal instruction exception
517 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
518 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
519 //0x04-0x05 should cause an illegal instruction exception
520 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
521 //0x07-0x0E should cause an illegal instruction exception
522 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
523 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
524 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
525 //0x12 should cause an illegal instruction exception
526 0x13: NoPriv::wrgsr({{
527 if(Fprs<2:> == 0 || Pstate<4:> == 0)
528 return new FpDisabled;
529 Gsr = Rs1 ^ Rs2_or_imm13;
530 }});
531 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
532 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});
533 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
534 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}});
535 0x18: NoPriv::wrstick({{
536 if(!Hpstate<2:>)
537 return new IllegalInstruction;
538 Stick = Rs1 ^ Rs2_or_imm13;
539 }});
540 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}});
541 0x1A: Priv::wrstrand_sts_reg({{
542 if(Pstate<2:> && !Hpstate<2:>)
543 StrandStsReg = StrandStsReg<63:1> |
544 (Rs1 ^ Rs2_or_imm13)<0:>;
545 else
546 StrandStsReg = Rs1 ^ Rs2_or_imm13;
547 }});
548 //0x1A is supposed to be reserved, but it writes the strand
549 //status register.
550 //0x1B-0x1F should cause an illegal instruction exception
551 }
552 0x31: decode FCN {
553 0x0: Priv::saved({{
554 assert(Cansave < NWindows - 2);
555 assert(Otherwin || Canrestore);
556 Cansave = Cansave + 1;
557 if(Otherwin == 0)
558 Canrestore = Canrestore - 1;
559 else
560 Otherwin = Otherwin - 1;
561 }});
562 0x1: Priv::restored({{
563 assert(Cansave || Otherwin);
564 assert(Canrestore < NWindows - 2);
565 Canrestore = Canrestore + 1;
566 if(Otherwin == 0)
567 Cansave = Cansave - 1;
568 else
569 Otherwin = Otherwin - 1;
| 530 //0x01 should cause an illegal instruction exception
531 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
532 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
533 //0x04-0x05 should cause an illegal instruction exception
534 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
535 //0x07-0x0E should cause an illegal instruction exception
536 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
537 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
538 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
539 //0x12 should cause an illegal instruction exception
540 0x13: NoPriv::wrgsr({{
541 if(Fprs<2:> == 0 || Pstate<4:> == 0)
542 return new FpDisabled;
543 Gsr = Rs1 ^ Rs2_or_imm13;
544 }});
545 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
546 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});
547 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
548 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}});
549 0x18: NoPriv::wrstick({{
550 if(!Hpstate<2:>)
551 return new IllegalInstruction;
552 Stick = Rs1 ^ Rs2_or_imm13;
553 }});
554 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}});
555 0x1A: Priv::wrstrand_sts_reg({{
556 if(Pstate<2:> && !Hpstate<2:>)
557 StrandStsReg = StrandStsReg<63:1> |
558 (Rs1 ^ Rs2_or_imm13)<0:>;
559 else
560 StrandStsReg = Rs1 ^ Rs2_or_imm13;
561 }});
562 //0x1A is supposed to be reserved, but it writes the strand
563 //status register.
564 //0x1B-0x1F should cause an illegal instruction exception
565 }
566 0x31: decode FCN {
567 0x0: Priv::saved({{
568 assert(Cansave < NWindows - 2);
569 assert(Otherwin || Canrestore);
570 Cansave = Cansave + 1;
571 if(Otherwin == 0)
572 Canrestore = Canrestore - 1;
573 else
574 Otherwin = Otherwin - 1;
575 }});
576 0x1: Priv::restored({{
577 assert(Cansave || Otherwin);
578 assert(Canrestore < NWindows - 2);
579 Canrestore = Canrestore + 1;
580 if(Otherwin == 0)
581 Cansave = Cansave - 1;
582 else
583 Otherwin = Otherwin - 1;
|
570
571 if(Cleanwin < NWindows - 1)
572 Cleanwin = Cleanwin + 1;
| |
573 }});
574 }
575 0x32: decode RD {
576 0x00: Priv::wrprtpc({{
577 if(Tl == 0)
578 return new IllegalInstruction;
579 else
580 Tpc = Rs1 ^ Rs2_or_imm13;
581 }});
582 0x01: Priv::wrprtnpc({{
583 if(Tl == 0)
584 return new IllegalInstruction;
585 else
586 Tnpc = Rs1 ^ Rs2_or_imm13;
587 }});
588 0x02: Priv::wrprtstate({{
589 if(Tl == 0)
590 return new IllegalInstruction;
591 else
592 Tstate = Rs1 ^ Rs2_or_imm13;
593 }});
594 0x03: Priv::wrprtt({{
595 if(Tl == 0)
596 return new IllegalInstruction;
597 else
598 Tt = Rs1 ^ Rs2_or_imm13;
599 }});
600 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
601 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
602 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
603 0x07: Priv::wrprtl({{
604 if(Pstate<2:> && !Hpstate<2:>)
605 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
606 else
607 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);
608 }});
609 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
610 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
611 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
612 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
613 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
614 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
615 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
616 //0x0F should cause an illegal instruction exception
617 0x10: Priv::wrprgl({{
618 if(Pstate<2:> && !Hpstate<2:>)
619 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL);
620 else
621 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
622 }});
623 //0x11-0x1F should cause an illegal instruction exception
624 }
625 0x33: decode RD {
626 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
627 0x01: HPriv::wrhprhtstate({{
628 if(Tl == 0)
629 return new IllegalInstruction;
630 Htstate = Rs1 ^ Rs2_or_imm13;
631 }});
632 //0x02 should cause an illegal instruction exception
633 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
634 //0x04 should cause an illegal instruction exception
635 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
636 //0x06-0x01D should cause an illegal instruction exception
637 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
638 }
639 0x34: decode OPF{
640 format BasicOperate{
641 0x01: fmovs({{
642 Frds.uw = Frs2s.uw;
643 //fsr.ftt = fsr.cexc = 0
644 Fsr &= ~(7 << 14);
645 Fsr &= ~(0x1F);
646 }});
647 0x02: fmovd({{
648 Frd.udw = Frs2.udw;
649 //fsr.ftt = fsr.cexc = 0
650 Fsr &= ~(7 << 14);
651 Fsr &= ~(0x1F);
652 }});
| 584 }});
585 }
586 0x32: decode RD {
587 0x00: Priv::wrprtpc({{
588 if(Tl == 0)
589 return new IllegalInstruction;
590 else
591 Tpc = Rs1 ^ Rs2_or_imm13;
592 }});
593 0x01: Priv::wrprtnpc({{
594 if(Tl == 0)
595 return new IllegalInstruction;
596 else
597 Tnpc = Rs1 ^ Rs2_or_imm13;
598 }});
599 0x02: Priv::wrprtstate({{
600 if(Tl == 0)
601 return new IllegalInstruction;
602 else
603 Tstate = Rs1 ^ Rs2_or_imm13;
604 }});
605 0x03: Priv::wrprtt({{
606 if(Tl == 0)
607 return new IllegalInstruction;
608 else
609 Tt = Rs1 ^ Rs2_or_imm13;
610 }});
611 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
612 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
613 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
614 0x07: Priv::wrprtl({{
615 if(Pstate<2:> && !Hpstate<2:>)
616 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
617 else
618 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);
619 }});
620 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
621 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
622 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
623 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
624 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
625 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
626 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
627 //0x0F should cause an illegal instruction exception
628 0x10: Priv::wrprgl({{
629 if(Pstate<2:> && !Hpstate<2:>)
630 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL);
631 else
632 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
633 }});
634 //0x11-0x1F should cause an illegal instruction exception
635 }
636 0x33: decode RD {
637 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
638 0x01: HPriv::wrhprhtstate({{
639 if(Tl == 0)
640 return new IllegalInstruction;
641 Htstate = Rs1 ^ Rs2_or_imm13;
642 }});
643 //0x02 should cause an illegal instruction exception
644 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
645 //0x04 should cause an illegal instruction exception
646 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
647 //0x06-0x01D should cause an illegal instruction exception
648 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
649 }
650 0x34: decode OPF{
651 format BasicOperate{
652 0x01: fmovs({{
653 Frds.uw = Frs2s.uw;
654 //fsr.ftt = fsr.cexc = 0
655 Fsr &= ~(7 << 14);
656 Fsr &= ~(0x1F);
657 }});
658 0x02: fmovd({{
659 Frd.udw = Frs2.udw;
660 //fsr.ftt = fsr.cexc = 0
661 Fsr &= ~(7 << 14);
662 Fsr &= ~(0x1F);
663 }});
|
653 0x03: Trap::fmovq({{fault = new FpExceptionOther;}}); //unimp fpop
| 664 0x03: Trap::fmovq({{fault = new FpDisabled;}});
|
654 0x05: fnegs({{
655 Frds.uw = Frs2s.uw ^ (1UL << 31);
656 //fsr.ftt = fsr.cexc = 0
657 Fsr &= ~(7 << 14);
658 Fsr &= ~(0x1F);
659 }});
660 0x06: fnegd({{
661 Frd.udw = Frs2.udw ^ (1ULL << 63);
662 //fsr.ftt = fsr.cexc = 0
663 Fsr &= ~(7 << 14);
664 Fsr &= ~(0x1F);
665 }});
| 665 0x05: fnegs({{
666 Frds.uw = Frs2s.uw ^ (1UL << 31);
667 //fsr.ftt = fsr.cexc = 0
668 Fsr &= ~(7 << 14);
669 Fsr &= ~(0x1F);
670 }});
671 0x06: fnegd({{
672 Frd.udw = Frs2.udw ^ (1ULL << 63);
673 //fsr.ftt = fsr.cexc = 0
674 Fsr &= ~(7 << 14);
675 Fsr &= ~(0x1F);
676 }});
|
666 0x07: Trap::fnegq({{fault = new FpExceptionOther;}}); //fpop unimp
| 677 0x07: Trap::fnegq({{fault = new FpDisabled;}});
|
667 0x09: fabss({{
668 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;
669 //fsr.ftt = fsr.cexc = 0
670 Fsr &= ~(7 << 14);
671 Fsr &= ~(0x1F);
672 }});
673 0x0A: fabsd({{
674 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;
675 //fsr.ftt = fsr.cexc = 0
676 Fsr &= ~(7 << 14);
677 Fsr &= ~(0x1F);
678 }});
| 678 0x09: fabss({{
679 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;
680 //fsr.ftt = fsr.cexc = 0
681 Fsr &= ~(7 << 14);
682 Fsr &= ~(0x1F);
683 }});
684 0x0A: fabsd({{
685 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;
686 //fsr.ftt = fsr.cexc = 0
687 Fsr &= ~(7 << 14);
688 Fsr &= ~(0x1F);
689 }});
|
679 0x0B: Trap::fabsq({{fault = new FpExceptionOther;}}); //fpop unimp
680 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}});
681 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}});
682 0x2B: Trap::fsqrtq({{fault = new FpExceptionOther;}}); //unimp fpop
| 690 0x0B: Trap::fabsq({{fault = new FpDisabled;}});
691 0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}});
692 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}});
693 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
|
683 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
684 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
| 694 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
695 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
|
685 0x43: Trap::faddq({{fault = new FpExceptionOther;}}); //unimp fpop
| 696 0x43: Trap::faddq({{fault = new FpDisabled;}});
|
686 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
687 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
| 697 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
698 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
|
688 0x47: Trap::fsubq({{fault = new FpExceptionOther;}}); //unimp fpop
| 699 0x47: Trap::fsubq({{fault = new FpDisabled;}});
|
689 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
690 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
| 700 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
701 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
|
691 0x4B: Trap::fmulq({{fault = new FpExceptionOther;}}); //unimp fpop
| 702 0x4B: Trap::fmulq({{fault = new FpDisabled;}});
|
692 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
693 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
| 703 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
704 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
|
694 0x4F: Trap::fdivq({{fault = new FpExceptionOther;}}); //unimp fpop
| 705 0x4F: Trap::fdivq({{fault = new FpDisabled;}});
|
695 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
| 706 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
|
696 0x6E: Trap::fdmulq({{fault = new FpExceptionOther;}}); //unimp fpop
| 707 0x6E: Trap::fdmulq({{fault = new FpDisabled;}});
|
697 0x81: fstox({{
698 Frd.df = (double)static_cast<int64_t>(Frs2s.sf);
699 }});
700 0x82: fdtox({{
701 Frd.df = (double)static_cast<int64_t>(Frs2.df);
702 }});
| 708 0x81: fstox({{
709 Frd.df = (double)static_cast<int64_t>(Frs2s.sf);
710 }});
711 0x82: fdtox({{
712 Frd.df = (double)static_cast<int64_t>(Frs2.df);
713 }});
|
703 0x83: Trap::fqtox({{fault = new FpExceptionOther;}}); //unimp fpop
| 714 0x83: Trap::fqtox({{fault = new FpDisabled;}});
|
704 0x84: fxtos({{
705 Frds.sf = static_cast<float>((int64_t)Frs2.df);
706 }});
707 0x88: fxtod({{
708 Frd.df = static_cast<double>((int64_t)Frs2.df);
709 }});
| 715 0x84: fxtos({{
716 Frds.sf = static_cast<float>((int64_t)Frs2.df);
717 }});
718 0x88: fxtod({{
719 Frd.df = static_cast<double>((int64_t)Frs2.df);
720 }});
|
710 0x8C: Trap::fxtoq({{fault = new FpExceptionOther;}}); //unimp fpop
| 721 0x8C: Trap::fxtoq({{fault = new FpDisabled;}});
|
711 0xC4: fitos({{
712 Frds.sf = static_cast<float>((int32_t)Frs2s.sf);
713 }});
714 0xC6: fdtos({{Frds.sf = Frs2.df;}});
| 722 0xC4: fitos({{
723 Frds.sf = static_cast<float>((int32_t)Frs2s.sf);
724 }});
725 0xC6: fdtos({{Frds.sf = Frs2.df;}});
|
715 0xC7: Trap::fqtos({{fault = new FpExceptionOther;}}); //unimp fpop
| 726 0xC7: Trap::fqtos({{fault = new FpDisabled;}});
|
716 0xC8: fitod({{
717 Frd.df = static_cast<double>((int32_t)Frs2s.sf);
718 }});
719 0xC9: fstod({{Frd.df = Frs2s.sf;}});
| 727 0xC8: fitod({{
728 Frd.df = static_cast<double>((int32_t)Frs2s.sf);
729 }});
730 0xC9: fstod({{Frd.df = Frs2s.sf;}});
|
720 0xCB: Trap::fqtod({{fault = new FpExceptionOther;}}); // unimp fpop
721 0xCC: Trap::fitoq({{fault = new FpExceptionOther;}}); // unimp fpop
722 0xCD: Trap::fstoq({{fault = new FpExceptionOther;}}); // unimp fpop
723 0xCE: Trap::fdtoq({{fault = new FpExceptionOther;}}); // unimp fpop
| 731 0xCB: Trap::fqtod({{fault = new FpDisabled;}});
732 0xCC: Trap::fitoq({{fault = new FpDisabled;}});
733 0xCD: Trap::fstoq({{fault = new FpDisabled;}});
734 0xCE: Trap::fdtoq({{fault = new FpDisabled;}});
|
724 0xD1: fstoi({{
725 Frds.sf = (float)static_cast<int32_t>(Frs2s.sf);
726 }});
727 0xD2: fdtoi({{
728 Frds.sf = (float)static_cast<int32_t>(Frs2.df);
729 }});
| 735 0xD1: fstoi({{
736 Frds.sf = (float)static_cast<int32_t>(Frs2s.sf);
737 }});
738 0xD2: fdtoi({{
739 Frds.sf = (float)static_cast<int32_t>(Frs2.df);
740 }});
|
730 0xD3: Trap::fqtoi({{fault = new FpExceptionOther;}}); // unimp fpop
731 default: FailUnimpl::fpop1();
| 741 0xD3: Trap::fqtoi({{fault = new FpDisabled;}});
742 default: Trap::fpop1({{fault = new FpDisabled;}});
|
732 }
733 }
734 0x35: Trap::fpop2({{fault = new FpDisabled;}});
735 //This used to be just impdep1, but now it's a whole bunch
736 //of instructions
737 0x36: decode OPF{
| 743 }
744 }
745 0x35: Trap::fpop2({{fault = new FpDisabled;}});
746 //This used to be just impdep1, but now it's a whole bunch
747 //of instructions
748 0x36: decode OPF{
|
738 0x00: FailUnimpl::edge8();
739 0x01: FailUnimpl::edge8n();
740 0x02: FailUnimpl::edge8l();
741 0x03: FailUnimpl::edge8ln();
742 0x04: FailUnimpl::edge16();
743 0x05: FailUnimpl::edge16n();
744 0x06: FailUnimpl::edge16l();
745 0x07: FailUnimpl::edge16ln();
746 0x08: FailUnimpl::edge32();
747 0x09: FailUnimpl::edge32n();
748 0x0A: FailUnimpl::edge32l();
749 0x0B: FailUnimpl::edge32ln();
750 0x10: FailUnimpl::array8();
751 0x12: FailUnimpl::array16();
752 0x14: FailUnimpl::array32();
| 749 0x00: Trap::edge8({{fault = new IllegalInstruction;}});
750 0x01: Trap::edge8n({{fault = new IllegalInstruction;}});
751 0x02: Trap::edge8l({{fault = new IllegalInstruction;}});
752 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}});
753 0x04: Trap::edge16({{fault = new IllegalInstruction;}});
754 0x05: Trap::edge16n({{fault = new IllegalInstruction;}});
755 0x06: Trap::edge16l({{fault = new IllegalInstruction;}});
756 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}});
757 0x08: Trap::edge32({{fault = new IllegalInstruction;}});
758 0x09: Trap::edge32n({{fault = new IllegalInstruction;}});
759 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}});
760 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}});
761 0x10: Trap::array8({{fault = new IllegalInstruction;}});
762 0x12: Trap::array16({{fault = new IllegalInstruction;}});
763 0x14: Trap::array32({{fault = new IllegalInstruction;}});
|
753 0x18: BasicOperate::alignaddr({{
754 uint64_t sum = Rs1 + Rs2;
755 Rd = sum & ~7;
756 Gsr = (Gsr & ~7) | (sum & 7);
757 }});
| 764 0x18: BasicOperate::alignaddr({{
765 uint64_t sum = Rs1 + Rs2;
766 Rd = sum & ~7;
767 Gsr = (Gsr & ~7) | (sum & 7);
768 }});
|
758 0x19: FailUnimpl::bmask();
| 769 0x19: Trap::bmask({{fault = new IllegalInstruction;}});
|
759 0x1A: BasicOperate::alignaddresslittle({{
760 uint64_t sum = Rs1 + Rs2;
761 Rd = sum & ~7;
762 Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
763 }});
| 770 0x1A: BasicOperate::alignaddresslittle({{
771 uint64_t sum = Rs1 + Rs2;
772 Rd = sum & ~7;
773 Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
774 }});
|
764 0x20: FailUnimpl::fcmple16();
765 0x22: FailUnimpl::fcmpne16();
766 0x24: FailUnimpl::fcmple32();
767 0x26: FailUnimpl::fcmpne32();
768 0x28: FailUnimpl::fcmpgt16();
769 0x2A: FailUnimpl::fcmpeq16();
770 0x2C: FailUnimpl::fcmpgt32();
771 0x2E: FailUnimpl::fcmpeq32();
772 0x31: FailUnimpl::fmul8x16();
773 0x33: FailUnimpl::fmul8x16au();
774 0x35: FailUnimpl::fmul8x16al();
775 0x36: FailUnimpl::fmul8sux16();
776 0x37: FailUnimpl::fmul8ulx16();
777 0x38: FailUnimpl::fmuld8sux16();
778 0x39: FailUnimpl::fmuld8ulx16();
| 775 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}});
776 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}});
777 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}});
778 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}});
779 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}});
780 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}});
781 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}});
782 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}});
783 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}});
784 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}});
785 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}});
786 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}});
787 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}});
788 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}});
789 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}});
|
779 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
780 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
781 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
782 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
783 0x48: BasicOperate::faligndata({{
784 uint64_t msbX = Frs1.udw;
785 uint64_t lsbX = Frs2.udw;
786 //Some special cases need to be split out, first
787 //because they're the most likely to be used, and
788 //second because otherwise, we end up shifting by
789 //greater than the width of the type being shifted,
790 //namely 64, which produces undefined results according
791 //to the C standard.
792 switch(Gsr<2:0>)
793 {
794 case 0:
795 Frd.udw = msbX;
796 break;
797 case 8:
798 Frd.udw = lsbX;
799 break;
800 default:
801 uint64_t msbShift = Gsr<2:0> * 8;
802 uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
803 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
804 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
805 Frd.udw = ((msbX & msbMask) << msbShift) |
806 ((lsbX & lsbMask) >> lsbShift);
807 }
808 }});
809 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
| 790 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
791 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
792 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
793 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
794 0x48: BasicOperate::faligndata({{
795 uint64_t msbX = Frs1.udw;
796 uint64_t lsbX = Frs2.udw;
797 //Some special cases need to be split out, first
798 //because they're the most likely to be used, and
799 //second because otherwise, we end up shifting by
800 //greater than the width of the type being shifted,
801 //namely 64, which produces undefined results according
802 //to the C standard.
803 switch(Gsr<2:0>)
804 {
805 case 0:
806 Frd.udw = msbX;
807 break;
808 case 8:
809 Frd.udw = lsbX;
810 break;
811 default:
812 uint64_t msbShift = Gsr<2:0> * 8;
813 uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
814 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
815 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
816 Frd.udw = ((msbX & msbMask) << msbShift) |
817 ((lsbX & lsbMask) >> lsbShift);
818 }
819 }});
820 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
|
810 0x4C: FailUnimpl::bshuffle();
811 0x4D: FailUnimpl::fexpand();
812 0x50: FailUnimpl::fpadd16();
813 0x51: FailUnimpl::fpadd16s();
814 0x52: FailUnimpl::fpadd32();
815 0x53: FailUnimpl::fpadd32s();
816 0x54: FailUnimpl::fpsub16();
817 0x55: FailUnimpl::fpsub16s();
818 0x56: FailUnimpl::fpsub32();
819 0x57: FailUnimpl::fpsub32s();
| 821 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}});
822 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}});
823 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}});
824 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}});
825 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}});
826 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}});
827 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}});
828 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}});
829 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}});
830 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}});
|
820 0x60: BasicOperate::fzero({{Frd.df = 0;}});
821 0x61: BasicOperate::fzeros({{Frds.sf = 0;}});
| 831 0x60: BasicOperate::fzero({{Frd.df = 0;}});
832 0x61: BasicOperate::fzeros({{Frds.sf = 0;}});
|
822 0x62: FailUnimpl::fnor();
823 0x63: FailUnimpl::fnors();
824 0x64: FailUnimpl::fandnot2();
825 0x65: FailUnimpl::fandnot2s();
| 833 0x62: Trap::fnor({{fault = new IllegalInstruction;}});
834 0x63: Trap::fnors({{fault = new IllegalInstruction;}});
835 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}});
836 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}});
|
826 0x66: BasicOperate::fnot2({{
827 Frd.df = (double)(~((uint64_t)Frs2.df));
828 }});
829 0x67: BasicOperate::fnot2s({{
830 Frds.sf = (float)(~((uint32_t)Frs2s.sf));
831 }});
| 837 0x66: BasicOperate::fnot2({{
838 Frd.df = (double)(~((uint64_t)Frs2.df));
839 }});
840 0x67: BasicOperate::fnot2s({{
841 Frds.sf = (float)(~((uint32_t)Frs2s.sf));
842 }});
|
832 0x68: FailUnimpl::fandnot1();
833 0x69: FailUnimpl::fandnot1s();
| 843 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}});
844 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}});
|
834 0x6A: BasicOperate::fnot1({{
835 Frd.df = (double)(~((uint64_t)Frs1.df));
836 }});
837 0x6B: BasicOperate::fnot1s({{
838 Frds.sf = (float)(~((uint32_t)Frs1s.sf));
839 }});
| 845 0x6A: BasicOperate::fnot1({{
846 Frd.df = (double)(~((uint64_t)Frs1.df));
847 }});
848 0x6B: BasicOperate::fnot1s({{
849 Frds.sf = (float)(~((uint32_t)Frs1s.sf));
850 }});
|
840 0x6C: FailUnimpl::fxor();
841 0x6D: FailUnimpl::fxors();
842 0x6E: FailUnimpl::fnand();
843 0x6F: FailUnimpl::fnands();
844 0x70: FailUnimpl::fand();
845 0x71: FailUnimpl::fands();
846 0x72: FailUnimpl::fxnor();
847 0x73: FailUnimpl::fxnors();
| 851 0x6C: Trap::fxor({{fault = new IllegalInstruction;}});
852 0x6D: Trap::fxors({{fault = new IllegalInstruction;}});
853 0x6E: Trap::fnand({{fault = new IllegalInstruction;}});
854 0x6F: Trap::fnands({{fault = new IllegalInstruction;}});
855 0x70: Trap::fand({{fault = new IllegalInstruction;}});
856 0x71: Trap::fands({{fault = new IllegalInstruction;}});
857 0x72: Trap::fxnor({{fault = new IllegalInstruction;}});
858 0x73: Trap::fxnors({{fault = new IllegalInstruction;}});
|
848 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}});
| 859 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}});
|
849 0x75: BasicOperate::fsrc1s({{Frds.uw = Frs1s.uw;}});
850 0x76: FailUnimpl::fornot2();
851 0x77: FailUnimpl::fornot2s();
| 860 0x75: BasicOperate::fsrc1s({{Frd.uw = Frs1.uw;}});
861 0x76: Trap::fornot2({{fault = new IllegalInstruction;}});
862 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}});
|
852 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}});
| 863 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}});
|
853 0x79: BasicOperate::fsrc2s({{Frds.uw = Frs2s.uw;}});
854 0x7A: FailUnimpl::fornot1();
855 0x7B: FailUnimpl::fornot1s();
856 0x7C: FailUnimpl::for();
857 0x7D: FailUnimpl::fors();
858 0x7E: BasicOperate::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}});
859 0x7F: BasicOperate::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}});
| 864 0x79: BasicOperate::fsrc2s({{Frd.uw = Frs2.uw;}});
865 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}});
866 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}});
867 0x7C: Trap::for({{fault = new IllegalInstruction;}});
868 0x7D: Trap::fors({{fault = new IllegalInstruction;}});
869 0x7E: Trap::fone({{fault = new IllegalInstruction;}});
870 0x7F: Trap::fones({{fault = new IllegalInstruction;}});
|
860 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
| 871 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
|
861 0x81: FailUnimpl::siam();
| 872 0x81: Trap::siam({{fault = new IllegalInstruction;}});
|
862 }
863 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
864 0x38: Branch::jmpl({{
865 Addr target = Rs1 + Rs2_or_imm13;
866 if(target & 0x3)
867 fault = new MemAddressNotAligned;
868 else
869 {
| 873 }
874 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
875 0x38: Branch::jmpl({{
876 Addr target = Rs1 + Rs2_or_imm13;
877 if(target & 0x3)
878 fault = new MemAddressNotAligned;
879 else
880 {
|
870 if (Pstate<3:>)
871 Rd = (xc->readPC())<31:0>;
872 else
873 Rd = xc->readPC();
| 881 Rd = xc->readPC();
|
874 NNPC = target;
875 }
876 }});
877 0x39: Branch::return({{
| 882 NNPC = target;
883 }
884 }});
885 0x39: Branch::return({{
|
878 //If both MemAddressNotAligned and
879 //a fill trap happen, it's not clear
880 //which one should be returned.
| |
881 Addr target = Rs1 + Rs2_or_imm13;
| 886 Addr target = Rs1 + Rs2_or_imm13;
|
882 if(target & 0x3)
883 fault = new MemAddressNotAligned;
884 else
885 NNPC = target;
| |
886 if(fault == NoFault)
887 {
| 887 if(fault == NoFault)
888 {
|
| 889 //Check for fills which are higher priority than alignment
890 //faults.
|
888 if(Canrestore == 0)
889 {
890 if(Otherwin)
| 891 if(Canrestore == 0)
892 {
893 if(Otherwin)
|
891 fault = new FillNOther(4*Wstate<5:3>);
| 894 fault = new FillNOther(Wstate<5:3>);
|
892 else
| 895 else
|
893 fault = new FillNNormal(4*Wstate<2:0>);
| 896 fault = new FillNNormal(Wstate<2:0>);
|
894 }
| 897 }
|
| 898 //Check for alignment faults
899 else if(target & 0x3)
900 fault = new MemAddressNotAligned;
|
895 else
896 {
| 901 else
902 {
|
897 //CWP should be set directly so that it always happens
898 //Also, this will allow writing to the new window and
899 //reading from the old one
| 903 NNPC = target;
|
900 Cwp = (Cwp - 1 + NWindows) % NWindows;
901 Cansave = Cansave + 1;
902 Canrestore = Canrestore - 1;
| 904 Cwp = (Cwp - 1 + NWindows) % NWindows;
905 Cansave = Cansave + 1;
906 Canrestore = Canrestore - 1;
|
903 //This is here to make sure the CWP is written
904 //no matter what. This ensures that the results
905 //are written in the new window as well.
906 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
| |
907 }
908 }
909 }});
910 0x3A: decode CC
911 {
912 0x0: Trap::tcci({{
913 if(passesCondition(Ccr<3:0>, COND2))
914 {
915#if FULL_SYSTEM
916 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
917 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
918 fault = new TrapInstruction(lTrapNum);
919#else
920 DPRINTF(Sparc, "The syscall number is %d\n", R1);
921 xc->syscall(R1);
922#endif
923 }
| 907 }
908 }
909 }});
910 0x3A: decode CC
911 {
912 0x0: Trap::tcci({{
913 if(passesCondition(Ccr<3:0>, COND2))
914 {
915#if FULL_SYSTEM
916 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
917 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
918 fault = new TrapInstruction(lTrapNum);
919#else
920 DPRINTF(Sparc, "The syscall number is %d\n", R1);
921 xc->syscall(R1);
922#endif
923 }
|
924 }});
| 924 }}, IsSerializeAfter, IsNonSpeculative);
|
925 0x2: Trap::tccx({{
926 if(passesCondition(Ccr<7:4>, COND2))
927 {
928#if FULL_SYSTEM
929 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
930 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
931 fault = new TrapInstruction(lTrapNum);
932#else
933 DPRINTF(Sparc, "The syscall number is %d\n", R1);
934 xc->syscall(R1);
935#endif
936 }
| 925 0x2: Trap::tccx({{
926 if(passesCondition(Ccr<7:4>, COND2))
927 {
928#if FULL_SYSTEM
929 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
930 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
931 fault = new TrapInstruction(lTrapNum);
932#else
933 DPRINTF(Sparc, "The syscall number is %d\n", R1);
934 xc->syscall(R1);
935#endif
936 }
|
937 }});
| 937 }}, IsSerializeAfter, IsNonSpeculative);
|
938 }
939 0x3B: Nop::flush({{/*Instruction memory flush*/}});
940 0x3C: save({{
| 938 }
939 0x3B: Nop::flush({{/*Instruction memory flush*/}});
940 0x3C: save({{
|
941 //CWP should be set directly so that it always happens
942 //Also, this will allow writing to the new window and
943 //reading from the old one
| |
944 if(Cansave == 0)
945 {
946 if(Otherwin)
| 941 if(Cansave == 0)
942 {
943 if(Otherwin)
|
947 fault = new SpillNOther(4*Wstate<5:3>);
| 944 fault = new SpillNOther(Wstate<5:3>);
|
948 else
| 945 else
|
949 fault = new SpillNNormal(4*Wstate<2:0>);
950 //Cwp = (Cwp + 2) % NWindows;
| 946 fault = new SpillNNormal(Wstate<2:0>);
|
951 }
952 else if(Cleanwin - Canrestore == 0)
953 {
| 947 }
948 else if(Cleanwin - Canrestore == 0)
949 {
|
954 //Cwp = (Cwp + 1) % NWindows;
| |
955 fault = new CleanWindow;
956 }
957 else
958 {
959 Cwp = (Cwp + 1) % NWindows;
| 950 fault = new CleanWindow;
951 }
952 else
953 {
954 Cwp = (Cwp + 1) % NWindows;
|
960 Rd = Rs1 + Rs2_or_imm13;
| 955 Rd_next = Rs1 + Rs2_or_imm13;
|
961 Cansave = Cansave - 1;
962 Canrestore = Canrestore + 1;
| 956 Cansave = Cansave - 1;
957 Canrestore = Canrestore + 1;
|
963 //This is here to make sure the CWP is written
964 //no matter what. This ensures that the results
965 //are written in the new window as well.
966 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
| |
967 }
968 }});
969 0x3D: restore({{
970 if(Canrestore == 0)
971 {
972 if(Otherwin)
| 958 }
959 }});
960 0x3D: restore({{
961 if(Canrestore == 0)
962 {
963 if(Otherwin)
|
973 fault = new FillNOther(4*Wstate<5:3>);
| 964 fault = new FillNOther(Wstate<5:3>);
|
974 else
| 965 else
|
975 fault = new FillNNormal(4*Wstate<2:0>);
| 966 fault = new FillNNormal(Wstate<2:0>);
|
976 }
977 else
978 {
| 967 }
968 else
969 {
|
979 //CWP should be set directly so that it always happens
980 //Also, this will allow writing to the new window and
981 //reading from the old one
| |
982 Cwp = (Cwp - 1 + NWindows) % NWindows;
| 970 Cwp = (Cwp - 1 + NWindows) % NWindows;
|
983 Rd = Rs1 + Rs2_or_imm13;
| 971 Rd_prev = Rs1 + Rs2_or_imm13;
|
984 Cansave = Cansave + 1;
985 Canrestore = Canrestore - 1;
| 972 Cansave = Cansave + 1;
973 Canrestore = Canrestore - 1;
|
986 //This is here to make sure the CWP is written
987 //no matter what. This ensures that the results
988 //are written in the new window as well.
989 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
| |
990 }
991 }});
992 0x3E: decode FCN {
993 0x0: Priv::done({{
994 if(Tl == 0)
995 return new IllegalInstruction;
996
997 Cwp = Tstate<4:0>;
998 Pstate = Tstate<20:8>;
999 Asi = Tstate<31:24>;
1000 Ccr = Tstate<39:32>;
1001 Gl = Tstate<42:40>;
1002 Hpstate = Htstate;
1003 NPC = Tnpc;
1004 NNPC = Tnpc + 4;
1005 Tl = Tl - 1;
1006 }});
1007 0x1: Priv::retry({{
1008 if(Tl == 0)
1009 return new IllegalInstruction;
1010 Cwp = Tstate<4:0>;
1011 Pstate = Tstate<20:8>;
1012 Asi = Tstate<31:24>;
1013 Ccr = Tstate<39:32>;
1014 Gl = Tstate<42:40>;
1015 Hpstate = Htstate;
1016 NPC = Tpc;
1017 NNPC = Tnpc;
1018 Tl = Tl - 1;
1019 }});
1020 }
1021 }
1022 }
1023 0x3: decode OP3 {
1024 format Load {
1025 0x00: lduw({{Rd = Mem.uw;}});
1026 0x01: ldub({{Rd = Mem.ub;}});
1027 0x02: lduh({{Rd = Mem.uhw;}});
| 974 }
975 }});
976 0x3E: decode FCN {
977 0x0: Priv::done({{
978 if(Tl == 0)
979 return new IllegalInstruction;
980
981 Cwp = Tstate<4:0>;
982 Pstate = Tstate<20:8>;
983 Asi = Tstate<31:24>;
984 Ccr = Tstate<39:32>;
985 Gl = Tstate<42:40>;
986 Hpstate = Htstate;
987 NPC = Tnpc;
988 NNPC = Tnpc + 4;
989 Tl = Tl - 1;
990 }});
991 0x1: Priv::retry({{
992 if(Tl == 0)
993 return new IllegalInstruction;
994 Cwp = Tstate<4:0>;
995 Pstate = Tstate<20:8>;
996 Asi = Tstate<31:24>;
997 Ccr = Tstate<39:32>;
998 Gl = Tstate<42:40>;
999 Hpstate = Htstate;
1000 NPC = Tpc;
1001 NNPC = Tnpc;
1002 Tl = Tl - 1;
1003 }});
1004 }
1005 }
1006 }
1007 0x3: decode OP3 {
1008 format Load {
1009 0x00: lduw({{Rd = Mem.uw;}});
1010 0x01: ldub({{Rd = Mem.ub;}});
1011 0x02: lduh({{Rd = Mem.uhw;}});
|
1028 0x03: ldtw({{
| 1012 0x03: ldd({{
|
1029 uint64_t val = Mem.udw;
1030 RdLow = val<31:0>;
1031 RdHigh = val<63:32>;
1032 }});
1033 }
1034 format Store {
1035 0x04: stw({{Mem.uw = Rd.sw;}});
1036 0x05: stb({{Mem.ub = Rd.sb;}});
1037 0x06: sth({{Mem.uhw = Rd.shw;}});
| 1013 uint64_t val = Mem.udw;
1014 RdLow = val<31:0>;
1015 RdHigh = val<63:32>;
1016 }});
1017 }
1018 format Store {
1019 0x04: stw({{Mem.uw = Rd.sw;}});
1020 0x05: stb({{Mem.ub = Rd.sb;}});
1021 0x06: sth({{Mem.uhw = Rd.shw;}});
|
1038 0x07: sttw({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
| 1022 0x07: std({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
|
1039 }
1040 format Load {
1041 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
1042 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
1043 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
1044 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
1045 }
1046 0x0D: LoadStore::ldstub(
| 1023 }
1024 format Load {
1025 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
1026 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
1027 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
1028 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
1029 }
1030 0x0D: LoadStore::ldstub(
|
1047 {{uReg0 = Mem.ub;}},
1048 {{Rd.ub = uReg0;
1049 Mem.ub = 0xFF;}});
| 1031 {{Rd = Mem.ub;}},
1032 {{Mem.ub = 0xFF;}});
|
1050 0x0E: Store::stx({{Mem.udw = Rd}});
1051 0x0F: LoadStore::swap(
| 1033 0x0E: Store::stx({{Mem.udw = Rd}});
1034 0x0F: LoadStore::swap(
|
1052 {{ uReg0 = Mem.uw}},
1053 {{ Mem.uw = Rd.uw;
1054 Rd.uw = uReg0;}});
| 1035 {{uReg0 = Rd.uw;
1036 Rd.uw = Mem.uw;}},
1037 {{Mem.uw = uReg0;}});
|
1055 format LoadAlt {
1056 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
1057 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
1058 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
| 1038 format LoadAlt {
1039 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
1040 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
1041 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
|
1059 0x13: decode EXT_ASI {
1060 //ASI_LDTD_AIUP
1061 0x22: TwinLoad::ldtx_aiup(
1062 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1063 //ASI_LDTD_AIUS
1064 0x23: TwinLoad::ldtx_aius(
1065 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1066 //ASI_QUAD_LDD
1067 0x24: TwinLoad::ldtx_quad_ldd(
1068 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1069 //ASI_LDTX_REAL
1070 0x26: TwinLoad::ldtx_real(
1071 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1072 //ASI_LDTX_N
1073 0x27: TwinLoad::ldtx_n(
1074 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1075 //ASI_LDTX_L
1076 0x2C: TwinLoad::ldtx_l(
1077 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1078 //ASI_LDTX_REAL_L
1079 0x2E: TwinLoad::ldtx_real_l(
1080 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1081 //ASI_LDTX_N_L
1082 0x2F: TwinLoad::ldtx_n_l(
1083 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1084 //ASI_LDTX_P
1085 0xE2: TwinLoad::ldtx_p(
1086 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1087 //ASI_LDTX_S
1088 0xE3: TwinLoad::ldtx_s(
1089 {{RdTwin.udw = Mem.udw;}}, {{EXT_ASI}});
1090 default: ldtwa({{
1091 uint64_t val = Mem.udw;
1092 RdLow = val<31:0>;
1093 RdHigh = val<63:32>;
1094 }}, {{EXT_ASI}});
1095 }
| 1042 0x13: ldda({{
1043 uint64_t val = Mem.udw;
1044 RdLow = val<31:0>;
1045 RdHigh = val<63:32>;
1046 }}, {{EXT_ASI}});
|
1096 }
1097 format StoreAlt {
1098 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
1099 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
1100 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
| 1047 }
1048 format StoreAlt {
1049 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
1050 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
1051 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
|
1101 0x17: sttwa({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}});
| 1052 0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}});
|
1102 }
1103 format LoadAlt {
1104 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
1105 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}});
1106 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}});
1107 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}});
1108 }
1109 0x1D: LoadStoreAlt::ldstuba(
| 1053 }
1054 format LoadAlt {
1055 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
1056 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}});
1057 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}});
1058 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}});
1059 }
1060 0x1D: LoadStoreAlt::ldstuba(
|
1110 {{uReg0 = Mem.ub;}},
1111 {{Rd.ub = uReg0;
1112 Mem.ub = 0xFF;}}, {{EXT_ASI}});
| 1061 {{Rd = Mem.ub;}},
1062 {{Mem.ub = 0xFF}}, {{EXT_ASI}});
|
1113 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}});
1114 0x1F: LoadStoreAlt::swapa(
| 1063 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}});
1064 0x1F: LoadStoreAlt::swapa(
|
1115 {{ uReg0 = Mem.uw}},
1116 {{ Mem.uw = Rd.uw;
1117 Rd.uw = uReg0;}}, {{EXT_ASI}});
| 1065 {{uReg0 = Rd.uw;
1066 Rd.uw = Mem.uw;}},
1067 {{Mem.uw = uReg0;}}, {{EXT_ASI}});
|
1118 format Trap {
| 1068 format Trap {
|
1119 0x20: Load::ldf({{Frds.uw = Mem.uw;}});
| 1069 0x20: Load::ldf({{Frd.uw = Mem.uw;}});
|
1120 0x21: decode X {
1121 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}});
1122 0x1: Load::ldxfsr({{Fsr = Mem.udw;}});
1123 }
1124 0x22: ldqf({{fault = new FpDisabled;}});
1125 0x23: Load::lddf({{Frd.udw = Mem.udw;}});
| 1070 0x21: decode X {
1071 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}});
1072 0x1: Load::ldxfsr({{Fsr = Mem.udw;}});
1073 }
1074 0x22: ldqf({{fault = new FpDisabled;}});
1075 0x23: Load::lddf({{Frd.udw = Mem.udw;}});
|
1126 0x24: Store::stf({{Mem.uw = Frds.uw;}});
| 1076 0x24: Store::stf({{Mem.uw = Frd.uw;}});
|
1127 0x25: decode X {
1128 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}});
1129 0x1: Store::stxfsr({{Mem.udw = Fsr;}});
1130 }
1131 0x26: stqf({{fault = new FpDisabled;}});
1132 0x27: Store::stdf({{Mem.udw = Frd.udw;}});
1133 0x2D: Nop::prefetch({{ }});
| 1077 0x25: decode X {
1078 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}});
1079 0x1: Store::stxfsr({{Mem.udw = Fsr;}});
1080 }
1081 0x26: stqf({{fault = new FpDisabled;}});
1082 0x27: Store::stdf({{Mem.udw = Frd.udw;}});
1083 0x2D: Nop::prefetch({{ }});
|
1134 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}}, {{EXT_ASI}});
| 1084 0x30: LoadAlt::ldfa({{Frd.uw = Mem.uw;}}, {{EXT_ASI}});
|
1135 0x32: ldqfa({{fault = new FpDisabled;}});
1136 format LoadAlt {
1137 0x33: decode EXT_ASI {
1138 //ASI_NUCLEUS
1139 0x04: FailUnimpl::lddfa_n();
1140 //ASI_NUCLEUS_LITTLE
1141 0x0C: FailUnimpl::lddfa_nl();
1142 //ASI_AS_IF_USER_PRIMARY
1143 0x10: FailUnimpl::lddfa_aiup();
1144 //ASI_AS_IF_USER_PRIMARY_LITTLE
1145 0x18: FailUnimpl::lddfa_aiupl();
1146 //ASI_AS_IF_USER_SECONDARY
1147 0x11: FailUnimpl::lddfa_aius();
1148 //ASI_AS_IF_USER_SECONDARY_LITTLE
1149 0x19: FailUnimpl::lddfa_aiusl();
1150 //ASI_REAL
1151 0x14: FailUnimpl::lddfa_real();
1152 //ASI_REAL_LITTLE
1153 0x1C: FailUnimpl::lddfa_real_l();
1154 //ASI_REAL_IO
1155 0x15: FailUnimpl::lddfa_real_io();
1156 //ASI_REAL_IO_LITTLE
1157 0x1D: FailUnimpl::lddfa_real_io_l();
1158 //ASI_PRIMARY
1159 0x80: FailUnimpl::lddfa_p();
1160 //ASI_PRIMARY_LITTLE
1161 0x88: FailUnimpl::lddfa_pl();
1162 //ASI_SECONDARY
1163 0x81: FailUnimpl::lddfa_s();
1164 //ASI_SECONDARY_LITTLE
1165 0x89: FailUnimpl::lddfa_sl();
1166 //ASI_PRIMARY_NO_FAULT
1167 0x82: FailUnimpl::lddfa_pnf();
1168 //ASI_PRIMARY_NO_FAULT_LITTLE
1169 0x8A: FailUnimpl::lddfa_pnfl();
1170 //ASI_SECONDARY_NO_FAULT
1171 0x83: FailUnimpl::lddfa_snf();
1172 //ASI_SECONDARY_NO_FAULT_LITTLE
1173 0x8B: FailUnimpl::lddfa_snfl();
1174
1175 format BlockLoad {
1176 // LDBLOCKF
1177 //ASI_BLOCK_AS_IF_USER_PRIMARY
1178 0x16: FailUnimpl::ldblockf_aiup();
1179 //ASI_BLOCK_AS_IF_USER_SECONDARY
1180 0x17: FailUnimpl::ldblockf_aius();
1181 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1182 0x1E: FailUnimpl::ldblockf_aiupl();
1183 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1184 0x1F: FailUnimpl::ldblockf_aiusl();
1185 //ASI_BLOCK_PRIMARY
1186 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}});
1187 //ASI_BLOCK_SECONDARY
1188 0xF1: FailUnimpl::ldblockf_s();
1189 //ASI_BLOCK_PRIMARY_LITTLE
1190 0xF8: FailUnimpl::ldblockf_pl();
1191 //ASI_BLOCK_SECONDARY_LITTLE
1192 0xF9: FailUnimpl::ldblockf_sl();
1193 }
1194
1195 //LDSHORTF
1196 //ASI_FL8_PRIMARY
1197 0xD0: FailUnimpl::ldshortf_8p();
1198 //ASI_FL8_SECONDARY
1199 0xD1: FailUnimpl::ldshortf_8s();
1200 //ASI_FL8_PRIMARY_LITTLE
1201 0xD8: FailUnimpl::ldshortf_8pl();
1202 //ASI_FL8_SECONDARY_LITTLE
1203 0xD9: FailUnimpl::ldshortf_8sl();
1204 //ASI_FL16_PRIMARY
1205 0xD2: FailUnimpl::ldshortf_16p();
1206 //ASI_FL16_SECONDARY
1207 0xD3: FailUnimpl::ldshortf_16s();
1208 //ASI_FL16_PRIMARY_LITTLE
1209 0xDA: FailUnimpl::ldshortf_16pl();
1210 //ASI_FL16_SECONDARY_LITTLE
1211 0xDB: FailUnimpl::ldshortf_16sl();
1212 //Not an ASI which is legal with lddfa
1213 default: Trap::lddfa_bad_asi(
1214 {{fault = new DataAccessException;}});
1215 }
1216 }
| 1085 0x32: ldqfa({{fault = new FpDisabled;}});
1086 format LoadAlt {
1087 0x33: decode EXT_ASI {
1088 //ASI_NUCLEUS
1089 0x04: FailUnimpl::lddfa_n();
1090 //ASI_NUCLEUS_LITTLE
1091 0x0C: FailUnimpl::lddfa_nl();
1092 //ASI_AS_IF_USER_PRIMARY
1093 0x10: FailUnimpl::lddfa_aiup();
1094 //ASI_AS_IF_USER_PRIMARY_LITTLE
1095 0x18: FailUnimpl::lddfa_aiupl();
1096 //ASI_AS_IF_USER_SECONDARY
1097 0x11: FailUnimpl::lddfa_aius();
1098 //ASI_AS_IF_USER_SECONDARY_LITTLE
1099 0x19: FailUnimpl::lddfa_aiusl();
1100 //ASI_REAL
1101 0x14: FailUnimpl::lddfa_real();
1102 //ASI_REAL_LITTLE
1103 0x1C: FailUnimpl::lddfa_real_l();
1104 //ASI_REAL_IO
1105 0x15: FailUnimpl::lddfa_real_io();
1106 //ASI_REAL_IO_LITTLE
1107 0x1D: FailUnimpl::lddfa_real_io_l();
1108 //ASI_PRIMARY
1109 0x80: FailUnimpl::lddfa_p();
1110 //ASI_PRIMARY_LITTLE
1111 0x88: FailUnimpl::lddfa_pl();
1112 //ASI_SECONDARY
1113 0x81: FailUnimpl::lddfa_s();
1114 //ASI_SECONDARY_LITTLE
1115 0x89: FailUnimpl::lddfa_sl();
1116 //ASI_PRIMARY_NO_FAULT
1117 0x82: FailUnimpl::lddfa_pnf();
1118 //ASI_PRIMARY_NO_FAULT_LITTLE
1119 0x8A: FailUnimpl::lddfa_pnfl();
1120 //ASI_SECONDARY_NO_FAULT
1121 0x83: FailUnimpl::lddfa_snf();
1122 //ASI_SECONDARY_NO_FAULT_LITTLE
1123 0x8B: FailUnimpl::lddfa_snfl();
1124
1125 format BlockLoad {
1126 // LDBLOCKF
1127 //ASI_BLOCK_AS_IF_USER_PRIMARY
1128 0x16: FailUnimpl::ldblockf_aiup();
1129 //ASI_BLOCK_AS_IF_USER_SECONDARY
1130 0x17: FailUnimpl::ldblockf_aius();
1131 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1132 0x1E: FailUnimpl::ldblockf_aiupl();
1133 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1134 0x1F: FailUnimpl::ldblockf_aiusl();
1135 //ASI_BLOCK_PRIMARY
1136 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}});
1137 //ASI_BLOCK_SECONDARY
1138 0xF1: FailUnimpl::ldblockf_s();
1139 //ASI_BLOCK_PRIMARY_LITTLE
1140 0xF8: FailUnimpl::ldblockf_pl();
1141 //ASI_BLOCK_SECONDARY_LITTLE
1142 0xF9: FailUnimpl::ldblockf_sl();
1143 }
1144
1145 //LDSHORTF
1146 //ASI_FL8_PRIMARY
1147 0xD0: FailUnimpl::ldshortf_8p();
1148 //ASI_FL8_SECONDARY
1149 0xD1: FailUnimpl::ldshortf_8s();
1150 //ASI_FL8_PRIMARY_LITTLE
1151 0xD8: FailUnimpl::ldshortf_8pl();
1152 //ASI_FL8_SECONDARY_LITTLE
1153 0xD9: FailUnimpl::ldshortf_8sl();
1154 //ASI_FL16_PRIMARY
1155 0xD2: FailUnimpl::ldshortf_16p();
1156 //ASI_FL16_SECONDARY
1157 0xD3: FailUnimpl::ldshortf_16s();
1158 //ASI_FL16_PRIMARY_LITTLE
1159 0xDA: FailUnimpl::ldshortf_16pl();
1160 //ASI_FL16_SECONDARY_LITTLE
1161 0xDB: FailUnimpl::ldshortf_16sl();
1162 //Not an ASI which is legal with lddfa
1163 default: Trap::lddfa_bad_asi(
1164 {{fault = new DataAccessException;}});
1165 }
1166 }
|
1217 0x34: Store::stfa({{Mem.uw = Frds.uw;}});
| 1167 0x34: Store::stfa({{Mem.uw = Frd.uw;}});
|
1218 0x36: stqfa({{fault = new FpDisabled;}});
1219 format StoreAlt {
1220 0x37: decode EXT_ASI {
1221 //ASI_NUCLEUS
1222 0x04: FailUnimpl::stdfa_n();
1223 //ASI_NUCLEUS_LITTLE
1224 0x0C: FailUnimpl::stdfa_nl();
1225 //ASI_AS_IF_USER_PRIMARY
1226 0x10: FailUnimpl::stdfa_aiup();
1227 //ASI_AS_IF_USER_PRIMARY_LITTLE
1228 0x18: FailUnimpl::stdfa_aiupl();
1229 //ASI_AS_IF_USER_SECONDARY
1230 0x11: FailUnimpl::stdfa_aius();
1231 //ASI_AS_IF_USER_SECONDARY_LITTLE
1232 0x19: FailUnimpl::stdfa_aiusl();
1233 //ASI_REAL
1234 0x14: FailUnimpl::stdfa_real();
1235 //ASI_REAL_LITTLE
1236 0x1C: FailUnimpl::stdfa_real_l();
1237 //ASI_REAL_IO
1238 0x15: FailUnimpl::stdfa_real_io();
1239 //ASI_REAL_IO_LITTLE
1240 0x1D: FailUnimpl::stdfa_real_io_l();
1241 //ASI_PRIMARY
1242 0x80: FailUnimpl::stdfa_p();
1243 //ASI_PRIMARY_LITTLE
1244 0x88: FailUnimpl::stdfa_pl();
1245 //ASI_SECONDARY
1246 0x81: FailUnimpl::stdfa_s();
1247 //ASI_SECONDARY_LITTLE
1248 0x89: FailUnimpl::stdfa_sl();
1249 //ASI_PRIMARY_NO_FAULT
1250 0x82: FailUnimpl::stdfa_pnf();
1251 //ASI_PRIMARY_NO_FAULT_LITTLE
1252 0x8A: FailUnimpl::stdfa_pnfl();
1253 //ASI_SECONDARY_NO_FAULT
1254 0x83: FailUnimpl::stdfa_snf();
1255 //ASI_SECONDARY_NO_FAULT_LITTLE
1256 0x8B: FailUnimpl::stdfa_snfl();
1257
1258 format BlockStore {
1259 // STBLOCKF
1260 //ASI_BLOCK_AS_IF_USER_PRIMARY
1261 0x16: FailUnimpl::stblockf_aiup();
1262 //ASI_BLOCK_AS_IF_USER_SECONDARY
1263 0x17: FailUnimpl::stblockf_aius();
1264 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1265 0x1E: FailUnimpl::stblockf_aiupl();
1266 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1267 0x1F: FailUnimpl::stblockf_aiusl();
1268 //ASI_BLOCK_PRIMARY
1269 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}});
1270 //ASI_BLOCK_SECONDARY
1271 0xF1: FailUnimpl::stblockf_s();
1272 //ASI_BLOCK_PRIMARY_LITTLE
1273 0xF8: FailUnimpl::stblockf_pl();
1274 //ASI_BLOCK_SECONDARY_LITTLE
1275 0xF9: FailUnimpl::stblockf_sl();
1276 }
1277
1278 //STSHORTF
1279 //ASI_FL8_PRIMARY
1280 0xD0: FailUnimpl::stshortf_8p();
1281 //ASI_FL8_SECONDARY
1282 0xD1: FailUnimpl::stshortf_8s();
1283 //ASI_FL8_PRIMARY_LITTLE
1284 0xD8: FailUnimpl::stshortf_8pl();
1285 //ASI_FL8_SECONDARY_LITTLE
1286 0xD9: FailUnimpl::stshortf_8sl();
1287 //ASI_FL16_PRIMARY
1288 0xD2: FailUnimpl::stshortf_16p();
1289 //ASI_FL16_SECONDARY
1290 0xD3: FailUnimpl::stshortf_16s();
1291 //ASI_FL16_PRIMARY_LITTLE
1292 0xDA: FailUnimpl::stshortf_16pl();
1293 //ASI_FL16_SECONDARY_LITTLE
1294 0xDB: FailUnimpl::stshortf_16sl();
1295 //Not an ASI which is legal with lddfa
1296 default: Trap::stdfa_bad_asi(
1297 {{fault = new DataAccessException;}});
1298 }
1299 }
1300 0x3C: Cas::casa(
1301 {{uReg0 = Mem.uw;}},
1302 {{if(Rs2.uw == uReg0)
1303 Mem.uw = Rd.uw;
1304 else
1305 storeCond = false;
1306 Rd.uw = uReg0;}}, {{EXT_ASI}});
1307 0x3D: Nop::prefetcha({{ }});
1308 0x3E: Cas::casxa(
1309 {{uReg0 = Mem.udw;}},
1310 {{if(Rs2 == uReg0)
1311 Mem.udw = Rd;
1312 else
1313 storeCond = false;
1314 Rd = uReg0;}}, {{EXT_ASI}});
1315 }
1316 }
1317}
| 1168 0x36: stqfa({{fault = new FpDisabled;}});
1169 format StoreAlt {
1170 0x37: decode EXT_ASI {
1171 //ASI_NUCLEUS
1172 0x04: FailUnimpl::stdfa_n();
1173 //ASI_NUCLEUS_LITTLE
1174 0x0C: FailUnimpl::stdfa_nl();
1175 //ASI_AS_IF_USER_PRIMARY
1176 0x10: FailUnimpl::stdfa_aiup();
1177 //ASI_AS_IF_USER_PRIMARY_LITTLE
1178 0x18: FailUnimpl::stdfa_aiupl();
1179 //ASI_AS_IF_USER_SECONDARY
1180 0x11: FailUnimpl::stdfa_aius();
1181 //ASI_AS_IF_USER_SECONDARY_LITTLE
1182 0x19: FailUnimpl::stdfa_aiusl();
1183 //ASI_REAL
1184 0x14: FailUnimpl::stdfa_real();
1185 //ASI_REAL_LITTLE
1186 0x1C: FailUnimpl::stdfa_real_l();
1187 //ASI_REAL_IO
1188 0x15: FailUnimpl::stdfa_real_io();
1189 //ASI_REAL_IO_LITTLE
1190 0x1D: FailUnimpl::stdfa_real_io_l();
1191 //ASI_PRIMARY
1192 0x80: FailUnimpl::stdfa_p();
1193 //ASI_PRIMARY_LITTLE
1194 0x88: FailUnimpl::stdfa_pl();
1195 //ASI_SECONDARY
1196 0x81: FailUnimpl::stdfa_s();
1197 //ASI_SECONDARY_LITTLE
1198 0x89: FailUnimpl::stdfa_sl();
1199 //ASI_PRIMARY_NO_FAULT
1200 0x82: FailUnimpl::stdfa_pnf();
1201 //ASI_PRIMARY_NO_FAULT_LITTLE
1202 0x8A: FailUnimpl::stdfa_pnfl();
1203 //ASI_SECONDARY_NO_FAULT
1204 0x83: FailUnimpl::stdfa_snf();
1205 //ASI_SECONDARY_NO_FAULT_LITTLE
1206 0x8B: FailUnimpl::stdfa_snfl();
1207
1208 format BlockStore {
1209 // STBLOCKF
1210 //ASI_BLOCK_AS_IF_USER_PRIMARY
1211 0x16: FailUnimpl::stblockf_aiup();
1212 //ASI_BLOCK_AS_IF_USER_SECONDARY
1213 0x17: FailUnimpl::stblockf_aius();
1214 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1215 0x1E: FailUnimpl::stblockf_aiupl();
1216 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1217 0x1F: FailUnimpl::stblockf_aiusl();
1218 //ASI_BLOCK_PRIMARY
1219 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}});
1220 //ASI_BLOCK_SECONDARY
1221 0xF1: FailUnimpl::stblockf_s();
1222 //ASI_BLOCK_PRIMARY_LITTLE
1223 0xF8: FailUnimpl::stblockf_pl();
1224 //ASI_BLOCK_SECONDARY_LITTLE
1225 0xF9: FailUnimpl::stblockf_sl();
1226 }
1227
1228 //STSHORTF
1229 //ASI_FL8_PRIMARY
1230 0xD0: FailUnimpl::stshortf_8p();
1231 //ASI_FL8_SECONDARY
1232 0xD1: FailUnimpl::stshortf_8s();
1233 //ASI_FL8_PRIMARY_LITTLE
1234 0xD8: FailUnimpl::stshortf_8pl();
1235 //ASI_FL8_SECONDARY_LITTLE
1236 0xD9: FailUnimpl::stshortf_8sl();
1237 //ASI_FL16_PRIMARY
1238 0xD2: FailUnimpl::stshortf_16p();
1239 //ASI_FL16_SECONDARY
1240 0xD3: FailUnimpl::stshortf_16s();
1241 //ASI_FL16_PRIMARY_LITTLE
1242 0xDA: FailUnimpl::stshortf_16pl();
1243 //ASI_FL16_SECONDARY_LITTLE
1244 0xDB: FailUnimpl::stshortf_16sl();
1245 //Not an ASI which is legal with lddfa
1246 default: Trap::stdfa_bad_asi(
1247 {{fault = new DataAccessException;}});
1248 }
1249 }
1250 0x3C: Cas::casa(
1251 {{uReg0 = Mem.uw;}},
1252 {{if(Rs2.uw == uReg0)
1253 Mem.uw = Rd.uw;
1254 else
1255 storeCond = false;
1256 Rd.uw = uReg0;}}, {{EXT_ASI}});
1257 0x3D: Nop::prefetcha({{ }});
1258 0x3E: Cas::casxa(
1259 {{uReg0 = Mem.udw;}},
1260 {{if(Rs2 == uReg0)
1261 Mem.udw = Rd;
1262 else
1263 storeCond = false;
1264 Rd = uReg0;}}, {{EXT_ASI}});
1265 }
1266 }
1267}
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