1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OP default Unknown::unknown()
37{
38 0x0: decode OP2
39 {
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 //bpcc
45 0x1: decode COND2
46 {
47 //Branch Always
48 0x8: decode A
49 {
50 0x0: bpa(19, {{
51 NNPC = xc->readPC() + disp;
52 }});
53 0x1: bpa(19, {{
54 NPC = xc->readPC() + disp;
55 NNPC = NPC + 4;
56 }}, ',a');
57 }
58 //Branch Never
59 0x0: decode A
60 {
61 0x0: bpn(19, {{
62 NNPC = NNPC;//Don't do anything
63 }});
64 0x1: bpn(19, {{
65 NPC = xc->readNextPC() + 4;
66 NNPC = NPC + 4;
67 }}, ',a');
68 }
69 default: decode BPCC
70 {
71 0x0: bpcci(19, {{
72 if(passesCondition(Ccr<3:0>, COND2))
73 NNPC = xc->readPC() + disp;
74 else
75 handle_annul
76 }});
77 0x2: bpccx(19, {{
78 if(passesCondition(Ccr<7:4>, COND2))
79 NNPC = xc->readPC() + disp;
80 else
81 handle_annul
82 }});
83 }
84 }
85 //bicc
86 0x2: decode COND2
87 {
88 //Branch Always
89 0x8: decode A
90 {
91 0x0: ba(22, {{
92 NNPC = xc->readPC() + disp;
93 }});
94 0x1: ba(22, {{
95 NPC = xc->readPC() + disp;
96 NNPC = NPC + 4;
97 }}, ',a');
98 }
99 //Branch Never
100 0x0: decode A
101 {
102 0x0: bn(22, {{
103 NNPC = NNPC;//Don't do anything
104 }});
105 0x1: bn(22, {{
106 NPC = xc->readNextPC() + 4;
107 NNPC = NPC + 4;
108 }}, ',a');
109 }
110 default: bicc(22, {{
111 if(passesCondition(Ccr<3:0>, COND2))
112 NNPC = xc->readPC() + disp;
113 else
114 handle_annul
115 }});
116 }
117 }
118 0x3: decode RCOND2
119 {
120 format BranchSplit
121 {
122 0x1: bpreq({{
123 if(Rs1.sdw == 0)
124 NNPC = xc->readPC() + disp;
125 else
126 handle_annul
127 }});
128 0x2: bprle({{
129 if(Rs1.sdw <= 0)
130 NNPC = xc->readPC() + disp;
131 else
132 handle_annul
133 }});
134 0x3: bprl({{
135 if(Rs1.sdw < 0)
136 NNPC = xc->readPC() + disp;
137 else
138 handle_annul
139 }});
140 0x5: bprne({{
141 if(Rs1.sdw != 0)
142 NNPC = xc->readPC() + disp;
143 else
144 handle_annul
145 }});
146 0x6: bprg({{
147 if(Rs1.sdw > 0)
148 NNPC = xc->readPC() + disp;
149 else
150 handle_annul
151 }});
152 0x7: bprge({{
153 if(Rs1.sdw >= 0)
154 NNPC = xc->readPC() + disp;
155 else
156 handle_annul
157 }});
158 }
159 }
160 //SETHI (or NOP if rd == 0 and imm == 0)
161 0x4: SetHi::sethi({{Rd.udw = imm;}});
162 0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
163 0x6: Trap::fbfcc({{fault = new FpDisabled;}});
164 }
165 0x1: BranchN::call(30, {{
166 R15 = xc->readPC();
167 NNPC = R15 + disp;
168 }});
169 0x2: decode OP3 {
170 format IntOp {
171 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
172 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
173 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
174 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
175 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
176 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}});
177 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}});
178 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
179 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
180 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
181 0x0A: umul({{
182 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
183 Y = Rd<63:32>;
184 }});
185 0x0B: smul({{
186 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
187 Y = Rd.sdw;
188 }});
189 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
190 0x0D: udivx({{
191 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
192 else Rd.udw = Rs1.udw / Rs2_or_imm13;
193 }});
194 0x0E: udiv({{
195 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
196 else
197 {
198 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
199 if(Rd.udw >> 32 != 0)
200 Rd.udw = 0xFFFFFFFF;
201 }
202 }});
203 0x0F: sdiv({{
204 if(Rs2_or_imm13.sdw == 0)
205 fault = new DivisionByZero;
206 else
207 {
208 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
209 if(Rd.udw<63:31> != 0)
210 Rd.udw = 0x7FFFFFFF;
211 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
212 Rd.udw = 0xFFFFFFFF80000000ULL;
213 }
214 }});
215 }
216 format IntOpCc {
217 0x10: addcc({{
218 int64_t resTemp, val2 = Rs2_or_imm13;
219 Rd = resTemp = Rs1 + val2;}},
220 {{(Rs1<31:0> + val2<31:0>)<32:>}},
221 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
222 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
223 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
224 );
225 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
226 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
227 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
228 0x14: subcc({{
229 int64_t val2 = Rs2_or_imm13;
230 Rd = Rs1 - val2;}},
231 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
232 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
233 {{(~(Rs1<63:1> + (~val2)<63:1> +
234 (Rs1 | ~val2)<0:>))<63:>}},
235 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
236 );
237 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
238 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
239 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
240 0x18: addccc({{
241 int64_t resTemp, val2 = Rs2_or_imm13;
242 int64_t carryin = Ccr<0:0>;
243 Rd = resTemp = Rs1 + val2 + carryin;}},
244 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
245 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
246 {{(Rs1<63:1> + val2<63:1> +
247 ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
248 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
249 );
250 0x1A: umulcc({{
251 uint64_t resTemp;
252 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
253 Y = resTemp<63:32>;}},
254 {{0}},{{0}},{{0}},{{0}});
255 0x1B: smulcc({{
256 int64_t resTemp;
257 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>;
258 Y = resTemp<63:32>;}},
259 {{0}},{{0}},{{0}},{{0}});
260 0x1C: subccc({{
261 int64_t resTemp, val2 = Rs2_or_imm13;
262 int64_t carryin = Ccr<0:0>;
263 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
264 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
265 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
266 {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
267 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
268 );
269 0x1D: udivxcc({{
270 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
271 else Rd = Rs1.udw / Rs2_or_imm13.udw;}}
272 ,{{0}},{{0}},{{0}},{{0}});
273 0x1E: udivcc({{
274 uint32_t resTemp, val2 = Rs2_or_imm13.udw;
275 int32_t overflow = 0;
276 if(val2 == 0) fault = new DivisionByZero;
277 else
278 {
279 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
280 overflow = (resTemp<63:32> != 0);
281 if(overflow) Rd = resTemp = 0xFFFFFFFF;
282 else Rd = resTemp;
283 } }},
284 {{0}},
285 {{overflow}},
286 {{0}},
287 {{0}}
288 );
289 0x1F: sdivcc({{
290 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
291 bool overflow = false, underflow = false;
292 if(val2 == 0) fault = new DivisionByZero;
293 else
294 {
295 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
296 overflow = (Rd<63:31> != 0);
297 underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF);
298 if(overflow) Rd = 0x7FFFFFFF;
299 else if(underflow) Rd = 0xFFFFFFFF80000000ULL;
300 } }},
301 {{0}},
302 {{overflow || underflow}},
303 {{0}},
304 {{0}}
305 );
306 0x20: taddcc({{
307 int64_t resTemp, val2 = Rs2_or_imm13;
308 Rd = resTemp = Rs1 + val2;
309 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
310 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
311 {{overflow}},
312 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
313 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
314 );
315 0x21: tsubcc({{
316 int64_t resTemp, val2 = Rs2_or_imm13;
317 Rd = resTemp = Rs1 + val2;
318 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
319 {{(Rs1<31:0> + val2<31:0>)<32:0>}},
320 {{overflow}},
321 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
322 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
323 );
324 0x22: taddcctv({{
325 int64_t val2 = Rs2_or_imm13;
326 Rd = Rs1 + val2;
327 int32_t overflow = Rs1<1:0> || val2<1:0> ||
328 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
329 if(overflow) fault = new TagOverflow;}},
330 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
331 {{overflow}},
332 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
333 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}}
334 );
335 0x23: tsubcctv({{
336 int64_t resTemp, val2 = Rs2_or_imm13;
337 Rd = resTemp = Rs1 + val2;
338 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
339 if(overflow) fault = new TagOverflow;}},
340 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
341 {{overflow}},
342 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
343 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
344 );
345 0x24: mulscc({{
346 int64_t resTemp, multiplicand = Rs2_or_imm13;
347 int32_t multiplier = Rs1<31:0>;
348 int32_t savedLSB = Rs1<0:>;
349 multiplier = multiplier<31:1> |
350 ((Ccr<3:3> ^ Ccr<1:1>) << 32);
351 if(!Y<0:>)
352 multiplicand = 0;
353 Rd = resTemp = multiplicand + multiplier;
354 Y = Y<31:1> | (savedLSB << 31);}},
355 {{((multiplicand<31:0> + multiplier<31:0>)<32:0>)}},
356 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
357 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
358 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
359 );
360 }
361 format IntOp
362 {
363 0x25: decode X {
364 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
365 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
366 }
367 0x26: decode X {
368 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
369 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
370 }
371 0x27: decode X {
372 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
373 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
374 }
375 0x28: decode RS1 {
376 0x00: NoPriv::rdy({{Rd = Y;}});
377 //1 should cause an illegal instruction exception
378 0x02: NoPriv::rdccr({{Rd = Ccr;}});
379 0x03: NoPriv::rdasi({{Rd = Asi;}});
380 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
381 0x05: NoPriv::rdpc({{
382 if(Pstate<3:>)
383 Rd = (xc->readPC())<31:0>;
384 else
385 Rd = xc->readPC();}});
386 0x06: NoPriv::rdfprs({{
387 //Wait for all fpops to finish.
388 Rd = Fprs;
389 }});
390 //7-14 should cause an illegal instruction exception
391 0x0F: decode I {
392 0x0: Nop::stbar({{/*stuff*/}});
393 0x1: Nop::membar({{/*stuff*/}});
394 }
395 0x10: Priv::rdpcr({{Rd = Pcr;}});
396 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
397 //0x12 should cause an illegal instruction exception
398 0x13: NoPriv::rdgsr({{
399 if(Fprs<2:> == 0 || Pstate<4:> == 0)
400 Rd = Gsr;
401 else
402 fault = new FpDisabled;
403 }});
404 //0x14-0x15 should cause an illegal instruction exception
405 0x16: Priv::rdsoftint({{Rd = Softint;}});
406 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
407 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}});
408 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
409 0x1A: Priv::rdstrand_sts_reg({{
410 if(Pstate<2:> && !Hpstate<2:>)
411 Rd = StrandStsReg<0:>;
412 else
413 Rd = StrandStsReg;
414 }});
415 //0x1A is supposed to be reserved, but it reads the strand
416 //status register.
417 //0x1B-0x1F should cause an illegal instruction exception
418 }
419 0x29: decode RS1 {
420 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
421 0x01: HPriv::rdhprhtstate({{
422 if(Tl == 0)
423 return new IllegalInstruction;
424 Rd = Htstate;
425 }});
426 //0x02 should cause an illegal instruction exception
427 0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
428 //0x04 should cause an illegal instruction exception
429 0x05: HPriv::rdhprhtba({{Rd = Htba;}});
430 0x06: HPriv::rdhprhver({{Rd = Hver;}});
431 //0x07-0x1E should cause an illegal instruction exception
432 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
433 }
434 0x2A: decode RS1 {
435 0x00: Priv::rdprtpc({{
436 if(Tl == 0)
437 return new IllegalInstruction;
438 Rd = Tpc;
439 }});
440 0x01: Priv::rdprtnpc({{
441 if(Tl == 0)
442 return new IllegalInstruction;
443 Rd = Tnpc;
444 }});
445 0x02: Priv::rdprtstate({{
446 if(Tl == 0)
447 return new IllegalInstruction;
448 Rd = Tstate;
449 }});
450 0x03: Priv::rdprtt({{
451 if(Tl == 0)
452 return new IllegalInstruction;
453 Rd = Tt;
454 }});
455 0x04: Priv::rdprtick({{Rd = Tick;}});
456 0x05: Priv::rdprtba({{Rd = Tba;}});
457 0x06: Priv::rdprpstate({{Rd = Pstate;}});
458 0x07: Priv::rdprtl({{Rd = Tl;}});
459 0x08: Priv::rdprpil({{Rd = Pil;}});
460 0x09: Priv::rdprcwp({{Rd = Cwp;}});
461 0x0A: Priv::rdprcansave({{Rd = Cansave;}});
462 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});
463 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});
464 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}});
465 0x0E: Priv::rdprwstate({{Rd = Wstate;}});
466 //0x0F should cause an illegal instruction exception
467 0x10: Priv::rdprgl({{Rd = Gl;}});
468 //0x11-0x1F should cause an illegal instruction exception
469 }
470 0x2B: BasicOperate::flushw({{
471 if(NWindows - 2 - Cansave == 0)
472 {
473 if(Otherwin)
474 fault = new SpillNOther(Wstate<5:3>);
475 else
476 fault = new SpillNNormal(Wstate<2:0>);
477 }
478 }});
479 0x2C: decode MOVCC3
480 {
481 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
482 0x1: decode CC
483 {
484 0x0: movcci({{
485 if(passesCondition(Ccr<3:0>, COND4))
486 Rd = Rs2_or_imm11;
487 else
488 Rd = Rd;
489 }});
490 0x2: movccx({{
491 if(passesCondition(Ccr<7:4>, COND4))
492 Rd = Rs2_or_imm11;
493 else
494 Rd = Rd;
495 }});
496 }
497 }
498 0x2D: sdivx({{
499 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
500 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
501 }});
502 0x2E: decode RS1 {
503 0x0: IntOp::popc({{
504 int64_t count = 0;
505 uint64_t temp = Rs2_or_imm13;
506 //Count the 1s in the front 4bits until none are left
507 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
508 while(temp)
509 {
510 count += oneBits[temp & 0xF];
511 temp = temp >> 4;
512 }
513 Rd = count;
514 }});
515 }
516 0x2F: decode RCOND3
517 {
518 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
519 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
520 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
521 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
522 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
523 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
524 }
525 0x30: decode RD {
526 0x00: NoPriv::wry({{Y = Rs1 ^ Rs2_or_imm13;}});
527 //0x01 should cause an illegal instruction exception
528 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
529 0x03: NoPriv::wrasi({{Ccr = Rs1 ^ Rs2_or_imm13;}});
530 //0x04-0x05 should cause an illegal instruction exception
531 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
532 //0x07-0x0E should cause an illegal instruction exception
533 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
534 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
535 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
536 //0x12 should cause an illegal instruction exception
537 0x13: NoPriv::wrgsr({{
538 if(Fprs<2:> == 0 || Pstate<4:> == 0)
539 return new FpDisabled;
540 Gsr = Rs1 ^ Rs2_or_imm13;
541 }});
542 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
543 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});
544 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
545 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}});
546 0x18: NoPriv::wrstick({{
547 if(!Hpstate<2:>)
548 return new IllegalInstruction;
549 Stick = Rs1 ^ Rs2_or_imm13;
550 }});
551 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}});
552 0x1A: Priv::wrstrand_sts_reg({{
553 if(Pstate<2:> && !Hpstate<2:>)
554 StrandStsReg = StrandStsReg<63:1> |
555 (Rs1 ^ Rs2_or_imm13)<0:>;
556 else
557 StrandStsReg = Rs1 ^ Rs2_or_imm13;
558 }});
559 //0x1A is supposed to be reserved, but it writes the strand
560 //status register.
561 //0x1B-0x1F should cause an illegal instruction exception
562 }
563 0x31: decode FCN {
564 0x0: Priv::saved({{
565 assert(Cansave < NWindows - 2);
566 assert(Otherwin || Canrestore);
567 Cansave = Cansave + 1;
568 if(Otherwin == 0)
569 Canrestore = Canrestore - 1;
570 else
571 Otherwin = Otherwin - 1;
572 }});
573 0x1: Priv::restored({{
574 assert(Cansave || Otherwin);
575 assert(Canrestore < NWindows - 2);
576 Canrestore = Canrestore + 1;
577 if(Otherwin == 0)
578 Cansave = Cansave - 1;
579 else
580 Otherwin = Otherwin - 1;
581 }});
582 }
583 0x32: decode RD {
584 0x00: Priv::wrprtpc({{
585 if(Tl == 0)
586 return new IllegalInstruction;
587 else
588 Tpc = Rs1 ^ Rs2_or_imm13;
589 }});
590 0x01: Priv::wrprtnpc({{
591 if(Tl == 0)
592 return new IllegalInstruction;
593 else
594 Tnpc = Rs1 ^ Rs2_or_imm13;
595 }});
596 0x02: Priv::wrprtstate({{
597 if(Tl == 0)
598 return new IllegalInstruction;
599 else
600 Tstate = Rs1 ^ Rs2_or_imm13;
601 }});
602 0x03: Priv::wrprtt({{
603 if(Tl == 0)
604 return new IllegalInstruction;
605 else
606 Tt = Rs1 ^ Rs2_or_imm13;
607 }});
608 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
609 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
610 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
611 0x07: Priv::wrprtl({{
612 if(Pstate<2:> && !Hpstate<2:>)
613 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
614 else
615 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);
616 }});
617 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
618 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
619 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
620 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
621 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
622 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
623 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
624 //0x0F should cause an illegal instruction exception
625 0x10: Priv::wrprgl({{
626 if(Pstate<2:> && !Hpstate<2:>)
627 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL);
628 else
629 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
630 }});
631 //0x11-0x1F should cause an illegal instruction exception
632 }
633 0x33: decode RD {
634 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
635 0x01: HPriv::wrhprhtstate({{
636 if(Tl == 0)
637 return new IllegalInstruction;
638 Htstate = Rs1 ^ Rs2_or_imm13;
639 }});
640 //0x02 should cause an illegal instruction exception
641 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
642 //0x04 should cause an illegal instruction exception
643 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
644 //0x06-0x01D should cause an illegal instruction exception
645 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
646 }
647 0x34: decode OPF{
648 format BasicOperate{
649 0x01: fmovs({{
650 Frds.uw = Frs2s.uw;
651 //fsr.ftt = fsr.cexc = 0
652 Fsr &= ~(7 << 14);
653 Fsr &= ~(0x1F);
654 }});
655 0x02: fmovd({{
656 Frd.udw = Frs2.udw;
657 //fsr.ftt = fsr.cexc = 0
658 Fsr &= ~(7 << 14);
659 Fsr &= ~(0x1F);
660 }});
661 0x03: Trap::fmovq({{fault = new FpDisabled;}});
662 0x05: fnegs({{
663 Frds.uw = Frs2s.uw ^ (1UL << 31);
664 //fsr.ftt = fsr.cexc = 0
665 Fsr &= ~(7 << 14);
666 Fsr &= ~(0x1F);
667 }});
668 0x06: fnegd({{
669 Frd.udw = Frs2.udw ^ (1ULL << 63);
670 //fsr.ftt = fsr.cexc = 0
671 Fsr &= ~(7 << 14);
672 Fsr &= ~(0x1F);
673 }});
674 0x07: Trap::fnegq({{fault = new FpDisabled;}});
675 0x09: fabss({{
676 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;
677 //fsr.ftt = fsr.cexc = 0
678 Fsr &= ~(7 << 14);
679 Fsr &= ~(0x1F);
680 }});
681 0x0A: fabsd({{
682 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;
683 //fsr.ftt = fsr.cexc = 0
684 Fsr &= ~(7 << 14);
685 Fsr &= ~(0x1F);
686 }});
687 0x0B: Trap::fabsq({{fault = new FpDisabled;}});
688 0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}});
689 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}});
690 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
691 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
692 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
693 0x43: Trap::faddq({{fault = new FpDisabled;}});
694 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
695 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
696 0x47: Trap::fsubq({{fault = new FpDisabled;}});
697 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
698 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
699 0x4B: Trap::fmulq({{fault = new FpDisabled;}});
700 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
701 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
702 0x4F: Trap::fdivq({{fault = new FpDisabled;}});
703 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
704 0x6E: Trap::fdmulq({{fault = new FpDisabled;}});
705 0x81: fstox({{
706 Frd.df = (double)static_cast<int64_t>(Frs2s.sf);
707 }});
708 0x82: fdtox({{
709 Frd.df = (double)static_cast<int64_t>(Frs2.df);
710 }});
711 0x83: Trap::fqtox({{fault = new FpDisabled;}});
712 0x84: fxtos({{
713 Frds.sf = static_cast<float>((int64_t)Frs2.df);
714 }});
715 0x88: fxtod({{
716 Frd.df = static_cast<double>((int64_t)Frs2.df);
717 }});
718 0x8C: Trap::fxtoq({{fault = new FpDisabled;}});
719 0xC4: fitos({{
720 Frds.sf = static_cast<float>((int32_t)Frs2s.sf);
721 }});
722 0xC6: fdtos({{Frds.sf = Frs2.df;}});
723 0xC7: Trap::fqtos({{fault = new FpDisabled;}});
724 0xC8: fitod({{
725 Frd.df = static_cast<double>((int32_t)Frs2s.sf);
726 }});
727 0xC9: fstod({{Frd.df = Frs2s.sf;}});
728 0xCB: Trap::fqtod({{fault = new FpDisabled;}});
729 0xCC: Trap::fitoq({{fault = new FpDisabled;}});
730 0xCD: Trap::fstoq({{fault = new FpDisabled;}});
731 0xCE: Trap::fdtoq({{fault = new FpDisabled;}});
732 0xD1: fstoi({{
733 Frds.sf = (float)static_cast<int32_t>(Frs2s.sf);
734 }});
735 0xD2: fdtoi({{
736 Frds.sf = (float)static_cast<int32_t>(Frs2.df);
737 }});
738 0xD3: Trap::fqtoi({{fault = new FpDisabled;}});
739 default: Trap::fpop1({{fault = new FpDisabled;}});
740 }
741 }
742 0x35: Trap::fpop2({{fault = new FpDisabled;}});
743 //This used to be just impdep1, but now it's a whole bunch
744 //of instructions
745 0x36: decode OPF{
746 0x00: Trap::edge8({{fault = new IllegalInstruction;}});
747 0x01: Trap::edge8n({{fault = new IllegalInstruction;}});
748 0x02: Trap::edge8l({{fault = new IllegalInstruction;}});
749 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}});
750 0x04: Trap::edge16({{fault = new IllegalInstruction;}});
751 0x05: Trap::edge16n({{fault = new IllegalInstruction;}});
752 0x06: Trap::edge16l({{fault = new IllegalInstruction;}});
753 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}});
754 0x08: Trap::edge32({{fault = new IllegalInstruction;}});
755 0x09: Trap::edge32n({{fault = new IllegalInstruction;}});
756 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}});
757 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}});
758 0x10: Trap::array8({{fault = new IllegalInstruction;}});
759 0x12: Trap::array16({{fault = new IllegalInstruction;}});
760 0x14: Trap::array32({{fault = new IllegalInstruction;}});
761 0x18: BasicOperate::alignaddr({{
762 uint64_t sum = Rs1 + Rs2;
763 Rd = sum & ~7;
764 Gsr = (Gsr & ~7) | (sum & 7);
765 }});
766 0x19: Trap::bmask({{fault = new IllegalInstruction;}});
767 0x1A: BasicOperate::alignaddresslittle({{
768 uint64_t sum = Rs1 + Rs2;
769 Rd = sum & ~7;
770 Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
771 }});
772 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}});
773 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}});
774 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}});
775 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}});
776 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}});
777 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}});
778 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}});
779 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}});
780 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}});
781 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}});
782 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}});
783 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}});
784 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}});
785 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}});
786 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}});
787 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
788 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
789 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
790 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
791 0x48: BasicOperate::faligndata({{
792 uint64_t msbX = Frs1.udw;
793 uint64_t lsbX = Frs2.udw;
794 //Some special cases need to be split out, first
795 //because they're the most likely to be used, and
796 //second because otherwise, we end up shifting by
797 //greater than the width of the type being shifted,
798 //namely 64, which produces undefined results according
799 //to the C standard.
800 switch(Gsr<2:0>)
801 {
802 case 0:
803 Frd.udw = msbX;
804 break;
805 case 8:
806 Frd.udw = lsbX;
807 break;
808 default:
809 uint64_t msbShift = Gsr<2:0> * 8;
810 uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
811 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
812 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
813 Frd.udw = ((msbX & msbMask) << msbShift) |
814 ((lsbX & lsbMask) >> lsbShift);
815 }
816 }});
817 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
818 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}});
819 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}});
820 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}});
821 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}});
822 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}});
823 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}});
824 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}});
825 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}});
826 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}});
827 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}});
828 0x60: BasicOperate::fzero({{Frd.df = 0;}});
829 0x61: BasicOperate::fzeros({{Frds.sf = 0;}});
830 0x62: Trap::fnor({{fault = new IllegalInstruction;}});
831 0x63: Trap::fnors({{fault = new IllegalInstruction;}});
832 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}});
833 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}});
834 0x66: BasicOperate::fnot2({{
835 Frd.df = (double)(~((uint64_t)Frs2.df));
836 }});
837 0x67: BasicOperate::fnot2s({{
838 Frds.sf = (float)(~((uint32_t)Frs2s.sf));
839 }});
840 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}});
841 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}});
842 0x6A: BasicOperate::fnot1({{
843 Frd.df = (double)(~((uint64_t)Frs1.df));
844 }});
845 0x6B: BasicOperate::fnot1s({{
846 Frds.sf = (float)(~((uint32_t)Frs1s.sf));
847 }});
848 0x6C: Trap::fxor({{fault = new IllegalInstruction;}});
849 0x6D: Trap::fxors({{fault = new IllegalInstruction;}});
850 0x6E: Trap::fnand({{fault = new IllegalInstruction;}});
851 0x6F: Trap::fnands({{fault = new IllegalInstruction;}});
852 0x70: Trap::fand({{fault = new IllegalInstruction;}});
853 0x71: Trap::fands({{fault = new IllegalInstruction;}});
854 0x72: Trap::fxnor({{fault = new IllegalInstruction;}});
855 0x73: Trap::fxnors({{fault = new IllegalInstruction;}});
856 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}});
857 0x75: BasicOperate::fsrc1s({{Frd.uw = Frs1.uw;}});
858 0x76: Trap::fornot2({{fault = new IllegalInstruction;}});
859 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}});
860 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}});
861 0x79: BasicOperate::fsrc2s({{Frd.uw = Frs2.uw;}});
862 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}});
863 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}});
864 0x7C: Trap::for({{fault = new IllegalInstruction;}});
865 0x7D: Trap::fors({{fault = new IllegalInstruction;}});
866 0x7E: Trap::fone({{fault = new IllegalInstruction;}});
867 0x7F: Trap::fones({{fault = new IllegalInstruction;}});
868 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
869 0x81: Trap::siam({{fault = new IllegalInstruction;}});
870 }
871 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
872 0x38: Branch::jmpl({{
873 Addr target = Rs1 + Rs2_or_imm13;
874 if(target & 0x3)
875 fault = new MemAddressNotAligned;
876 else
877 {
878 Rd = xc->readPC();
879 NNPC = target;
880 }
881 }});
882 0x39: Branch::return({{
883 //If both MemAddressNotAligned and
884 //a fill trap happen, it's not clear
885 //which one should be returned.
886 Addr target = Rs1 + Rs2_or_imm13;
887 if(target & 0x3)
888 fault = new MemAddressNotAligned;
889 else
890 NNPC = target;
891 if(fault == NoFault)
892 {
893 if(Canrestore == 0)
894 {
895 if(Otherwin)
896 fault = new FillNOther(Wstate<5:3>);
897 else
898 fault = new FillNNormal(Wstate<2:0>);
899 }
900 else
901 {
902 //CWP should be set directly so that it always happens
903 //Also, this will allow writing to the new window and
904 //reading from the old one
905 Cwp = (Cwp - 1 + NWindows) % NWindows;
906 Cansave = Cansave + 1;
907 Canrestore = Canrestore - 1;
908 //This is here to make sure the CWP is written
909 //no matter what. This ensures that the results
910 //are written in the new window as well.
911 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
912 }
913 }
914 }});
915 0x3A: decode CC
916 {
917 0x0: Trap::tcci({{
918 if(passesCondition(Ccr<3:0>, COND2))
919 {
920#if FULL_SYSTEM
921 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
922 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
923 fault = new TrapInstruction(lTrapNum);
924#else
925 DPRINTF(Sparc, "The syscall number is %d\n", R1);
926 xc->syscall(R1);
927#endif
928 }
929 }});
930 0x2: Trap::tccx({{
931 if(passesCondition(Ccr<7:4>, COND2))
932 {
933#if FULL_SYSTEM
934 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
935 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
936 fault = new TrapInstruction(lTrapNum);
937#else
938 DPRINTF(Sparc, "The syscall number is %d\n", R1);
939 xc->syscall(R1);
940#endif
941 }
942 }});
943 }
944 0x3B: Nop::flush({{/*Instruction memory flush*/}});
945 0x3C: save({{
946 //CWP should be set directly so that it always happens
947 //Also, this will allow writing to the new window and
948 //reading from the old one
949 if(Cansave == 0)
950 {
951 if(Otherwin)
952 fault = new SpillNOther(Wstate<5:3>);
953 else
954 fault = new SpillNNormal(Wstate<2:0>);
955 //Cwp = (Cwp + 2) % NWindows;
956 }
957 else if(Cleanwin - Canrestore == 0)
958 {
959 //Cwp = (Cwp + 1) % NWindows;
960 fault = new CleanWindow;
961 }
962 else
963 {
964 Cwp = (Cwp + 1) % NWindows;
965 Rd = Rs1 + Rs2_or_imm13;
966 Cansave = Cansave - 1;
967 Canrestore = Canrestore + 1;
968 //This is here to make sure the CWP is written
969 //no matter what. This ensures that the results
970 //are written in the new window as well.
971 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
972 }
973 }});
974 0x3D: restore({{
975 if(Canrestore == 0)
976 {
977 if(Otherwin)
978 fault = new FillNOther(Wstate<5:3>);
979 else
980 fault = new FillNNormal(Wstate<2:0>);
981 }
982 else
983 {
984 //CWP should be set directly so that it always happens
985 //Also, this will allow writing to the new window and
986 //reading from the old one
987 Cwp = (Cwp - 1 + NWindows) % NWindows;
988 Rd = Rs1 + Rs2_or_imm13;
989 Cansave = Cansave + 1;
990 Canrestore = Canrestore - 1;
991 //This is here to make sure the CWP is written
992 //no matter what. This ensures that the results
993 //are written in the new window as well.
994 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
995 }
996 }});
997 0x3E: decode FCN {
998 0x0: Priv::done({{
999 if(Tl == 0)
1000 return new IllegalInstruction;
1001
1002 Cwp = Tstate<4:0>;
1003 Pstate = Tstate<20:8>;
1004 Asi = Tstate<31:24>;
1005 Ccr = Tstate<39:32>;
1006 Gl = Tstate<42:40>;
| 1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OP default Unknown::unknown()
37{
38 0x0: decode OP2
39 {
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 //bpcc
45 0x1: decode COND2
46 {
47 //Branch Always
48 0x8: decode A
49 {
50 0x0: bpa(19, {{
51 NNPC = xc->readPC() + disp;
52 }});
53 0x1: bpa(19, {{
54 NPC = xc->readPC() + disp;
55 NNPC = NPC + 4;
56 }}, ',a');
57 }
58 //Branch Never
59 0x0: decode A
60 {
61 0x0: bpn(19, {{
62 NNPC = NNPC;//Don't do anything
63 }});
64 0x1: bpn(19, {{
65 NPC = xc->readNextPC() + 4;
66 NNPC = NPC + 4;
67 }}, ',a');
68 }
69 default: decode BPCC
70 {
71 0x0: bpcci(19, {{
72 if(passesCondition(Ccr<3:0>, COND2))
73 NNPC = xc->readPC() + disp;
74 else
75 handle_annul
76 }});
77 0x2: bpccx(19, {{
78 if(passesCondition(Ccr<7:4>, COND2))
79 NNPC = xc->readPC() + disp;
80 else
81 handle_annul
82 }});
83 }
84 }
85 //bicc
86 0x2: decode COND2
87 {
88 //Branch Always
89 0x8: decode A
90 {
91 0x0: ba(22, {{
92 NNPC = xc->readPC() + disp;
93 }});
94 0x1: ba(22, {{
95 NPC = xc->readPC() + disp;
96 NNPC = NPC + 4;
97 }}, ',a');
98 }
99 //Branch Never
100 0x0: decode A
101 {
102 0x0: bn(22, {{
103 NNPC = NNPC;//Don't do anything
104 }});
105 0x1: bn(22, {{
106 NPC = xc->readNextPC() + 4;
107 NNPC = NPC + 4;
108 }}, ',a');
109 }
110 default: bicc(22, {{
111 if(passesCondition(Ccr<3:0>, COND2))
112 NNPC = xc->readPC() + disp;
113 else
114 handle_annul
115 }});
116 }
117 }
118 0x3: decode RCOND2
119 {
120 format BranchSplit
121 {
122 0x1: bpreq({{
123 if(Rs1.sdw == 0)
124 NNPC = xc->readPC() + disp;
125 else
126 handle_annul
127 }});
128 0x2: bprle({{
129 if(Rs1.sdw <= 0)
130 NNPC = xc->readPC() + disp;
131 else
132 handle_annul
133 }});
134 0x3: bprl({{
135 if(Rs1.sdw < 0)
136 NNPC = xc->readPC() + disp;
137 else
138 handle_annul
139 }});
140 0x5: bprne({{
141 if(Rs1.sdw != 0)
142 NNPC = xc->readPC() + disp;
143 else
144 handle_annul
145 }});
146 0x6: bprg({{
147 if(Rs1.sdw > 0)
148 NNPC = xc->readPC() + disp;
149 else
150 handle_annul
151 }});
152 0x7: bprge({{
153 if(Rs1.sdw >= 0)
154 NNPC = xc->readPC() + disp;
155 else
156 handle_annul
157 }});
158 }
159 }
160 //SETHI (or NOP if rd == 0 and imm == 0)
161 0x4: SetHi::sethi({{Rd.udw = imm;}});
162 0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
163 0x6: Trap::fbfcc({{fault = new FpDisabled;}});
164 }
165 0x1: BranchN::call(30, {{
166 R15 = xc->readPC();
167 NNPC = R15 + disp;
168 }});
169 0x2: decode OP3 {
170 format IntOp {
171 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
172 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
173 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
174 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
175 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
176 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}});
177 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}});
178 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
179 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
180 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
181 0x0A: umul({{
182 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
183 Y = Rd<63:32>;
184 }});
185 0x0B: smul({{
186 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
187 Y = Rd.sdw;
188 }});
189 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
190 0x0D: udivx({{
191 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
192 else Rd.udw = Rs1.udw / Rs2_or_imm13;
193 }});
194 0x0E: udiv({{
195 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
196 else
197 {
198 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
199 if(Rd.udw >> 32 != 0)
200 Rd.udw = 0xFFFFFFFF;
201 }
202 }});
203 0x0F: sdiv({{
204 if(Rs2_or_imm13.sdw == 0)
205 fault = new DivisionByZero;
206 else
207 {
208 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
209 if(Rd.udw<63:31> != 0)
210 Rd.udw = 0x7FFFFFFF;
211 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
212 Rd.udw = 0xFFFFFFFF80000000ULL;
213 }
214 }});
215 }
216 format IntOpCc {
217 0x10: addcc({{
218 int64_t resTemp, val2 = Rs2_or_imm13;
219 Rd = resTemp = Rs1 + val2;}},
220 {{(Rs1<31:0> + val2<31:0>)<32:>}},
221 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
222 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
223 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
224 );
225 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
226 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
227 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
228 0x14: subcc({{
229 int64_t val2 = Rs2_or_imm13;
230 Rd = Rs1 - val2;}},
231 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
232 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
233 {{(~(Rs1<63:1> + (~val2)<63:1> +
234 (Rs1 | ~val2)<0:>))<63:>}},
235 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
236 );
237 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
238 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
239 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
240 0x18: addccc({{
241 int64_t resTemp, val2 = Rs2_or_imm13;
242 int64_t carryin = Ccr<0:0>;
243 Rd = resTemp = Rs1 + val2 + carryin;}},
244 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
245 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
246 {{(Rs1<63:1> + val2<63:1> +
247 ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
248 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
249 );
250 0x1A: umulcc({{
251 uint64_t resTemp;
252 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
253 Y = resTemp<63:32>;}},
254 {{0}},{{0}},{{0}},{{0}});
255 0x1B: smulcc({{
256 int64_t resTemp;
257 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>;
258 Y = resTemp<63:32>;}},
259 {{0}},{{0}},{{0}},{{0}});
260 0x1C: subccc({{
261 int64_t resTemp, val2 = Rs2_or_imm13;
262 int64_t carryin = Ccr<0:0>;
263 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
264 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
265 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
266 {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
267 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
268 );
269 0x1D: udivxcc({{
270 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
271 else Rd = Rs1.udw / Rs2_or_imm13.udw;}}
272 ,{{0}},{{0}},{{0}},{{0}});
273 0x1E: udivcc({{
274 uint32_t resTemp, val2 = Rs2_or_imm13.udw;
275 int32_t overflow = 0;
276 if(val2 == 0) fault = new DivisionByZero;
277 else
278 {
279 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
280 overflow = (resTemp<63:32> != 0);
281 if(overflow) Rd = resTemp = 0xFFFFFFFF;
282 else Rd = resTemp;
283 } }},
284 {{0}},
285 {{overflow}},
286 {{0}},
287 {{0}}
288 );
289 0x1F: sdivcc({{
290 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
291 bool overflow = false, underflow = false;
292 if(val2 == 0) fault = new DivisionByZero;
293 else
294 {
295 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
296 overflow = (Rd<63:31> != 0);
297 underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF);
298 if(overflow) Rd = 0x7FFFFFFF;
299 else if(underflow) Rd = 0xFFFFFFFF80000000ULL;
300 } }},
301 {{0}},
302 {{overflow || underflow}},
303 {{0}},
304 {{0}}
305 );
306 0x20: taddcc({{
307 int64_t resTemp, val2 = Rs2_or_imm13;
308 Rd = resTemp = Rs1 + val2;
309 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
310 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
311 {{overflow}},
312 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
313 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
314 );
315 0x21: tsubcc({{
316 int64_t resTemp, val2 = Rs2_or_imm13;
317 Rd = resTemp = Rs1 + val2;
318 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
319 {{(Rs1<31:0> + val2<31:0>)<32:0>}},
320 {{overflow}},
321 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
322 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
323 );
324 0x22: taddcctv({{
325 int64_t val2 = Rs2_or_imm13;
326 Rd = Rs1 + val2;
327 int32_t overflow = Rs1<1:0> || val2<1:0> ||
328 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
329 if(overflow) fault = new TagOverflow;}},
330 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
331 {{overflow}},
332 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
333 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}}
334 );
335 0x23: tsubcctv({{
336 int64_t resTemp, val2 = Rs2_or_imm13;
337 Rd = resTemp = Rs1 + val2;
338 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
339 if(overflow) fault = new TagOverflow;}},
340 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
341 {{overflow}},
342 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
343 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
344 );
345 0x24: mulscc({{
346 int64_t resTemp, multiplicand = Rs2_or_imm13;
347 int32_t multiplier = Rs1<31:0>;
348 int32_t savedLSB = Rs1<0:>;
349 multiplier = multiplier<31:1> |
350 ((Ccr<3:3> ^ Ccr<1:1>) << 32);
351 if(!Y<0:>)
352 multiplicand = 0;
353 Rd = resTemp = multiplicand + multiplier;
354 Y = Y<31:1> | (savedLSB << 31);}},
355 {{((multiplicand<31:0> + multiplier<31:0>)<32:0>)}},
356 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
357 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
358 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
359 );
360 }
361 format IntOp
362 {
363 0x25: decode X {
364 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
365 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
366 }
367 0x26: decode X {
368 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
369 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
370 }
371 0x27: decode X {
372 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
373 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
374 }
375 0x28: decode RS1 {
376 0x00: NoPriv::rdy({{Rd = Y;}});
377 //1 should cause an illegal instruction exception
378 0x02: NoPriv::rdccr({{Rd = Ccr;}});
379 0x03: NoPriv::rdasi({{Rd = Asi;}});
380 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
381 0x05: NoPriv::rdpc({{
382 if(Pstate<3:>)
383 Rd = (xc->readPC())<31:0>;
384 else
385 Rd = xc->readPC();}});
386 0x06: NoPriv::rdfprs({{
387 //Wait for all fpops to finish.
388 Rd = Fprs;
389 }});
390 //7-14 should cause an illegal instruction exception
391 0x0F: decode I {
392 0x0: Nop::stbar({{/*stuff*/}});
393 0x1: Nop::membar({{/*stuff*/}});
394 }
395 0x10: Priv::rdpcr({{Rd = Pcr;}});
396 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
397 //0x12 should cause an illegal instruction exception
398 0x13: NoPriv::rdgsr({{
399 if(Fprs<2:> == 0 || Pstate<4:> == 0)
400 Rd = Gsr;
401 else
402 fault = new FpDisabled;
403 }});
404 //0x14-0x15 should cause an illegal instruction exception
405 0x16: Priv::rdsoftint({{Rd = Softint;}});
406 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
407 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}});
408 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
409 0x1A: Priv::rdstrand_sts_reg({{
410 if(Pstate<2:> && !Hpstate<2:>)
411 Rd = StrandStsReg<0:>;
412 else
413 Rd = StrandStsReg;
414 }});
415 //0x1A is supposed to be reserved, but it reads the strand
416 //status register.
417 //0x1B-0x1F should cause an illegal instruction exception
418 }
419 0x29: decode RS1 {
420 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
421 0x01: HPriv::rdhprhtstate({{
422 if(Tl == 0)
423 return new IllegalInstruction;
424 Rd = Htstate;
425 }});
426 //0x02 should cause an illegal instruction exception
427 0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
428 //0x04 should cause an illegal instruction exception
429 0x05: HPriv::rdhprhtba({{Rd = Htba;}});
430 0x06: HPriv::rdhprhver({{Rd = Hver;}});
431 //0x07-0x1E should cause an illegal instruction exception
432 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
433 }
434 0x2A: decode RS1 {
435 0x00: Priv::rdprtpc({{
436 if(Tl == 0)
437 return new IllegalInstruction;
438 Rd = Tpc;
439 }});
440 0x01: Priv::rdprtnpc({{
441 if(Tl == 0)
442 return new IllegalInstruction;
443 Rd = Tnpc;
444 }});
445 0x02: Priv::rdprtstate({{
446 if(Tl == 0)
447 return new IllegalInstruction;
448 Rd = Tstate;
449 }});
450 0x03: Priv::rdprtt({{
451 if(Tl == 0)
452 return new IllegalInstruction;
453 Rd = Tt;
454 }});
455 0x04: Priv::rdprtick({{Rd = Tick;}});
456 0x05: Priv::rdprtba({{Rd = Tba;}});
457 0x06: Priv::rdprpstate({{Rd = Pstate;}});
458 0x07: Priv::rdprtl({{Rd = Tl;}});
459 0x08: Priv::rdprpil({{Rd = Pil;}});
460 0x09: Priv::rdprcwp({{Rd = Cwp;}});
461 0x0A: Priv::rdprcansave({{Rd = Cansave;}});
462 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});
463 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});
464 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}});
465 0x0E: Priv::rdprwstate({{Rd = Wstate;}});
466 //0x0F should cause an illegal instruction exception
467 0x10: Priv::rdprgl({{Rd = Gl;}});
468 //0x11-0x1F should cause an illegal instruction exception
469 }
470 0x2B: BasicOperate::flushw({{
471 if(NWindows - 2 - Cansave == 0)
472 {
473 if(Otherwin)
474 fault = new SpillNOther(Wstate<5:3>);
475 else
476 fault = new SpillNNormal(Wstate<2:0>);
477 }
478 }});
479 0x2C: decode MOVCC3
480 {
481 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
482 0x1: decode CC
483 {
484 0x0: movcci({{
485 if(passesCondition(Ccr<3:0>, COND4))
486 Rd = Rs2_or_imm11;
487 else
488 Rd = Rd;
489 }});
490 0x2: movccx({{
491 if(passesCondition(Ccr<7:4>, COND4))
492 Rd = Rs2_or_imm11;
493 else
494 Rd = Rd;
495 }});
496 }
497 }
498 0x2D: sdivx({{
499 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
500 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
501 }});
502 0x2E: decode RS1 {
503 0x0: IntOp::popc({{
504 int64_t count = 0;
505 uint64_t temp = Rs2_or_imm13;
506 //Count the 1s in the front 4bits until none are left
507 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
508 while(temp)
509 {
510 count += oneBits[temp & 0xF];
511 temp = temp >> 4;
512 }
513 Rd = count;
514 }});
515 }
516 0x2F: decode RCOND3
517 {
518 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
519 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
520 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
521 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
522 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
523 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
524 }
525 0x30: decode RD {
526 0x00: NoPriv::wry({{Y = Rs1 ^ Rs2_or_imm13;}});
527 //0x01 should cause an illegal instruction exception
528 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
529 0x03: NoPriv::wrasi({{Ccr = Rs1 ^ Rs2_or_imm13;}});
530 //0x04-0x05 should cause an illegal instruction exception
531 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
532 //0x07-0x0E should cause an illegal instruction exception
533 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
534 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
535 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
536 //0x12 should cause an illegal instruction exception
537 0x13: NoPriv::wrgsr({{
538 if(Fprs<2:> == 0 || Pstate<4:> == 0)
539 return new FpDisabled;
540 Gsr = Rs1 ^ Rs2_or_imm13;
541 }});
542 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
543 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});
544 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
545 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}});
546 0x18: NoPriv::wrstick({{
547 if(!Hpstate<2:>)
548 return new IllegalInstruction;
549 Stick = Rs1 ^ Rs2_or_imm13;
550 }});
551 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}});
552 0x1A: Priv::wrstrand_sts_reg({{
553 if(Pstate<2:> && !Hpstate<2:>)
554 StrandStsReg = StrandStsReg<63:1> |
555 (Rs1 ^ Rs2_or_imm13)<0:>;
556 else
557 StrandStsReg = Rs1 ^ Rs2_or_imm13;
558 }});
559 //0x1A is supposed to be reserved, but it writes the strand
560 //status register.
561 //0x1B-0x1F should cause an illegal instruction exception
562 }
563 0x31: decode FCN {
564 0x0: Priv::saved({{
565 assert(Cansave < NWindows - 2);
566 assert(Otherwin || Canrestore);
567 Cansave = Cansave + 1;
568 if(Otherwin == 0)
569 Canrestore = Canrestore - 1;
570 else
571 Otherwin = Otherwin - 1;
572 }});
573 0x1: Priv::restored({{
574 assert(Cansave || Otherwin);
575 assert(Canrestore < NWindows - 2);
576 Canrestore = Canrestore + 1;
577 if(Otherwin == 0)
578 Cansave = Cansave - 1;
579 else
580 Otherwin = Otherwin - 1;
581 }});
582 }
583 0x32: decode RD {
584 0x00: Priv::wrprtpc({{
585 if(Tl == 0)
586 return new IllegalInstruction;
587 else
588 Tpc = Rs1 ^ Rs2_or_imm13;
589 }});
590 0x01: Priv::wrprtnpc({{
591 if(Tl == 0)
592 return new IllegalInstruction;
593 else
594 Tnpc = Rs1 ^ Rs2_or_imm13;
595 }});
596 0x02: Priv::wrprtstate({{
597 if(Tl == 0)
598 return new IllegalInstruction;
599 else
600 Tstate = Rs1 ^ Rs2_or_imm13;
601 }});
602 0x03: Priv::wrprtt({{
603 if(Tl == 0)
604 return new IllegalInstruction;
605 else
606 Tt = Rs1 ^ Rs2_or_imm13;
607 }});
608 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
609 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
610 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
611 0x07: Priv::wrprtl({{
612 if(Pstate<2:> && !Hpstate<2:>)
613 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
614 else
615 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);
616 }});
617 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
618 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
619 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
620 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
621 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
622 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
623 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
624 //0x0F should cause an illegal instruction exception
625 0x10: Priv::wrprgl({{
626 if(Pstate<2:> && !Hpstate<2:>)
627 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL);
628 else
629 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
630 }});
631 //0x11-0x1F should cause an illegal instruction exception
632 }
633 0x33: decode RD {
634 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
635 0x01: HPriv::wrhprhtstate({{
636 if(Tl == 0)
637 return new IllegalInstruction;
638 Htstate = Rs1 ^ Rs2_or_imm13;
639 }});
640 //0x02 should cause an illegal instruction exception
641 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
642 //0x04 should cause an illegal instruction exception
643 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
644 //0x06-0x01D should cause an illegal instruction exception
645 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
646 }
647 0x34: decode OPF{
648 format BasicOperate{
649 0x01: fmovs({{
650 Frds.uw = Frs2s.uw;
651 //fsr.ftt = fsr.cexc = 0
652 Fsr &= ~(7 << 14);
653 Fsr &= ~(0x1F);
654 }});
655 0x02: fmovd({{
656 Frd.udw = Frs2.udw;
657 //fsr.ftt = fsr.cexc = 0
658 Fsr &= ~(7 << 14);
659 Fsr &= ~(0x1F);
660 }});
661 0x03: Trap::fmovq({{fault = new FpDisabled;}});
662 0x05: fnegs({{
663 Frds.uw = Frs2s.uw ^ (1UL << 31);
664 //fsr.ftt = fsr.cexc = 0
665 Fsr &= ~(7 << 14);
666 Fsr &= ~(0x1F);
667 }});
668 0x06: fnegd({{
669 Frd.udw = Frs2.udw ^ (1ULL << 63);
670 //fsr.ftt = fsr.cexc = 0
671 Fsr &= ~(7 << 14);
672 Fsr &= ~(0x1F);
673 }});
674 0x07: Trap::fnegq({{fault = new FpDisabled;}});
675 0x09: fabss({{
676 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;
677 //fsr.ftt = fsr.cexc = 0
678 Fsr &= ~(7 << 14);
679 Fsr &= ~(0x1F);
680 }});
681 0x0A: fabsd({{
682 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;
683 //fsr.ftt = fsr.cexc = 0
684 Fsr &= ~(7 << 14);
685 Fsr &= ~(0x1F);
686 }});
687 0x0B: Trap::fabsq({{fault = new FpDisabled;}});
688 0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}});
689 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}});
690 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
691 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
692 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
693 0x43: Trap::faddq({{fault = new FpDisabled;}});
694 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
695 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
696 0x47: Trap::fsubq({{fault = new FpDisabled;}});
697 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
698 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
699 0x4B: Trap::fmulq({{fault = new FpDisabled;}});
700 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
701 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
702 0x4F: Trap::fdivq({{fault = new FpDisabled;}});
703 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
704 0x6E: Trap::fdmulq({{fault = new FpDisabled;}});
705 0x81: fstox({{
706 Frd.df = (double)static_cast<int64_t>(Frs2s.sf);
707 }});
708 0x82: fdtox({{
709 Frd.df = (double)static_cast<int64_t>(Frs2.df);
710 }});
711 0x83: Trap::fqtox({{fault = new FpDisabled;}});
712 0x84: fxtos({{
713 Frds.sf = static_cast<float>((int64_t)Frs2.df);
714 }});
715 0x88: fxtod({{
716 Frd.df = static_cast<double>((int64_t)Frs2.df);
717 }});
718 0x8C: Trap::fxtoq({{fault = new FpDisabled;}});
719 0xC4: fitos({{
720 Frds.sf = static_cast<float>((int32_t)Frs2s.sf);
721 }});
722 0xC6: fdtos({{Frds.sf = Frs2.df;}});
723 0xC7: Trap::fqtos({{fault = new FpDisabled;}});
724 0xC8: fitod({{
725 Frd.df = static_cast<double>((int32_t)Frs2s.sf);
726 }});
727 0xC9: fstod({{Frd.df = Frs2s.sf;}});
728 0xCB: Trap::fqtod({{fault = new FpDisabled;}});
729 0xCC: Trap::fitoq({{fault = new FpDisabled;}});
730 0xCD: Trap::fstoq({{fault = new FpDisabled;}});
731 0xCE: Trap::fdtoq({{fault = new FpDisabled;}});
732 0xD1: fstoi({{
733 Frds.sf = (float)static_cast<int32_t>(Frs2s.sf);
734 }});
735 0xD2: fdtoi({{
736 Frds.sf = (float)static_cast<int32_t>(Frs2.df);
737 }});
738 0xD3: Trap::fqtoi({{fault = new FpDisabled;}});
739 default: Trap::fpop1({{fault = new FpDisabled;}});
740 }
741 }
742 0x35: Trap::fpop2({{fault = new FpDisabled;}});
743 //This used to be just impdep1, but now it's a whole bunch
744 //of instructions
745 0x36: decode OPF{
746 0x00: Trap::edge8({{fault = new IllegalInstruction;}});
747 0x01: Trap::edge8n({{fault = new IllegalInstruction;}});
748 0x02: Trap::edge8l({{fault = new IllegalInstruction;}});
749 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}});
750 0x04: Trap::edge16({{fault = new IllegalInstruction;}});
751 0x05: Trap::edge16n({{fault = new IllegalInstruction;}});
752 0x06: Trap::edge16l({{fault = new IllegalInstruction;}});
753 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}});
754 0x08: Trap::edge32({{fault = new IllegalInstruction;}});
755 0x09: Trap::edge32n({{fault = new IllegalInstruction;}});
756 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}});
757 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}});
758 0x10: Trap::array8({{fault = new IllegalInstruction;}});
759 0x12: Trap::array16({{fault = new IllegalInstruction;}});
760 0x14: Trap::array32({{fault = new IllegalInstruction;}});
761 0x18: BasicOperate::alignaddr({{
762 uint64_t sum = Rs1 + Rs2;
763 Rd = sum & ~7;
764 Gsr = (Gsr & ~7) | (sum & 7);
765 }});
766 0x19: Trap::bmask({{fault = new IllegalInstruction;}});
767 0x1A: BasicOperate::alignaddresslittle({{
768 uint64_t sum = Rs1 + Rs2;
769 Rd = sum & ~7;
770 Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
771 }});
772 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}});
773 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}});
774 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}});
775 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}});
776 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}});
777 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}});
778 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}});
779 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}});
780 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}});
781 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}});
782 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}});
783 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}});
784 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}});
785 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}});
786 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}});
787 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
788 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
789 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
790 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
791 0x48: BasicOperate::faligndata({{
792 uint64_t msbX = Frs1.udw;
793 uint64_t lsbX = Frs2.udw;
794 //Some special cases need to be split out, first
795 //because they're the most likely to be used, and
796 //second because otherwise, we end up shifting by
797 //greater than the width of the type being shifted,
798 //namely 64, which produces undefined results according
799 //to the C standard.
800 switch(Gsr<2:0>)
801 {
802 case 0:
803 Frd.udw = msbX;
804 break;
805 case 8:
806 Frd.udw = lsbX;
807 break;
808 default:
809 uint64_t msbShift = Gsr<2:0> * 8;
810 uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
811 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
812 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
813 Frd.udw = ((msbX & msbMask) << msbShift) |
814 ((lsbX & lsbMask) >> lsbShift);
815 }
816 }});
817 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
818 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}});
819 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}});
820 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}});
821 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}});
822 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}});
823 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}});
824 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}});
825 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}});
826 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}});
827 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}});
828 0x60: BasicOperate::fzero({{Frd.df = 0;}});
829 0x61: BasicOperate::fzeros({{Frds.sf = 0;}});
830 0x62: Trap::fnor({{fault = new IllegalInstruction;}});
831 0x63: Trap::fnors({{fault = new IllegalInstruction;}});
832 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}});
833 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}});
834 0x66: BasicOperate::fnot2({{
835 Frd.df = (double)(~((uint64_t)Frs2.df));
836 }});
837 0x67: BasicOperate::fnot2s({{
838 Frds.sf = (float)(~((uint32_t)Frs2s.sf));
839 }});
840 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}});
841 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}});
842 0x6A: BasicOperate::fnot1({{
843 Frd.df = (double)(~((uint64_t)Frs1.df));
844 }});
845 0x6B: BasicOperate::fnot1s({{
846 Frds.sf = (float)(~((uint32_t)Frs1s.sf));
847 }});
848 0x6C: Trap::fxor({{fault = new IllegalInstruction;}});
849 0x6D: Trap::fxors({{fault = new IllegalInstruction;}});
850 0x6E: Trap::fnand({{fault = new IllegalInstruction;}});
851 0x6F: Trap::fnands({{fault = new IllegalInstruction;}});
852 0x70: Trap::fand({{fault = new IllegalInstruction;}});
853 0x71: Trap::fands({{fault = new IllegalInstruction;}});
854 0x72: Trap::fxnor({{fault = new IllegalInstruction;}});
855 0x73: Trap::fxnors({{fault = new IllegalInstruction;}});
856 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}});
857 0x75: BasicOperate::fsrc1s({{Frd.uw = Frs1.uw;}});
858 0x76: Trap::fornot2({{fault = new IllegalInstruction;}});
859 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}});
860 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}});
861 0x79: BasicOperate::fsrc2s({{Frd.uw = Frs2.uw;}});
862 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}});
863 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}});
864 0x7C: Trap::for({{fault = new IllegalInstruction;}});
865 0x7D: Trap::fors({{fault = new IllegalInstruction;}});
866 0x7E: Trap::fone({{fault = new IllegalInstruction;}});
867 0x7F: Trap::fones({{fault = new IllegalInstruction;}});
868 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
869 0x81: Trap::siam({{fault = new IllegalInstruction;}});
870 }
871 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
872 0x38: Branch::jmpl({{
873 Addr target = Rs1 + Rs2_or_imm13;
874 if(target & 0x3)
875 fault = new MemAddressNotAligned;
876 else
877 {
878 Rd = xc->readPC();
879 NNPC = target;
880 }
881 }});
882 0x39: Branch::return({{
883 //If both MemAddressNotAligned and
884 //a fill trap happen, it's not clear
885 //which one should be returned.
886 Addr target = Rs1 + Rs2_or_imm13;
887 if(target & 0x3)
888 fault = new MemAddressNotAligned;
889 else
890 NNPC = target;
891 if(fault == NoFault)
892 {
893 if(Canrestore == 0)
894 {
895 if(Otherwin)
896 fault = new FillNOther(Wstate<5:3>);
897 else
898 fault = new FillNNormal(Wstate<2:0>);
899 }
900 else
901 {
902 //CWP should be set directly so that it always happens
903 //Also, this will allow writing to the new window and
904 //reading from the old one
905 Cwp = (Cwp - 1 + NWindows) % NWindows;
906 Cansave = Cansave + 1;
907 Canrestore = Canrestore - 1;
908 //This is here to make sure the CWP is written
909 //no matter what. This ensures that the results
910 //are written in the new window as well.
911 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
912 }
913 }
914 }});
915 0x3A: decode CC
916 {
917 0x0: Trap::tcci({{
918 if(passesCondition(Ccr<3:0>, COND2))
919 {
920#if FULL_SYSTEM
921 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
922 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
923 fault = new TrapInstruction(lTrapNum);
924#else
925 DPRINTF(Sparc, "The syscall number is %d\n", R1);
926 xc->syscall(R1);
927#endif
928 }
929 }});
930 0x2: Trap::tccx({{
931 if(passesCondition(Ccr<7:4>, COND2))
932 {
933#if FULL_SYSTEM
934 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
935 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
936 fault = new TrapInstruction(lTrapNum);
937#else
938 DPRINTF(Sparc, "The syscall number is %d\n", R1);
939 xc->syscall(R1);
940#endif
941 }
942 }});
943 }
944 0x3B: Nop::flush({{/*Instruction memory flush*/}});
945 0x3C: save({{
946 //CWP should be set directly so that it always happens
947 //Also, this will allow writing to the new window and
948 //reading from the old one
949 if(Cansave == 0)
950 {
951 if(Otherwin)
952 fault = new SpillNOther(Wstate<5:3>);
953 else
954 fault = new SpillNNormal(Wstate<2:0>);
955 //Cwp = (Cwp + 2) % NWindows;
956 }
957 else if(Cleanwin - Canrestore == 0)
958 {
959 //Cwp = (Cwp + 1) % NWindows;
960 fault = new CleanWindow;
961 }
962 else
963 {
964 Cwp = (Cwp + 1) % NWindows;
965 Rd = Rs1 + Rs2_or_imm13;
966 Cansave = Cansave - 1;
967 Canrestore = Canrestore + 1;
968 //This is here to make sure the CWP is written
969 //no matter what. This ensures that the results
970 //are written in the new window as well.
971 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
972 }
973 }});
974 0x3D: restore({{
975 if(Canrestore == 0)
976 {
977 if(Otherwin)
978 fault = new FillNOther(Wstate<5:3>);
979 else
980 fault = new FillNNormal(Wstate<2:0>);
981 }
982 else
983 {
984 //CWP should be set directly so that it always happens
985 //Also, this will allow writing to the new window and
986 //reading from the old one
987 Cwp = (Cwp - 1 + NWindows) % NWindows;
988 Rd = Rs1 + Rs2_or_imm13;
989 Cansave = Cansave + 1;
990 Canrestore = Canrestore - 1;
991 //This is here to make sure the CWP is written
992 //no matter what. This ensures that the results
993 //are written in the new window as well.
994 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
995 }
996 }});
997 0x3E: decode FCN {
998 0x0: Priv::done({{
999 if(Tl == 0)
1000 return new IllegalInstruction;
1001
1002 Cwp = Tstate<4:0>;
1003 Pstate = Tstate<20:8>;
1004 Asi = Tstate<31:24>;
1005 Ccr = Tstate<39:32>;
1006 Gl = Tstate<42:40>;
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