1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OP default Unknown::unknown()
37{
38 0x0: decode OP2
39 {
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 //bpcc
45 0x1: decode COND2
46 {
47 //Branch Always
48 0x8: decode A
49 {
50 0x0: bpa(19, {{
51 NNPC = xc->readPC() + disp;
52 }});
53 0x1: bpa(19, {{
54 NPC = xc->readPC() + disp;
55 NNPC = NPC + 4;
56 }}, ',a');
57 }
58 //Branch Never
59 0x0: decode A
60 {
61 0x0: bpn(19, {{
62 NNPC = NNPC;//Don't do anything
63 }});
64 0x1: bpn(19, {{
65 NPC = xc->readNextPC() + 4;
66 NNPC = NPC + 4;
67 }}, ',a');
68 }
69 default: decode BPCC
70 {
71 0x0: bpcci(19, {{
72 if(passesCondition(Ccr<3:0>, COND2))
73 NNPC = xc->readPC() + disp;
74 else
75 handle_annul
76 }});
77 0x2: bpccx(19, {{
78 if(passesCondition(Ccr<7:4>, COND2))
79 NNPC = xc->readPC() + disp;
80 else
81 handle_annul
82 }});
83 }
84 }
85 //bicc
86 0x2: decode COND2
87 {
88 //Branch Always
89 0x8: decode A
90 {
91 0x0: ba(22, {{
92 NNPC = xc->readPC() + disp;
93 }});
94 0x1: ba(22, {{
95 NPC = xc->readPC() + disp;
96 NNPC = NPC + 4;
97 }}, ',a');
98 }
99 //Branch Never
100 0x0: decode A
101 {
102 0x0: bn(22, {{
103 NNPC = NNPC;//Don't do anything
104 }});
105 0x1: bn(22, {{
106 NPC = xc->readNextPC() + 4;
107 NNPC = NPC + 4;
108 }}, ',a');
109 }
110 default: bicc(22, {{
111 if(passesCondition(Ccr<3:0>, COND2))
112 NNPC = xc->readPC() + disp;
113 else
114 handle_annul
115 }});
116 }
117 }
118 0x3: decode RCOND2
119 {
120 format BranchSplit
121 {
122 0x1: bpreq({{
123 if(Rs1.sdw == 0)
124 NNPC = xc->readPC() + disp;
125 else
126 handle_annul
127 }});
128 0x2: bprle({{
129 if(Rs1.sdw <= 0)
130 NNPC = xc->readPC() + disp;
131 else
132 handle_annul
133 }});
134 0x3: bprl({{
135 if(Rs1.sdw < 0)
136 NNPC = xc->readPC() + disp;
137 else
138 handle_annul
139 }});
140 0x5: bprne({{
141 if(Rs1.sdw != 0)
142 NNPC = xc->readPC() + disp;
143 else
144 handle_annul
145 }});
146 0x6: bprg({{
147 if(Rs1.sdw > 0)
148 NNPC = xc->readPC() + disp;
149 else
150 handle_annul
151 }});
152 0x7: bprge({{
153 if(Rs1.sdw >= 0)
154 NNPC = xc->readPC() + disp;
155 else
156 handle_annul
157 }});
158 }
159 }
160 //SETHI (or NOP if rd == 0 and imm == 0)
161 0x4: SetHi::sethi({{Rd.udw = imm;}});
162 0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
163 0x6: Trap::fbfcc({{fault = new FpDisabled;}});
164 }
165 0x1: BranchN::call(30, {{
166 R15 = xc->readPC();
167 NNPC = R15 + disp;
168 }});
169 0x2: decode OP3 {
170 format IntOp {
171 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
172 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
173 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
174 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
175 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
176 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}});
177 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}});
178 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
179 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
180 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
181 0x0A: umul({{
182 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
183 Y = Rd<63:32>;
184 }});
185 0x0B: smul({{
186 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
187 Y = Rd.sdw;
188 }});
189 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
190 0x0D: udivx({{
191 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
192 else Rd.udw = Rs1.udw / Rs2_or_imm13;
193 }});
194 0x0E: udiv({{
195 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
196 else
197 {
198 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
199 if(Rd.udw >> 32 != 0)
200 Rd.udw = 0xFFFFFFFF;
201 }
202 }});
203 0x0F: sdiv({{
204 if(Rs2_or_imm13.sdw == 0)
205 fault = new DivisionByZero;
206 else
207 {
208 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
209 if(Rd.udw<63:31> != 0)
210 Rd.udw = 0x7FFFFFFF;
211 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
212 Rd.udw = 0xFFFFFFFF80000000ULL;
213 }
214 }});
215 }
216 format IntOpCc {
217 0x10: addcc({{
218 int64_t resTemp, val2 = Rs2_or_imm13;
219 Rd = resTemp = Rs1 + val2;}},
220 {{(Rs1<31:0> + val2<31:0>)<32:>}},
221 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
222 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
223 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
224 );
225 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
226 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
227 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
228 0x14: subcc({{
229 int64_t val2 = Rs2_or_imm13;
230 Rd = Rs1 - val2;}},
231 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
232 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
233 {{(~(Rs1<63:1> + (~val2)<63:1> +
234 (Rs1 | ~val2)<0:>))<63:>}},
235 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
236 );
237 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
238 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
239 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
240 0x18: addccc({{
241 int64_t resTemp, val2 = Rs2_or_imm13;
242 int64_t carryin = Ccr<0:0>;
243 Rd = resTemp = Rs1 + val2 + carryin;}},
244 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
245 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
246 {{(Rs1<63:1> + val2<63:1> +
247 ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
248 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
249 );
250 0x1A: umulcc({{
251 uint64_t resTemp;
252 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
253 Y = resTemp<63:32>;}},
254 {{0}},{{0}},{{0}},{{0}});
255 0x1B: smulcc({{
256 int64_t resTemp;
257 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>;
258 Y = resTemp<63:32>;}},
259 {{0}},{{0}},{{0}},{{0}});
260 0x1C: subccc({{
261 int64_t resTemp, val2 = Rs2_or_imm13;
262 int64_t carryin = Ccr<0:0>;
263 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
264 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
265 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
266 {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
267 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
268 );
269 0x1D: udivxcc({{
270 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
271 else Rd = Rs1.udw / Rs2_or_imm13.udw;}}
272 ,{{0}},{{0}},{{0}},{{0}});
273 0x1E: udivcc({{
274 uint32_t resTemp, val2 = Rs2_or_imm13.udw;
275 int32_t overflow = 0;
276 if(val2 == 0) fault = new DivisionByZero;
277 else
278 {
279 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
280 overflow = (resTemp<63:32> != 0);
281 if(overflow) Rd = resTemp = 0xFFFFFFFF;
282 else Rd = resTemp;
283 } }},
284 {{0}},
285 {{overflow}},
286 {{0}},
287 {{0}}
288 );
289 0x1F: sdivcc({{
290 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
291 bool overflow = false, underflow = false;
292 if(val2 == 0) fault = new DivisionByZero;
293 else
294 {
295 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
296 overflow = (Rd<63:31> != 0);
297 underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF);
298 if(overflow) Rd = 0x7FFFFFFF;
299 else if(underflow) Rd = 0xFFFFFFFF80000000ULL;
300 } }},
301 {{0}},
302 {{overflow || underflow}},
303 {{0}},
304 {{0}}
305 );
306 0x20: taddcc({{
307 int64_t resTemp, val2 = Rs2_or_imm13;
308 Rd = resTemp = Rs1 + val2;
309 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
310 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
311 {{overflow}},
312 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
313 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
314 );
315 0x21: tsubcc({{
316 int64_t resTemp, val2 = Rs2_or_imm13;
317 Rd = resTemp = Rs1 + val2;
318 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
319 {{(Rs1<31:0> + val2<31:0>)<32:0>}},
320 {{overflow}},
321 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
322 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
323 );
324 0x22: taddcctv({{
325 int64_t val2 = Rs2_or_imm13;
326 Rd = Rs1 + val2;
327 int32_t overflow = Rs1<1:0> || val2<1:0> ||
328 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
329 if(overflow) fault = new TagOverflow;}},
330 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
331 {{overflow}},
332 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
333 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}}
334 );
335 0x23: tsubcctv({{
336 int64_t resTemp, val2 = Rs2_or_imm13;
337 Rd = resTemp = Rs1 + val2;
338 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
339 if(overflow) fault = new TagOverflow;}},
340 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
341 {{overflow}},
342 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
343 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
344 );
345 0x24: mulscc({{
346 int64_t resTemp, multiplicand = Rs2_or_imm13;
347 int32_t multiplier = Rs1<31:0>;
348 int32_t savedLSB = Rs1<0:>;
349 multiplier = multiplier<31:1> |
350 ((Ccr<3:3> ^ Ccr<1:1>) << 32);
351 if(!Y<0:>)
352 multiplicand = 0;
353 Rd = resTemp = multiplicand + multiplier;
354 Y = Y<31:1> | (savedLSB << 31);}},
355 {{((multiplicand<31:0> + multiplier<31:0>)<32:0>)}},
356 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
357 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
358 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
359 );
360 }
361 format IntOp
362 {
363 0x25: decode X {
364 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
365 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
366 }
367 0x26: decode X {
368 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
369 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
370 }
371 0x27: decode X {
372 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
373 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
374 }
375 0x28: decode RS1 {
376 0x00: NoPriv::rdy({{Rd = Y;}});
377 //1 should cause an illegal instruction exception
378 0x02: NoPriv::rdccr({{Rd = Ccr;}});
379 0x03: NoPriv::rdasi({{Rd = Asi;}});
| 1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OP default Unknown::unknown()
37{
38 0x0: decode OP2
39 {
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 //bpcc
45 0x1: decode COND2
46 {
47 //Branch Always
48 0x8: decode A
49 {
50 0x0: bpa(19, {{
51 NNPC = xc->readPC() + disp;
52 }});
53 0x1: bpa(19, {{
54 NPC = xc->readPC() + disp;
55 NNPC = NPC + 4;
56 }}, ',a');
57 }
58 //Branch Never
59 0x0: decode A
60 {
61 0x0: bpn(19, {{
62 NNPC = NNPC;//Don't do anything
63 }});
64 0x1: bpn(19, {{
65 NPC = xc->readNextPC() + 4;
66 NNPC = NPC + 4;
67 }}, ',a');
68 }
69 default: decode BPCC
70 {
71 0x0: bpcci(19, {{
72 if(passesCondition(Ccr<3:0>, COND2))
73 NNPC = xc->readPC() + disp;
74 else
75 handle_annul
76 }});
77 0x2: bpccx(19, {{
78 if(passesCondition(Ccr<7:4>, COND2))
79 NNPC = xc->readPC() + disp;
80 else
81 handle_annul
82 }});
83 }
84 }
85 //bicc
86 0x2: decode COND2
87 {
88 //Branch Always
89 0x8: decode A
90 {
91 0x0: ba(22, {{
92 NNPC = xc->readPC() + disp;
93 }});
94 0x1: ba(22, {{
95 NPC = xc->readPC() + disp;
96 NNPC = NPC + 4;
97 }}, ',a');
98 }
99 //Branch Never
100 0x0: decode A
101 {
102 0x0: bn(22, {{
103 NNPC = NNPC;//Don't do anything
104 }});
105 0x1: bn(22, {{
106 NPC = xc->readNextPC() + 4;
107 NNPC = NPC + 4;
108 }}, ',a');
109 }
110 default: bicc(22, {{
111 if(passesCondition(Ccr<3:0>, COND2))
112 NNPC = xc->readPC() + disp;
113 else
114 handle_annul
115 }});
116 }
117 }
118 0x3: decode RCOND2
119 {
120 format BranchSplit
121 {
122 0x1: bpreq({{
123 if(Rs1.sdw == 0)
124 NNPC = xc->readPC() + disp;
125 else
126 handle_annul
127 }});
128 0x2: bprle({{
129 if(Rs1.sdw <= 0)
130 NNPC = xc->readPC() + disp;
131 else
132 handle_annul
133 }});
134 0x3: bprl({{
135 if(Rs1.sdw < 0)
136 NNPC = xc->readPC() + disp;
137 else
138 handle_annul
139 }});
140 0x5: bprne({{
141 if(Rs1.sdw != 0)
142 NNPC = xc->readPC() + disp;
143 else
144 handle_annul
145 }});
146 0x6: bprg({{
147 if(Rs1.sdw > 0)
148 NNPC = xc->readPC() + disp;
149 else
150 handle_annul
151 }});
152 0x7: bprge({{
153 if(Rs1.sdw >= 0)
154 NNPC = xc->readPC() + disp;
155 else
156 handle_annul
157 }});
158 }
159 }
160 //SETHI (or NOP if rd == 0 and imm == 0)
161 0x4: SetHi::sethi({{Rd.udw = imm;}});
162 0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
163 0x6: Trap::fbfcc({{fault = new FpDisabled;}});
164 }
165 0x1: BranchN::call(30, {{
166 R15 = xc->readPC();
167 NNPC = R15 + disp;
168 }});
169 0x2: decode OP3 {
170 format IntOp {
171 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
172 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
173 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
174 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
175 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
176 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}});
177 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}});
178 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
179 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
180 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
181 0x0A: umul({{
182 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
183 Y = Rd<63:32>;
184 }});
185 0x0B: smul({{
186 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
187 Y = Rd.sdw;
188 }});
189 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
190 0x0D: udivx({{
191 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
192 else Rd.udw = Rs1.udw / Rs2_or_imm13;
193 }});
194 0x0E: udiv({{
195 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
196 else
197 {
198 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
199 if(Rd.udw >> 32 != 0)
200 Rd.udw = 0xFFFFFFFF;
201 }
202 }});
203 0x0F: sdiv({{
204 if(Rs2_or_imm13.sdw == 0)
205 fault = new DivisionByZero;
206 else
207 {
208 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
209 if(Rd.udw<63:31> != 0)
210 Rd.udw = 0x7FFFFFFF;
211 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
212 Rd.udw = 0xFFFFFFFF80000000ULL;
213 }
214 }});
215 }
216 format IntOpCc {
217 0x10: addcc({{
218 int64_t resTemp, val2 = Rs2_or_imm13;
219 Rd = resTemp = Rs1 + val2;}},
220 {{(Rs1<31:0> + val2<31:0>)<32:>}},
221 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
222 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
223 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
224 );
225 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
226 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
227 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
228 0x14: subcc({{
229 int64_t val2 = Rs2_or_imm13;
230 Rd = Rs1 - val2;}},
231 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
232 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
233 {{(~(Rs1<63:1> + (~val2)<63:1> +
234 (Rs1 | ~val2)<0:>))<63:>}},
235 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
236 );
237 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
238 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
239 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
240 0x18: addccc({{
241 int64_t resTemp, val2 = Rs2_or_imm13;
242 int64_t carryin = Ccr<0:0>;
243 Rd = resTemp = Rs1 + val2 + carryin;}},
244 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
245 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
246 {{(Rs1<63:1> + val2<63:1> +
247 ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
248 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
249 );
250 0x1A: umulcc({{
251 uint64_t resTemp;
252 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
253 Y = resTemp<63:32>;}},
254 {{0}},{{0}},{{0}},{{0}});
255 0x1B: smulcc({{
256 int64_t resTemp;
257 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>;
258 Y = resTemp<63:32>;}},
259 {{0}},{{0}},{{0}},{{0}});
260 0x1C: subccc({{
261 int64_t resTemp, val2 = Rs2_or_imm13;
262 int64_t carryin = Ccr<0:0>;
263 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
264 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
265 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
266 {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
267 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
268 );
269 0x1D: udivxcc({{
270 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
271 else Rd = Rs1.udw / Rs2_or_imm13.udw;}}
272 ,{{0}},{{0}},{{0}},{{0}});
273 0x1E: udivcc({{
274 uint32_t resTemp, val2 = Rs2_or_imm13.udw;
275 int32_t overflow = 0;
276 if(val2 == 0) fault = new DivisionByZero;
277 else
278 {
279 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
280 overflow = (resTemp<63:32> != 0);
281 if(overflow) Rd = resTemp = 0xFFFFFFFF;
282 else Rd = resTemp;
283 } }},
284 {{0}},
285 {{overflow}},
286 {{0}},
287 {{0}}
288 );
289 0x1F: sdivcc({{
290 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
291 bool overflow = false, underflow = false;
292 if(val2 == 0) fault = new DivisionByZero;
293 else
294 {
295 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
296 overflow = (Rd<63:31> != 0);
297 underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF);
298 if(overflow) Rd = 0x7FFFFFFF;
299 else if(underflow) Rd = 0xFFFFFFFF80000000ULL;
300 } }},
301 {{0}},
302 {{overflow || underflow}},
303 {{0}},
304 {{0}}
305 );
306 0x20: taddcc({{
307 int64_t resTemp, val2 = Rs2_or_imm13;
308 Rd = resTemp = Rs1 + val2;
309 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
310 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
311 {{overflow}},
312 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
313 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
314 );
315 0x21: tsubcc({{
316 int64_t resTemp, val2 = Rs2_or_imm13;
317 Rd = resTemp = Rs1 + val2;
318 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
319 {{(Rs1<31:0> + val2<31:0>)<32:0>}},
320 {{overflow}},
321 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
322 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
323 );
324 0x22: taddcctv({{
325 int64_t val2 = Rs2_or_imm13;
326 Rd = Rs1 + val2;
327 int32_t overflow = Rs1<1:0> || val2<1:0> ||
328 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
329 if(overflow) fault = new TagOverflow;}},
330 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
331 {{overflow}},
332 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
333 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}}
334 );
335 0x23: tsubcctv({{
336 int64_t resTemp, val2 = Rs2_or_imm13;
337 Rd = resTemp = Rs1 + val2;
338 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
339 if(overflow) fault = new TagOverflow;}},
340 {{((Rs1<31:0> + val2<31:0>)<32:0>)}},
341 {{overflow}},
342 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
343 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
344 );
345 0x24: mulscc({{
346 int64_t resTemp, multiplicand = Rs2_or_imm13;
347 int32_t multiplier = Rs1<31:0>;
348 int32_t savedLSB = Rs1<0:>;
349 multiplier = multiplier<31:1> |
350 ((Ccr<3:3> ^ Ccr<1:1>) << 32);
351 if(!Y<0:>)
352 multiplicand = 0;
353 Rd = resTemp = multiplicand + multiplier;
354 Y = Y<31:1> | (savedLSB << 31);}},
355 {{((multiplicand<31:0> + multiplier<31:0>)<32:0>)}},
356 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
357 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
358 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
359 );
360 }
361 format IntOp
362 {
363 0x25: decode X {
364 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
365 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
366 }
367 0x26: decode X {
368 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
369 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
370 }
371 0x27: decode X {
372 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
373 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
374 }
375 0x28: decode RS1 {
376 0x00: NoPriv::rdy({{Rd = Y;}});
377 //1 should cause an illegal instruction exception
378 0x02: NoPriv::rdccr({{Rd = Ccr;}});
379 0x03: NoPriv::rdasi({{Rd = Asi;}});
|
380 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
| 380 0x04: PrivCheck::rdtick(
381 {{ Rd = xc->readMiscRegWithEffect(MISCREG_TICK);}},
382 {{Tick<63:>}});
|
381 0x05: NoPriv::rdpc({{
382 if(Pstate<3:>)
383 Rd = (xc->readPC())<31:0>;
384 else
385 Rd = xc->readPC();}});
386 0x06: NoPriv::rdfprs({{
387 //Wait for all fpops to finish.
388 Rd = Fprs;
389 }});
390 //7-14 should cause an illegal instruction exception
391 0x0F: decode I {
392 0x0: Nop::stbar({{/*stuff*/}});
393 0x1: Nop::membar({{/*stuff*/}});
394 }
395 0x10: Priv::rdpcr({{Rd = Pcr;}});
396 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
397 //0x12 should cause an illegal instruction exception
398 0x13: NoPriv::rdgsr({{
399 if(Fprs<2:> == 0 || Pstate<4:> == 0)
400 Rd = Gsr;
401 else
402 fault = new FpDisabled;
403 }});
404 //0x14-0x15 should cause an illegal instruction exception
405 0x16: Priv::rdsoftint({{Rd = Softint;}});
| 383 0x05: NoPriv::rdpc({{
384 if(Pstate<3:>)
385 Rd = (xc->readPC())<31:0>;
386 else
387 Rd = xc->readPC();}});
388 0x06: NoPriv::rdfprs({{
389 //Wait for all fpops to finish.
390 Rd = Fprs;
391 }});
392 //7-14 should cause an illegal instruction exception
393 0x0F: decode I {
394 0x0: Nop::stbar({{/*stuff*/}});
395 0x1: Nop::membar({{/*stuff*/}});
396 }
397 0x10: Priv::rdpcr({{Rd = Pcr;}});
398 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
399 //0x12 should cause an illegal instruction exception
400 0x13: NoPriv::rdgsr({{
401 if(Fprs<2:> == 0 || Pstate<4:> == 0)
402 Rd = Gsr;
403 else
404 fault = new FpDisabled;
405 }});
406 //0x14-0x15 should cause an illegal instruction exception
407 0x16: Priv::rdsoftint({{Rd = Softint;}});
|
406 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
407 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}});
408 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
| 408 0x17: Priv::rdtick_cmpr({{
409 Rd = xc->readMiscRegWithEffect(MISCREG_TICK_CMPR);
410 }});
411 0x18: PrivCheck::rdstick({{
412 Rd = xc->readMiscRegWithEffect(MISCREG_STICK);
413 }}, {{Stick<63:>}});
414 0x19: Priv::rdstick_cmpr({{
415 Rd = xc->readMiscRegWithEffect(MISCREG_STICK_CMPR);
416 }});
|
409 0x1A: Priv::rdstrand_sts_reg({{
410 if(Pstate<2:> && !Hpstate<2:>)
411 Rd = StrandStsReg<0:>;
412 else
413 Rd = StrandStsReg;
414 }});
415 //0x1A is supposed to be reserved, but it reads the strand
416 //status register.
417 //0x1B-0x1F should cause an illegal instruction exception
418 }
419 0x29: decode RS1 {
420 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
421 0x01: HPriv::rdhprhtstate({{
422 if(Tl == 0)
423 return new IllegalInstruction;
424 Rd = Htstate;
425 }});
426 //0x02 should cause an illegal instruction exception
427 0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
428 //0x04 should cause an illegal instruction exception
429 0x05: HPriv::rdhprhtba({{Rd = Htba;}});
430 0x06: HPriv::rdhprhver({{Rd = Hver;}});
431 //0x07-0x1E should cause an illegal instruction exception
| 417 0x1A: Priv::rdstrand_sts_reg({{
418 if(Pstate<2:> && !Hpstate<2:>)
419 Rd = StrandStsReg<0:>;
420 else
421 Rd = StrandStsReg;
422 }});
423 //0x1A is supposed to be reserved, but it reads the strand
424 //status register.
425 //0x1B-0x1F should cause an illegal instruction exception
426 }
427 0x29: decode RS1 {
428 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
429 0x01: HPriv::rdhprhtstate({{
430 if(Tl == 0)
431 return new IllegalInstruction;
432 Rd = Htstate;
433 }});
434 //0x02 should cause an illegal instruction exception
435 0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
436 //0x04 should cause an illegal instruction exception
437 0x05: HPriv::rdhprhtba({{Rd = Htba;}});
438 0x06: HPriv::rdhprhver({{Rd = Hver;}});
439 //0x07-0x1E should cause an illegal instruction exception
|
432 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
| 440 0x1F: HPriv::rdhprhstick_cmpr({{
441 Rd = xc->readMiscRegWithEffect(MISCREG_HSTICK_CMPR);
442 }});
|
433 }
434 0x2A: decode RS1 {
435 0x00: Priv::rdprtpc({{
436 if(Tl == 0)
437 return new IllegalInstruction;
438 Rd = Tpc;
439 }});
440 0x01: Priv::rdprtnpc({{
441 if(Tl == 0)
442 return new IllegalInstruction;
443 Rd = Tnpc;
444 }});
445 0x02: Priv::rdprtstate({{
446 if(Tl == 0)
447 return new IllegalInstruction;
448 Rd = Tstate;
449 }});
450 0x03: Priv::rdprtt({{
451 if(Tl == 0)
452 return new IllegalInstruction;
453 Rd = Tt;
454 }});
| 443 }
444 0x2A: decode RS1 {
445 0x00: Priv::rdprtpc({{
446 if(Tl == 0)
447 return new IllegalInstruction;
448 Rd = Tpc;
449 }});
450 0x01: Priv::rdprtnpc({{
451 if(Tl == 0)
452 return new IllegalInstruction;
453 Rd = Tnpc;
454 }});
455 0x02: Priv::rdprtstate({{
456 if(Tl == 0)
457 return new IllegalInstruction;
458 Rd = Tstate;
459 }});
460 0x03: Priv::rdprtt({{
461 if(Tl == 0)
462 return new IllegalInstruction;
463 Rd = Tt;
464 }});
|
455 0x04: Priv::rdprtick({{Rd = Tick;}});
| 465 0x04: Priv::rdprtick({{
466 Rd = xc->readMiscRegWithEffect(MISCREG_TICK);
467 }});
|
456 0x05: Priv::rdprtba({{Rd = Tba;}});
457 0x06: Priv::rdprpstate({{Rd = Pstate;}});
458 0x07: Priv::rdprtl({{Rd = Tl;}});
459 0x08: Priv::rdprpil({{Rd = Pil;}});
460 0x09: Priv::rdprcwp({{Rd = Cwp;}});
461 0x0A: Priv::rdprcansave({{Rd = Cansave;}});
462 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});
463 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});
464 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}});
465 0x0E: Priv::rdprwstate({{Rd = Wstate;}});
466 //0x0F should cause an illegal instruction exception
467 0x10: Priv::rdprgl({{Rd = Gl;}});
468 //0x11-0x1F should cause an illegal instruction exception
469 }
470 0x2B: BasicOperate::flushw({{
471 if(NWindows - 2 - Cansave == 0)
472 {
473 if(Otherwin)
474 fault = new SpillNOther(Wstate<5:3>);
475 else
476 fault = new SpillNNormal(Wstate<2:0>);
477 }
478 }});
479 0x2C: decode MOVCC3
480 {
481 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
482 0x1: decode CC
483 {
484 0x0: movcci({{
485 if(passesCondition(Ccr<3:0>, COND4))
486 Rd = Rs2_or_imm11;
487 else
488 Rd = Rd;
489 }});
490 0x2: movccx({{
491 if(passesCondition(Ccr<7:4>, COND4))
492 Rd = Rs2_or_imm11;
493 else
494 Rd = Rd;
495 }});
496 }
497 }
498 0x2D: sdivx({{
499 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
500 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
501 }});
502 0x2E: decode RS1 {
503 0x0: IntOp::popc({{
504 int64_t count = 0;
505 uint64_t temp = Rs2_or_imm13;
506 //Count the 1s in the front 4bits until none are left
507 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
508 while(temp)
509 {
510 count += oneBits[temp & 0xF];
511 temp = temp >> 4;
512 }
513 Rd = count;
514 }});
515 }
516 0x2F: decode RCOND3
517 {
518 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
519 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
520 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
521 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
522 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
523 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
524 }
525 0x30: decode RD {
526 0x00: NoPriv::wry({{Y = Rs1 ^ Rs2_or_imm13;}});
527 //0x01 should cause an illegal instruction exception
528 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
529 0x03: NoPriv::wrasi({{Ccr = Rs1 ^ Rs2_or_imm13;}});
530 //0x04-0x05 should cause an illegal instruction exception
531 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
532 //0x07-0x0E should cause an illegal instruction exception
533 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
534 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
535 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
536 //0x12 should cause an illegal instruction exception
537 0x13: NoPriv::wrgsr({{
538 if(Fprs<2:> == 0 || Pstate<4:> == 0)
539 return new FpDisabled;
540 Gsr = Rs1 ^ Rs2_or_imm13;
541 }});
542 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
543 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});
544 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
| 468 0x05: Priv::rdprtba({{Rd = Tba;}});
469 0x06: Priv::rdprpstate({{Rd = Pstate;}});
470 0x07: Priv::rdprtl({{Rd = Tl;}});
471 0x08: Priv::rdprpil({{Rd = Pil;}});
472 0x09: Priv::rdprcwp({{Rd = Cwp;}});
473 0x0A: Priv::rdprcansave({{Rd = Cansave;}});
474 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});
475 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});
476 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}});
477 0x0E: Priv::rdprwstate({{Rd = Wstate;}});
478 //0x0F should cause an illegal instruction exception
479 0x10: Priv::rdprgl({{Rd = Gl;}});
480 //0x11-0x1F should cause an illegal instruction exception
481 }
482 0x2B: BasicOperate::flushw({{
483 if(NWindows - 2 - Cansave == 0)
484 {
485 if(Otherwin)
486 fault = new SpillNOther(Wstate<5:3>);
487 else
488 fault = new SpillNNormal(Wstate<2:0>);
489 }
490 }});
491 0x2C: decode MOVCC3
492 {
493 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
494 0x1: decode CC
495 {
496 0x0: movcci({{
497 if(passesCondition(Ccr<3:0>, COND4))
498 Rd = Rs2_or_imm11;
499 else
500 Rd = Rd;
501 }});
502 0x2: movccx({{
503 if(passesCondition(Ccr<7:4>, COND4))
504 Rd = Rs2_or_imm11;
505 else
506 Rd = Rd;
507 }});
508 }
509 }
510 0x2D: sdivx({{
511 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
512 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
513 }});
514 0x2E: decode RS1 {
515 0x0: IntOp::popc({{
516 int64_t count = 0;
517 uint64_t temp = Rs2_or_imm13;
518 //Count the 1s in the front 4bits until none are left
519 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
520 while(temp)
521 {
522 count += oneBits[temp & 0xF];
523 temp = temp >> 4;
524 }
525 Rd = count;
526 }});
527 }
528 0x2F: decode RCOND3
529 {
530 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
531 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
532 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
533 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
534 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
535 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
536 }
537 0x30: decode RD {
538 0x00: NoPriv::wry({{Y = Rs1 ^ Rs2_or_imm13;}});
539 //0x01 should cause an illegal instruction exception
540 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
541 0x03: NoPriv::wrasi({{Ccr = Rs1 ^ Rs2_or_imm13;}});
542 //0x04-0x05 should cause an illegal instruction exception
543 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
544 //0x07-0x0E should cause an illegal instruction exception
545 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
546 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
547 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
548 //0x12 should cause an illegal instruction exception
549 0x13: NoPriv::wrgsr({{
550 if(Fprs<2:> == 0 || Pstate<4:> == 0)
551 return new FpDisabled;
552 Gsr = Rs1 ^ Rs2_or_imm13;
553 }});
554 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
555 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});
556 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
|
545 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}});
| 557 0x17: Priv::wrtick_cmpr({{
558 xc->setMiscRegWithEffect(MISCREG_TICK_CMPR, Rs1 ^ Rs2_or_imm13);
559 }});
|
546 0x18: NoPriv::wrstick({{
547 if(!Hpstate<2:>)
548 return new IllegalInstruction;
| 560 0x18: NoPriv::wrstick({{
561 if(!Hpstate<2:>)
562 return new IllegalInstruction;
|
549 Stick = Rs1 ^ Rs2_or_imm13;
| 563 xc->setMiscRegWithEffect(MISCREG_STICK, Rs1 ^ Rs2_or_imm13);
|
550 }});
| 564 }});
|
551 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}});
| 565 0x19: Priv::wrstick_cmpr({{
566 xc->setMiscRegWithEffect(MISCREG_STICK_CMPR, Rs1 ^ Rs2_or_imm13);
567 }});
|
552 0x1A: Priv::wrstrand_sts_reg({{
553 if(Pstate<2:> && !Hpstate<2:>)
554 StrandStsReg = StrandStsReg<63:1> |
555 (Rs1 ^ Rs2_or_imm13)<0:>;
556 else
557 StrandStsReg = Rs1 ^ Rs2_or_imm13;
558 }});
559 //0x1A is supposed to be reserved, but it writes the strand
560 //status register.
561 //0x1B-0x1F should cause an illegal instruction exception
562 }
563 0x31: decode FCN {
564 0x0: Priv::saved({{
565 assert(Cansave < NWindows - 2);
566 assert(Otherwin || Canrestore);
567 Cansave = Cansave + 1;
568 if(Otherwin == 0)
569 Canrestore = Canrestore - 1;
570 else
571 Otherwin = Otherwin - 1;
572 }});
573 0x1: Priv::restored({{
574 assert(Cansave || Otherwin);
575 assert(Canrestore < NWindows - 2);
576 Canrestore = Canrestore + 1;
577 if(Otherwin == 0)
578 Cansave = Cansave - 1;
579 else
580 Otherwin = Otherwin - 1;
581 }});
582 }
583 0x32: decode RD {
584 0x00: Priv::wrprtpc({{
585 if(Tl == 0)
586 return new IllegalInstruction;
587 else
588 Tpc = Rs1 ^ Rs2_or_imm13;
589 }});
590 0x01: Priv::wrprtnpc({{
591 if(Tl == 0)
592 return new IllegalInstruction;
593 else
594 Tnpc = Rs1 ^ Rs2_or_imm13;
595 }});
596 0x02: Priv::wrprtstate({{
597 if(Tl == 0)
598 return new IllegalInstruction;
599 else
600 Tstate = Rs1 ^ Rs2_or_imm13;
601 }});
602 0x03: Priv::wrprtt({{
603 if(Tl == 0)
604 return new IllegalInstruction;
605 else
606 Tt = Rs1 ^ Rs2_or_imm13;
607 }});
| 568 0x1A: Priv::wrstrand_sts_reg({{
569 if(Pstate<2:> && !Hpstate<2:>)
570 StrandStsReg = StrandStsReg<63:1> |
571 (Rs1 ^ Rs2_or_imm13)<0:>;
572 else
573 StrandStsReg = Rs1 ^ Rs2_or_imm13;
574 }});
575 //0x1A is supposed to be reserved, but it writes the strand
576 //status register.
577 //0x1B-0x1F should cause an illegal instruction exception
578 }
579 0x31: decode FCN {
580 0x0: Priv::saved({{
581 assert(Cansave < NWindows - 2);
582 assert(Otherwin || Canrestore);
583 Cansave = Cansave + 1;
584 if(Otherwin == 0)
585 Canrestore = Canrestore - 1;
586 else
587 Otherwin = Otherwin - 1;
588 }});
589 0x1: Priv::restored({{
590 assert(Cansave || Otherwin);
591 assert(Canrestore < NWindows - 2);
592 Canrestore = Canrestore + 1;
593 if(Otherwin == 0)
594 Cansave = Cansave - 1;
595 else
596 Otherwin = Otherwin - 1;
597 }});
598 }
599 0x32: decode RD {
600 0x00: Priv::wrprtpc({{
601 if(Tl == 0)
602 return new IllegalInstruction;
603 else
604 Tpc = Rs1 ^ Rs2_or_imm13;
605 }});
606 0x01: Priv::wrprtnpc({{
607 if(Tl == 0)
608 return new IllegalInstruction;
609 else
610 Tnpc = Rs1 ^ Rs2_or_imm13;
611 }});
612 0x02: Priv::wrprtstate({{
613 if(Tl == 0)
614 return new IllegalInstruction;
615 else
616 Tstate = Rs1 ^ Rs2_or_imm13;
617 }});
618 0x03: Priv::wrprtt({{
619 if(Tl == 0)
620 return new IllegalInstruction;
621 else
622 Tt = Rs1 ^ Rs2_or_imm13;
623 }});
|
608 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
| 624 0x04: HPriv::wrprtick({{
625 xc->setMiscRegWithEffect(MISCREG_TICK, Rs1 ^ Rs2_or_imm13);
626 }});
|
609 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
610 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
611 0x07: Priv::wrprtl({{
612 if(Pstate<2:> && !Hpstate<2:>)
613 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
614 else
615 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);
616 }});
617 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
618 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
619 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
620 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
621 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
622 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
623 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
624 //0x0F should cause an illegal instruction exception
625 0x10: Priv::wrprgl({{
626 if(Pstate<2:> && !Hpstate<2:>)
627 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL);
628 else
629 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
630 }});
631 //0x11-0x1F should cause an illegal instruction exception
632 }
633 0x33: decode RD {
634 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
635 0x01: HPriv::wrhprhtstate({{
636 if(Tl == 0)
637 return new IllegalInstruction;
638 Htstate = Rs1 ^ Rs2_or_imm13;
639 }});
640 //0x02 should cause an illegal instruction exception
641 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
642 //0x04 should cause an illegal instruction exception
643 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
644 //0x06-0x01D should cause an illegal instruction exception
| 627 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
628 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
629 0x07: Priv::wrprtl({{
630 if(Pstate<2:> && !Hpstate<2:>)
631 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
632 else
633 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);
634 }});
635 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
636 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
637 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
638 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
639 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
640 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
641 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
642 //0x0F should cause an illegal instruction exception
643 0x10: Priv::wrprgl({{
644 if(Pstate<2:> && !Hpstate<2:>)
645 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL);
646 else
647 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
648 }});
649 //0x11-0x1F should cause an illegal instruction exception
650 }
651 0x33: decode RD {
652 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
653 0x01: HPriv::wrhprhtstate({{
654 if(Tl == 0)
655 return new IllegalInstruction;
656 Htstate = Rs1 ^ Rs2_or_imm13;
657 }});
658 //0x02 should cause an illegal instruction exception
659 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
660 //0x04 should cause an illegal instruction exception
661 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
662 //0x06-0x01D should cause an illegal instruction exception
|
645 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
| 663 0x1F: HPriv::wrhprhstick_cmpr({{
664 xc->setMiscRegWithEffect(MISCREG_HSTICK_CMPR, Rs1 ^ Rs2_or_imm13);
665 }});
|
646 }
647 0x34: decode OPF{
648 format BasicOperate{
649 0x01: fmovs({{
650 Frds.uw = Frs2s.uw;
651 //fsr.ftt = fsr.cexc = 0
652 Fsr &= ~(7 << 14);
653 Fsr &= ~(0x1F);
654 }});
655 0x02: fmovd({{
656 Frd.udw = Frs2.udw;
657 //fsr.ftt = fsr.cexc = 0
658 Fsr &= ~(7 << 14);
659 Fsr &= ~(0x1F);
660 }});
661 0x03: Trap::fmovq({{fault = new FpDisabled;}});
662 0x05: fnegs({{
663 Frds.uw = Frs2s.uw ^ (1UL << 31);
664 //fsr.ftt = fsr.cexc = 0
665 Fsr &= ~(7 << 14);
666 Fsr &= ~(0x1F);
667 }});
668 0x06: fnegd({{
669 Frd.udw = Frs2.udw ^ (1ULL << 63);
670 //fsr.ftt = fsr.cexc = 0
671 Fsr &= ~(7 << 14);
672 Fsr &= ~(0x1F);
673 }});
674 0x07: Trap::fnegq({{fault = new FpDisabled;}});
675 0x09: fabss({{
676 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;
677 //fsr.ftt = fsr.cexc = 0
678 Fsr &= ~(7 << 14);
679 Fsr &= ~(0x1F);
680 }});
681 0x0A: fabsd({{
682 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;
683 //fsr.ftt = fsr.cexc = 0
684 Fsr &= ~(7 << 14);
685 Fsr &= ~(0x1F);
686 }});
687 0x0B: Trap::fabsq({{fault = new FpDisabled;}});
688 0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}});
689 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}});
690 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
691 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
692 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
693 0x43: Trap::faddq({{fault = new FpDisabled;}});
694 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
695 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
696 0x47: Trap::fsubq({{fault = new FpDisabled;}});
697 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
698 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
699 0x4B: Trap::fmulq({{fault = new FpDisabled;}});
700 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
701 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
702 0x4F: Trap::fdivq({{fault = new FpDisabled;}});
703 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
704 0x6E: Trap::fdmulq({{fault = new FpDisabled;}});
705 0x81: fstox({{
706 Frd.df = (double)static_cast<int64_t>(Frs2s.sf);
707 }});
708 0x82: fdtox({{
709 Frd.df = (double)static_cast<int64_t>(Frs2.df);
710 }});
711 0x83: Trap::fqtox({{fault = new FpDisabled;}});
712 0x84: fxtos({{
713 Frds.sf = static_cast<float>((int64_t)Frs2.df);
714 }});
715 0x88: fxtod({{
716 Frd.df = static_cast<double>((int64_t)Frs2.df);
717 }});
718 0x8C: Trap::fxtoq({{fault = new FpDisabled;}});
719 0xC4: fitos({{
720 Frds.sf = static_cast<float>((int32_t)Frs2s.sf);
721 }});
722 0xC6: fdtos({{Frds.sf = Frs2.df;}});
723 0xC7: Trap::fqtos({{fault = new FpDisabled;}});
724 0xC8: fitod({{
725 Frd.df = static_cast<double>((int32_t)Frs2s.sf);
726 }});
727 0xC9: fstod({{Frd.df = Frs2s.sf;}});
728 0xCB: Trap::fqtod({{fault = new FpDisabled;}});
729 0xCC: Trap::fitoq({{fault = new FpDisabled;}});
730 0xCD: Trap::fstoq({{fault = new FpDisabled;}});
731 0xCE: Trap::fdtoq({{fault = new FpDisabled;}});
732 0xD1: fstoi({{
733 Frds.sf = (float)static_cast<int32_t>(Frs2s.sf);
734 }});
735 0xD2: fdtoi({{
736 Frds.sf = (float)static_cast<int32_t>(Frs2.df);
737 }});
738 0xD3: Trap::fqtoi({{fault = new FpDisabled;}});
739 default: Trap::fpop1({{fault = new FpDisabled;}});
740 }
741 }
742 0x35: Trap::fpop2({{fault = new FpDisabled;}});
743 //This used to be just impdep1, but now it's a whole bunch
744 //of instructions
745 0x36: decode OPF{
746 0x00: Trap::edge8({{fault = new IllegalInstruction;}});
747 0x01: Trap::edge8n({{fault = new IllegalInstruction;}});
748 0x02: Trap::edge8l({{fault = new IllegalInstruction;}});
749 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}});
750 0x04: Trap::edge16({{fault = new IllegalInstruction;}});
751 0x05: Trap::edge16n({{fault = new IllegalInstruction;}});
752 0x06: Trap::edge16l({{fault = new IllegalInstruction;}});
753 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}});
754 0x08: Trap::edge32({{fault = new IllegalInstruction;}});
755 0x09: Trap::edge32n({{fault = new IllegalInstruction;}});
756 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}});
757 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}});
758 0x10: Trap::array8({{fault = new IllegalInstruction;}});
759 0x12: Trap::array16({{fault = new IllegalInstruction;}});
760 0x14: Trap::array32({{fault = new IllegalInstruction;}});
761 0x18: BasicOperate::alignaddr({{
762 uint64_t sum = Rs1 + Rs2;
763 Rd = sum & ~7;
764 Gsr = (Gsr & ~7) | (sum & 7);
765 }});
766 0x19: Trap::bmask({{fault = new IllegalInstruction;}});
767 0x1A: BasicOperate::alignaddresslittle({{
768 uint64_t sum = Rs1 + Rs2;
769 Rd = sum & ~7;
770 Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
771 }});
772 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}});
773 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}});
774 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}});
775 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}});
776 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}});
777 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}});
778 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}});
779 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}});
780 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}});
781 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}});
782 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}});
783 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}});
784 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}});
785 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}});
786 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}});
787 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
788 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
789 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
790 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
791 0x48: BasicOperate::faligndata({{
792 uint64_t msbX = Frs1.udw;
793 uint64_t lsbX = Frs2.udw;
794 //Some special cases need to be split out, first
795 //because they're the most likely to be used, and
796 //second because otherwise, we end up shifting by
797 //greater than the width of the type being shifted,
798 //namely 64, which produces undefined results according
799 //to the C standard.
800 switch(Gsr<2:0>)
801 {
802 case 0:
803 Frd.udw = msbX;
804 break;
805 case 8:
806 Frd.udw = lsbX;
807 break;
808 default:
809 uint64_t msbShift = Gsr<2:0> * 8;
810 uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
811 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
812 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
813 Frd.udw = ((msbX & msbMask) << msbShift) |
814 ((lsbX & lsbMask) >> lsbShift);
815 }
816 }});
817 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
818 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}});
819 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}});
820 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}});
821 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}});
822 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}});
823 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}});
824 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}});
825 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}});
826 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}});
827 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}});
828 0x60: BasicOperate::fzero({{Frd.df = 0;}});
829 0x61: BasicOperate::fzeros({{Frds.sf = 0;}});
830 0x62: Trap::fnor({{fault = new IllegalInstruction;}});
831 0x63: Trap::fnors({{fault = new IllegalInstruction;}});
832 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}});
833 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}});
834 0x66: BasicOperate::fnot2({{
835 Frd.df = (double)(~((uint64_t)Frs2.df));
836 }});
837 0x67: BasicOperate::fnot2s({{
838 Frds.sf = (float)(~((uint32_t)Frs2s.sf));
839 }});
840 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}});
841 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}});
842 0x6A: BasicOperate::fnot1({{
843 Frd.df = (double)(~((uint64_t)Frs1.df));
844 }});
845 0x6B: BasicOperate::fnot1s({{
846 Frds.sf = (float)(~((uint32_t)Frs1s.sf));
847 }});
848 0x6C: Trap::fxor({{fault = new IllegalInstruction;}});
849 0x6D: Trap::fxors({{fault = new IllegalInstruction;}});
850 0x6E: Trap::fnand({{fault = new IllegalInstruction;}});
851 0x6F: Trap::fnands({{fault = new IllegalInstruction;}});
852 0x70: Trap::fand({{fault = new IllegalInstruction;}});
853 0x71: Trap::fands({{fault = new IllegalInstruction;}});
854 0x72: Trap::fxnor({{fault = new IllegalInstruction;}});
855 0x73: Trap::fxnors({{fault = new IllegalInstruction;}});
856 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}});
857 0x75: BasicOperate::fsrc1s({{Frd.uw = Frs1.uw;}});
858 0x76: Trap::fornot2({{fault = new IllegalInstruction;}});
859 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}});
860 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}});
861 0x79: BasicOperate::fsrc2s({{Frd.uw = Frs2.uw;}});
862 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}});
863 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}});
864 0x7C: Trap::for({{fault = new IllegalInstruction;}});
865 0x7D: Trap::fors({{fault = new IllegalInstruction;}});
866 0x7E: Trap::fone({{fault = new IllegalInstruction;}});
867 0x7F: Trap::fones({{fault = new IllegalInstruction;}});
868 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
869 0x81: Trap::siam({{fault = new IllegalInstruction;}});
870 }
871 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
872 0x38: Branch::jmpl({{
873 Addr target = Rs1 + Rs2_or_imm13;
874 if(target & 0x3)
875 fault = new MemAddressNotAligned;
876 else
877 {
878 Rd = xc->readPC();
879 NNPC = target;
880 }
881 }});
882 0x39: Branch::return({{
883 //If both MemAddressNotAligned and
884 //a fill trap happen, it's not clear
885 //which one should be returned.
886 Addr target = Rs1 + Rs2_or_imm13;
887 if(target & 0x3)
888 fault = new MemAddressNotAligned;
889 else
890 NNPC = target;
891 if(fault == NoFault)
892 {
893 if(Canrestore == 0)
894 {
895 if(Otherwin)
896 fault = new FillNOther(Wstate<5:3>);
897 else
898 fault = new FillNNormal(Wstate<2:0>);
899 }
900 else
901 {
902 //CWP should be set directly so that it always happens
903 //Also, this will allow writing to the new window and
904 //reading from the old one
905 Cwp = (Cwp - 1 + NWindows) % NWindows;
906 Cansave = Cansave + 1;
907 Canrestore = Canrestore - 1;
908 //This is here to make sure the CWP is written
909 //no matter what. This ensures that the results
910 //are written in the new window as well.
911 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
912 }
913 }
914 }});
915 0x3A: decode CC
916 {
917 0x0: Trap::tcci({{
918 if(passesCondition(Ccr<3:0>, COND2))
919 {
920#if FULL_SYSTEM
921 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
922 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
923 fault = new TrapInstruction(lTrapNum);
924#else
925 DPRINTF(Sparc, "The syscall number is %d\n", R1);
926 xc->syscall(R1);
927#endif
928 }
929 }});
930 0x2: Trap::tccx({{
931 if(passesCondition(Ccr<7:4>, COND2))
932 {
933#if FULL_SYSTEM
934 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
935 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
936 fault = new TrapInstruction(lTrapNum);
937#else
938 DPRINTF(Sparc, "The syscall number is %d\n", R1);
939 xc->syscall(R1);
940#endif
941 }
942 }});
943 }
944 0x3B: Nop::flush({{/*Instruction memory flush*/}});
945 0x3C: save({{
946 //CWP should be set directly so that it always happens
947 //Also, this will allow writing to the new window and
948 //reading from the old one
949 if(Cansave == 0)
950 {
951 if(Otherwin)
952 fault = new SpillNOther(Wstate<5:3>);
953 else
954 fault = new SpillNNormal(Wstate<2:0>);
955 //Cwp = (Cwp + 2) % NWindows;
956 }
957 else if(Cleanwin - Canrestore == 0)
958 {
959 //Cwp = (Cwp + 1) % NWindows;
960 fault = new CleanWindow;
961 }
962 else
963 {
964 Cwp = (Cwp + 1) % NWindows;
965 Rd = Rs1 + Rs2_or_imm13;
966 Cansave = Cansave - 1;
967 Canrestore = Canrestore + 1;
968 //This is here to make sure the CWP is written
969 //no matter what. This ensures that the results
970 //are written in the new window as well.
971 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
972 }
973 }});
974 0x3D: restore({{
975 if(Canrestore == 0)
976 {
977 if(Otherwin)
978 fault = new FillNOther(Wstate<5:3>);
979 else
980 fault = new FillNNormal(Wstate<2:0>);
981 }
982 else
983 {
984 //CWP should be set directly so that it always happens
985 //Also, this will allow writing to the new window and
986 //reading from the old one
987 Cwp = (Cwp - 1 + NWindows) % NWindows;
988 Rd = Rs1 + Rs2_or_imm13;
989 Cansave = Cansave + 1;
990 Canrestore = Canrestore - 1;
991 //This is here to make sure the CWP is written
992 //no matter what. This ensures that the results
993 //are written in the new window as well.
994 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
995 }
996 }});
997 0x3E: decode FCN {
998 0x0: Priv::done({{
999 if(Tl == 0)
1000 return new IllegalInstruction;
1001
1002 Cwp = Tstate<4:0>;
1003 Pstate = Tstate<20:8>;
1004 Asi = Tstate<31:24>;
1005 Ccr = Tstate<39:32>;
1006 Gl = Tstate<42:40>;
1007 NPC = Tnpc;
1008 NNPC = Tnpc + 4;
1009 Tl = Tl - 1;
1010 }});
1011 0x1: Priv::retry({{
1012 if(Tl == 0)
1013 return new IllegalInstruction;
1014 Cwp = Tstate<4:0>;
1015 Pstate = Tstate<20:8>;
1016 Asi = Tstate<31:24>;
1017 Ccr = Tstate<39:32>;
1018 Gl = Tstate<42:40>;
1019 NPC = Tpc;
1020 NNPC = Tnpc;
1021 Tl = Tl - 1;
1022 }});
1023 }
1024 }
1025 }
1026 0x3: decode OP3 {
1027 format Load {
1028 0x00: lduw({{Rd = Mem.uw;}});
1029 0x01: ldub({{Rd = Mem.ub;}});
1030 0x02: lduh({{Rd = Mem.uhw;}});
1031 0x03: ldd({{
1032 uint64_t val = Mem.udw;
1033 RdLow = val<31:0>;
1034 RdHigh = val<63:32>;
1035 }});
1036 }
1037 format Store {
1038 0x04: stw({{Mem.uw = Rd.sw;}});
1039 0x05: stb({{Mem.ub = Rd.sb;}});
1040 0x06: sth({{Mem.uhw = Rd.shw;}});
1041 0x07: std({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
1042 }
1043 format Load {
1044 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
1045 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
1046 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
1047 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
1048 }
1049 0x0D: LoadStore::ldstub(
1050 {{Rd = Mem.ub;}},
1051 {{Mem.ub = 0xFF;}});
1052 0x0E: Store::stx({{Mem.udw = Rd}});
1053 0x0F: LoadStore::swap(
1054 {{uReg0 = Rd.uw;
1055 Rd.uw = Mem.uw;}},
1056 {{Mem.uw = uReg0;}});
| 666 }
667 0x34: decode OPF{
668 format BasicOperate{
669 0x01: fmovs({{
670 Frds.uw = Frs2s.uw;
671 //fsr.ftt = fsr.cexc = 0
672 Fsr &= ~(7 << 14);
673 Fsr &= ~(0x1F);
674 }});
675 0x02: fmovd({{
676 Frd.udw = Frs2.udw;
677 //fsr.ftt = fsr.cexc = 0
678 Fsr &= ~(7 << 14);
679 Fsr &= ~(0x1F);
680 }});
681 0x03: Trap::fmovq({{fault = new FpDisabled;}});
682 0x05: fnegs({{
683 Frds.uw = Frs2s.uw ^ (1UL << 31);
684 //fsr.ftt = fsr.cexc = 0
685 Fsr &= ~(7 << 14);
686 Fsr &= ~(0x1F);
687 }});
688 0x06: fnegd({{
689 Frd.udw = Frs2.udw ^ (1ULL << 63);
690 //fsr.ftt = fsr.cexc = 0
691 Fsr &= ~(7 << 14);
692 Fsr &= ~(0x1F);
693 }});
694 0x07: Trap::fnegq({{fault = new FpDisabled;}});
695 0x09: fabss({{
696 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;
697 //fsr.ftt = fsr.cexc = 0
698 Fsr &= ~(7 << 14);
699 Fsr &= ~(0x1F);
700 }});
701 0x0A: fabsd({{
702 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;
703 //fsr.ftt = fsr.cexc = 0
704 Fsr &= ~(7 << 14);
705 Fsr &= ~(0x1F);
706 }});
707 0x0B: Trap::fabsq({{fault = new FpDisabled;}});
708 0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}});
709 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}});
710 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
711 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
712 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
713 0x43: Trap::faddq({{fault = new FpDisabled;}});
714 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
715 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
716 0x47: Trap::fsubq({{fault = new FpDisabled;}});
717 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
718 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
719 0x4B: Trap::fmulq({{fault = new FpDisabled;}});
720 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
721 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
722 0x4F: Trap::fdivq({{fault = new FpDisabled;}});
723 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
724 0x6E: Trap::fdmulq({{fault = new FpDisabled;}});
725 0x81: fstox({{
726 Frd.df = (double)static_cast<int64_t>(Frs2s.sf);
727 }});
728 0x82: fdtox({{
729 Frd.df = (double)static_cast<int64_t>(Frs2.df);
730 }});
731 0x83: Trap::fqtox({{fault = new FpDisabled;}});
732 0x84: fxtos({{
733 Frds.sf = static_cast<float>((int64_t)Frs2.df);
734 }});
735 0x88: fxtod({{
736 Frd.df = static_cast<double>((int64_t)Frs2.df);
737 }});
738 0x8C: Trap::fxtoq({{fault = new FpDisabled;}});
739 0xC4: fitos({{
740 Frds.sf = static_cast<float>((int32_t)Frs2s.sf);
741 }});
742 0xC6: fdtos({{Frds.sf = Frs2.df;}});
743 0xC7: Trap::fqtos({{fault = new FpDisabled;}});
744 0xC8: fitod({{
745 Frd.df = static_cast<double>((int32_t)Frs2s.sf);
746 }});
747 0xC9: fstod({{Frd.df = Frs2s.sf;}});
748 0xCB: Trap::fqtod({{fault = new FpDisabled;}});
749 0xCC: Trap::fitoq({{fault = new FpDisabled;}});
750 0xCD: Trap::fstoq({{fault = new FpDisabled;}});
751 0xCE: Trap::fdtoq({{fault = new FpDisabled;}});
752 0xD1: fstoi({{
753 Frds.sf = (float)static_cast<int32_t>(Frs2s.sf);
754 }});
755 0xD2: fdtoi({{
756 Frds.sf = (float)static_cast<int32_t>(Frs2.df);
757 }});
758 0xD3: Trap::fqtoi({{fault = new FpDisabled;}});
759 default: Trap::fpop1({{fault = new FpDisabled;}});
760 }
761 }
762 0x35: Trap::fpop2({{fault = new FpDisabled;}});
763 //This used to be just impdep1, but now it's a whole bunch
764 //of instructions
765 0x36: decode OPF{
766 0x00: Trap::edge8({{fault = new IllegalInstruction;}});
767 0x01: Trap::edge8n({{fault = new IllegalInstruction;}});
768 0x02: Trap::edge8l({{fault = new IllegalInstruction;}});
769 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}});
770 0x04: Trap::edge16({{fault = new IllegalInstruction;}});
771 0x05: Trap::edge16n({{fault = new IllegalInstruction;}});
772 0x06: Trap::edge16l({{fault = new IllegalInstruction;}});
773 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}});
774 0x08: Trap::edge32({{fault = new IllegalInstruction;}});
775 0x09: Trap::edge32n({{fault = new IllegalInstruction;}});
776 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}});
777 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}});
778 0x10: Trap::array8({{fault = new IllegalInstruction;}});
779 0x12: Trap::array16({{fault = new IllegalInstruction;}});
780 0x14: Trap::array32({{fault = new IllegalInstruction;}});
781 0x18: BasicOperate::alignaddr({{
782 uint64_t sum = Rs1 + Rs2;
783 Rd = sum & ~7;
784 Gsr = (Gsr & ~7) | (sum & 7);
785 }});
786 0x19: Trap::bmask({{fault = new IllegalInstruction;}});
787 0x1A: BasicOperate::alignaddresslittle({{
788 uint64_t sum = Rs1 + Rs2;
789 Rd = sum & ~7;
790 Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
791 }});
792 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}});
793 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}});
794 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}});
795 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}});
796 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}});
797 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}});
798 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}});
799 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}});
800 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}});
801 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}});
802 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}});
803 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}});
804 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}});
805 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}});
806 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}});
807 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
808 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
809 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
810 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
811 0x48: BasicOperate::faligndata({{
812 uint64_t msbX = Frs1.udw;
813 uint64_t lsbX = Frs2.udw;
814 //Some special cases need to be split out, first
815 //because they're the most likely to be used, and
816 //second because otherwise, we end up shifting by
817 //greater than the width of the type being shifted,
818 //namely 64, which produces undefined results according
819 //to the C standard.
820 switch(Gsr<2:0>)
821 {
822 case 0:
823 Frd.udw = msbX;
824 break;
825 case 8:
826 Frd.udw = lsbX;
827 break;
828 default:
829 uint64_t msbShift = Gsr<2:0> * 8;
830 uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
831 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
832 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
833 Frd.udw = ((msbX & msbMask) << msbShift) |
834 ((lsbX & lsbMask) >> lsbShift);
835 }
836 }});
837 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
838 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}});
839 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}});
840 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}});
841 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}});
842 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}});
843 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}});
844 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}});
845 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}});
846 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}});
847 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}});
848 0x60: BasicOperate::fzero({{Frd.df = 0;}});
849 0x61: BasicOperate::fzeros({{Frds.sf = 0;}});
850 0x62: Trap::fnor({{fault = new IllegalInstruction;}});
851 0x63: Trap::fnors({{fault = new IllegalInstruction;}});
852 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}});
853 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}});
854 0x66: BasicOperate::fnot2({{
855 Frd.df = (double)(~((uint64_t)Frs2.df));
856 }});
857 0x67: BasicOperate::fnot2s({{
858 Frds.sf = (float)(~((uint32_t)Frs2s.sf));
859 }});
860 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}});
861 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}});
862 0x6A: BasicOperate::fnot1({{
863 Frd.df = (double)(~((uint64_t)Frs1.df));
864 }});
865 0x6B: BasicOperate::fnot1s({{
866 Frds.sf = (float)(~((uint32_t)Frs1s.sf));
867 }});
868 0x6C: Trap::fxor({{fault = new IllegalInstruction;}});
869 0x6D: Trap::fxors({{fault = new IllegalInstruction;}});
870 0x6E: Trap::fnand({{fault = new IllegalInstruction;}});
871 0x6F: Trap::fnands({{fault = new IllegalInstruction;}});
872 0x70: Trap::fand({{fault = new IllegalInstruction;}});
873 0x71: Trap::fands({{fault = new IllegalInstruction;}});
874 0x72: Trap::fxnor({{fault = new IllegalInstruction;}});
875 0x73: Trap::fxnors({{fault = new IllegalInstruction;}});
876 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}});
877 0x75: BasicOperate::fsrc1s({{Frd.uw = Frs1.uw;}});
878 0x76: Trap::fornot2({{fault = new IllegalInstruction;}});
879 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}});
880 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}});
881 0x79: BasicOperate::fsrc2s({{Frd.uw = Frs2.uw;}});
882 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}});
883 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}});
884 0x7C: Trap::for({{fault = new IllegalInstruction;}});
885 0x7D: Trap::fors({{fault = new IllegalInstruction;}});
886 0x7E: Trap::fone({{fault = new IllegalInstruction;}});
887 0x7F: Trap::fones({{fault = new IllegalInstruction;}});
888 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
889 0x81: Trap::siam({{fault = new IllegalInstruction;}});
890 }
891 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
892 0x38: Branch::jmpl({{
893 Addr target = Rs1 + Rs2_or_imm13;
894 if(target & 0x3)
895 fault = new MemAddressNotAligned;
896 else
897 {
898 Rd = xc->readPC();
899 NNPC = target;
900 }
901 }});
902 0x39: Branch::return({{
903 //If both MemAddressNotAligned and
904 //a fill trap happen, it's not clear
905 //which one should be returned.
906 Addr target = Rs1 + Rs2_or_imm13;
907 if(target & 0x3)
908 fault = new MemAddressNotAligned;
909 else
910 NNPC = target;
911 if(fault == NoFault)
912 {
913 if(Canrestore == 0)
914 {
915 if(Otherwin)
916 fault = new FillNOther(Wstate<5:3>);
917 else
918 fault = new FillNNormal(Wstate<2:0>);
919 }
920 else
921 {
922 //CWP should be set directly so that it always happens
923 //Also, this will allow writing to the new window and
924 //reading from the old one
925 Cwp = (Cwp - 1 + NWindows) % NWindows;
926 Cansave = Cansave + 1;
927 Canrestore = Canrestore - 1;
928 //This is here to make sure the CWP is written
929 //no matter what. This ensures that the results
930 //are written in the new window as well.
931 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
932 }
933 }
934 }});
935 0x3A: decode CC
936 {
937 0x0: Trap::tcci({{
938 if(passesCondition(Ccr<3:0>, COND2))
939 {
940#if FULL_SYSTEM
941 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
942 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
943 fault = new TrapInstruction(lTrapNum);
944#else
945 DPRINTF(Sparc, "The syscall number is %d\n", R1);
946 xc->syscall(R1);
947#endif
948 }
949 }});
950 0x2: Trap::tccx({{
951 if(passesCondition(Ccr<7:4>, COND2))
952 {
953#if FULL_SYSTEM
954 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
955 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
956 fault = new TrapInstruction(lTrapNum);
957#else
958 DPRINTF(Sparc, "The syscall number is %d\n", R1);
959 xc->syscall(R1);
960#endif
961 }
962 }});
963 }
964 0x3B: Nop::flush({{/*Instruction memory flush*/}});
965 0x3C: save({{
966 //CWP should be set directly so that it always happens
967 //Also, this will allow writing to the new window and
968 //reading from the old one
969 if(Cansave == 0)
970 {
971 if(Otherwin)
972 fault = new SpillNOther(Wstate<5:3>);
973 else
974 fault = new SpillNNormal(Wstate<2:0>);
975 //Cwp = (Cwp + 2) % NWindows;
976 }
977 else if(Cleanwin - Canrestore == 0)
978 {
979 //Cwp = (Cwp + 1) % NWindows;
980 fault = new CleanWindow;
981 }
982 else
983 {
984 Cwp = (Cwp + 1) % NWindows;
985 Rd = Rs1 + Rs2_or_imm13;
986 Cansave = Cansave - 1;
987 Canrestore = Canrestore + 1;
988 //This is here to make sure the CWP is written
989 //no matter what. This ensures that the results
990 //are written in the new window as well.
991 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
992 }
993 }});
994 0x3D: restore({{
995 if(Canrestore == 0)
996 {
997 if(Otherwin)
998 fault = new FillNOther(Wstate<5:3>);
999 else
1000 fault = new FillNNormal(Wstate<2:0>);
1001 }
1002 else
1003 {
1004 //CWP should be set directly so that it always happens
1005 //Also, this will allow writing to the new window and
1006 //reading from the old one
1007 Cwp = (Cwp - 1 + NWindows) % NWindows;
1008 Rd = Rs1 + Rs2_or_imm13;
1009 Cansave = Cansave + 1;
1010 Canrestore = Canrestore - 1;
1011 //This is here to make sure the CWP is written
1012 //no matter what. This ensures that the results
1013 //are written in the new window as well.
1014 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
1015 }
1016 }});
1017 0x3E: decode FCN {
1018 0x0: Priv::done({{
1019 if(Tl == 0)
1020 return new IllegalInstruction;
1021
1022 Cwp = Tstate<4:0>;
1023 Pstate = Tstate<20:8>;
1024 Asi = Tstate<31:24>;
1025 Ccr = Tstate<39:32>;
1026 Gl = Tstate<42:40>;
1027 NPC = Tnpc;
1028 NNPC = Tnpc + 4;
1029 Tl = Tl - 1;
1030 }});
1031 0x1: Priv::retry({{
1032 if(Tl == 0)
1033 return new IllegalInstruction;
1034 Cwp = Tstate<4:0>;
1035 Pstate = Tstate<20:8>;
1036 Asi = Tstate<31:24>;
1037 Ccr = Tstate<39:32>;
1038 Gl = Tstate<42:40>;
1039 NPC = Tpc;
1040 NNPC = Tnpc;
1041 Tl = Tl - 1;
1042 }});
1043 }
1044 }
1045 }
1046 0x3: decode OP3 {
1047 format Load {
1048 0x00: lduw({{Rd = Mem.uw;}});
1049 0x01: ldub({{Rd = Mem.ub;}});
1050 0x02: lduh({{Rd = Mem.uhw;}});
1051 0x03: ldd({{
1052 uint64_t val = Mem.udw;
1053 RdLow = val<31:0>;
1054 RdHigh = val<63:32>;
1055 }});
1056 }
1057 format Store {
1058 0x04: stw({{Mem.uw = Rd.sw;}});
1059 0x05: stb({{Mem.ub = Rd.sb;}});
1060 0x06: sth({{Mem.uhw = Rd.shw;}});
1061 0x07: std({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
1062 }
1063 format Load {
1064 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
1065 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
1066 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
1067 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
1068 }
1069 0x0D: LoadStore::ldstub(
1070 {{Rd = Mem.ub;}},
1071 {{Mem.ub = 0xFF;}});
1072 0x0E: Store::stx({{Mem.udw = Rd}});
1073 0x0F: LoadStore::swap(
1074 {{uReg0 = Rd.uw;
1075 Rd.uw = Mem.uw;}},
1076 {{Mem.uw = uReg0;}});
|
1057 format LoadAlt {
1058 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}});
1059 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}});
1060 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}});
| 1077 format Load {
1078 0x10: lduwa({{Rd = Mem.uw;}});
1079 0x11: lduba({{Rd = Mem.ub;}});
1080 0x12: lduha({{Rd = Mem.uhw;}});
|
1061 0x13: ldda({{
1062 uint64_t val = Mem.udw;
1063 RdLow = val<31:0>;
1064 RdHigh = val<63:32>;
| 1081 0x13: ldda({{
1082 uint64_t val = Mem.udw;
1083 RdLow = val<31:0>;
1084 RdHigh = val<63:32>;
|
1065 }}, {{EXT_ASI}});
| 1085 }});
|
1066 }
| 1086 }
|
1067 format StoreAlt {
1068 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}});
1069 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
1070 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
1071 0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}});
| 1087 format Store {
1088 0x14: stwa({{Mem.uw = Rd;}});
1089 0x15: stba({{Mem.ub = Rd;}});
1090 0x16: stha({{Mem.uhw = Rd;}});
1091 0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}});
|
1072 }
| 1092 }
|
1073 format LoadAlt {
1074 0x18: ldswa({{Rd = (int32_t)Mem.sw;}}, {{EXT_ASI}});
1075 0x19: ldsba({{Rd = (int8_t)Mem.sb;}}, {{EXT_ASI}});
1076 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}}, {{EXT_ASI}});
1077 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}}, {{EXT_ASI}});
| 1093 format Load {
1094 0x18: ldswa({{Rd = (int32_t)Mem.sw;}});
1095 0x19: ldsba({{Rd = (int8_t)Mem.sb;}});
1096 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}});
1097 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}});
|
1078 }
| 1098 }
|
1079 0x1D: LoadStoreAlt::ldstuba(
| 1099 0x1D: LoadStore::ldstuba(
|
1080 {{Rd = Mem.ub;}},
| 1100 {{Rd = Mem.ub;}},
|
1081 {{Mem.ub = 0xFF}}, {{EXT_ASI}});
1082 0x1E: StoreAlt::stxa({{Mem.udw = Rd}}, {{EXT_ASI}});
1083 0x1F: LoadStoreAlt::swapa(
| 1101 {{Mem.ub = 0xFF}});
1102 0x1E: Store::stxa({{Mem.udw = Rd}});
1103 0x1F: LoadStore::swapa(
|
1084 {{uReg0 = Rd.uw;
1085 Rd.uw = Mem.uw;}},
| 1104 {{uReg0 = Rd.uw;
1105 Rd.uw = Mem.uw;}},
|
1086 {{Mem.uw = uReg0;}}, {{EXT_ASI}});
| 1106 {{Mem.uw = uReg0;}});
|
1087 format Trap {
1088 0x20: Load::ldf({{Frd.uw = Mem.uw;}});
1089 0x21: decode X {
1090 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}});
1091 0x1: Load::ldxfsr({{Fsr = Mem.udw;}});
1092 }
1093 0x22: ldqf({{fault = new FpDisabled;}});
1094 0x23: Load::lddf({{Frd.udw = Mem.udw;}});
1095 0x24: Store::stf({{Mem.uw = Frd.uw;}});
1096 0x25: decode X {
1097 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}});
1098 0x1: Store::stxfsr({{Mem.udw = Fsr;}});
1099 }
1100 0x26: stqf({{fault = new FpDisabled;}});
1101 0x27: Store::stdf({{Mem.udw = Frd.udw;}});
1102 0x2D: Nop::prefetch({{ }});
| 1107 format Trap {
1108 0x20: Load::ldf({{Frd.uw = Mem.uw;}});
1109 0x21: decode X {
1110 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}});
1111 0x1: Load::ldxfsr({{Fsr = Mem.udw;}});
1112 }
1113 0x22: ldqf({{fault = new FpDisabled;}});
1114 0x23: Load::lddf({{Frd.udw = Mem.udw;}});
1115 0x24: Store::stf({{Mem.uw = Frd.uw;}});
1116 0x25: decode X {
1117 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}});
1118 0x1: Store::stxfsr({{Mem.udw = Fsr;}});
1119 }
1120 0x26: stqf({{fault = new FpDisabled;}});
1121 0x27: Store::stdf({{Mem.udw = Frd.udw;}});
1122 0x2D: Nop::prefetch({{ }});
|
1103 0x30: LoadAlt::ldfa({{Frd.uw = Mem.uw;}}, {{EXT_ASI}});
| 1123 0x30: Load::ldfa({{Frd.uw = Mem.uw;}});
|
1104 0x32: ldqfa({{fault = new FpDisabled;}});
1105 format LoadAlt {
1106 0x33: decode EXT_ASI {
1107 //ASI_NUCLEUS
1108 0x04: FailUnimpl::lddfa_n();
1109 //ASI_NUCLEUS_LITTLE
1110 0x0C: FailUnimpl::lddfa_nl();
1111 //ASI_AS_IF_USER_PRIMARY
1112 0x10: FailUnimpl::lddfa_aiup();
1113 //ASI_AS_IF_USER_PRIMARY_LITTLE
1114 0x18: FailUnimpl::lddfa_aiupl();
1115 //ASI_AS_IF_USER_SECONDARY
1116 0x11: FailUnimpl::lddfa_aius();
1117 //ASI_AS_IF_USER_SECONDARY_LITTLE
1118 0x19: FailUnimpl::lddfa_aiusl();
1119 //ASI_REAL
1120 0x14: FailUnimpl::lddfa_real();
1121 //ASI_REAL_LITTLE
1122 0x1C: FailUnimpl::lddfa_real_l();
1123 //ASI_REAL_IO
1124 0x15: FailUnimpl::lddfa_real_io();
1125 //ASI_REAL_IO_LITTLE
1126 0x1D: FailUnimpl::lddfa_real_io_l();
1127 //ASI_PRIMARY
1128 0x80: FailUnimpl::lddfa_p();
1129 //ASI_PRIMARY_LITTLE
1130 0x88: FailUnimpl::lddfa_pl();
1131 //ASI_SECONDARY
1132 0x81: FailUnimpl::lddfa_s();
1133 //ASI_SECONDARY_LITTLE
1134 0x89: FailUnimpl::lddfa_sl();
1135 //ASI_PRIMARY_NO_FAULT
1136 0x82: FailUnimpl::lddfa_pnf();
1137 //ASI_PRIMARY_NO_FAULT_LITTLE
1138 0x8A: FailUnimpl::lddfa_pnfl();
1139 //ASI_SECONDARY_NO_FAULT
1140 0x83: FailUnimpl::lddfa_snf();
1141 //ASI_SECONDARY_NO_FAULT_LITTLE
1142 0x8B: FailUnimpl::lddfa_snfl();
1143
1144 format BlockLoad {
1145 // LDBLOCKF
1146 //ASI_BLOCK_AS_IF_USER_PRIMARY
1147 0x16: FailUnimpl::ldblockf_aiup();
1148 //ASI_BLOCK_AS_IF_USER_SECONDARY
1149 0x17: FailUnimpl::ldblockf_aius();
1150 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1151 0x1E: FailUnimpl::ldblockf_aiupl();
1152 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1153 0x1F: FailUnimpl::ldblockf_aiusl();
1154 //ASI_BLOCK_PRIMARY
| 1124 0x32: ldqfa({{fault = new FpDisabled;}});
1125 format LoadAlt {
1126 0x33: decode EXT_ASI {
1127 //ASI_NUCLEUS
1128 0x04: FailUnimpl::lddfa_n();
1129 //ASI_NUCLEUS_LITTLE
1130 0x0C: FailUnimpl::lddfa_nl();
1131 //ASI_AS_IF_USER_PRIMARY
1132 0x10: FailUnimpl::lddfa_aiup();
1133 //ASI_AS_IF_USER_PRIMARY_LITTLE
1134 0x18: FailUnimpl::lddfa_aiupl();
1135 //ASI_AS_IF_USER_SECONDARY
1136 0x11: FailUnimpl::lddfa_aius();
1137 //ASI_AS_IF_USER_SECONDARY_LITTLE
1138 0x19: FailUnimpl::lddfa_aiusl();
1139 //ASI_REAL
1140 0x14: FailUnimpl::lddfa_real();
1141 //ASI_REAL_LITTLE
1142 0x1C: FailUnimpl::lddfa_real_l();
1143 //ASI_REAL_IO
1144 0x15: FailUnimpl::lddfa_real_io();
1145 //ASI_REAL_IO_LITTLE
1146 0x1D: FailUnimpl::lddfa_real_io_l();
1147 //ASI_PRIMARY
1148 0x80: FailUnimpl::lddfa_p();
1149 //ASI_PRIMARY_LITTLE
1150 0x88: FailUnimpl::lddfa_pl();
1151 //ASI_SECONDARY
1152 0x81: FailUnimpl::lddfa_s();
1153 //ASI_SECONDARY_LITTLE
1154 0x89: FailUnimpl::lddfa_sl();
1155 //ASI_PRIMARY_NO_FAULT
1156 0x82: FailUnimpl::lddfa_pnf();
1157 //ASI_PRIMARY_NO_FAULT_LITTLE
1158 0x8A: FailUnimpl::lddfa_pnfl();
1159 //ASI_SECONDARY_NO_FAULT
1160 0x83: FailUnimpl::lddfa_snf();
1161 //ASI_SECONDARY_NO_FAULT_LITTLE
1162 0x8B: FailUnimpl::lddfa_snfl();
1163
1164 format BlockLoad {
1165 // LDBLOCKF
1166 //ASI_BLOCK_AS_IF_USER_PRIMARY
1167 0x16: FailUnimpl::ldblockf_aiup();
1168 //ASI_BLOCK_AS_IF_USER_SECONDARY
1169 0x17: FailUnimpl::ldblockf_aius();
1170 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1171 0x1E: FailUnimpl::ldblockf_aiupl();
1172 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1173 0x1F: FailUnimpl::ldblockf_aiusl();
1174 //ASI_BLOCK_PRIMARY
|
1155 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}}, {{EXT_ASI}});
| 1175 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}});
|
1156 //ASI_BLOCK_SECONDARY
1157 0xF1: FailUnimpl::ldblockf_s();
1158 //ASI_BLOCK_PRIMARY_LITTLE
1159 0xF8: FailUnimpl::ldblockf_pl();
1160 //ASI_BLOCK_SECONDARY_LITTLE
1161 0xF9: FailUnimpl::ldblockf_sl();
1162 }
1163
1164 //LDSHORTF
1165 //ASI_FL8_PRIMARY
1166 0xD0: FailUnimpl::ldshortf_8p();
1167 //ASI_FL8_SECONDARY
1168 0xD1: FailUnimpl::ldshortf_8s();
1169 //ASI_FL8_PRIMARY_LITTLE
1170 0xD8: FailUnimpl::ldshortf_8pl();
1171 //ASI_FL8_SECONDARY_LITTLE
1172 0xD9: FailUnimpl::ldshortf_8sl();
1173 //ASI_FL16_PRIMARY
1174 0xD2: FailUnimpl::ldshortf_16p();
1175 //ASI_FL16_SECONDARY
1176 0xD3: FailUnimpl::ldshortf_16s();
1177 //ASI_FL16_PRIMARY_LITTLE
1178 0xDA: FailUnimpl::ldshortf_16pl();
1179 //ASI_FL16_SECONDARY_LITTLE
1180 0xDB: FailUnimpl::ldshortf_16sl();
1181 //Not an ASI which is legal with lddfa
1182 default: Trap::lddfa_bad_asi(
1183 {{fault = new DataAccessException;}});
1184 }
1185 }
1186 0x34: Store::stfa({{Mem.uw = Frd.uw;}});
1187 0x36: stqfa({{fault = new FpDisabled;}});
1188 format StoreAlt {
1189 0x37: decode EXT_ASI {
1190 //ASI_NUCLEUS
1191 0x04: FailUnimpl::stdfa_n();
1192 //ASI_NUCLEUS_LITTLE
1193 0x0C: FailUnimpl::stdfa_nl();
1194 //ASI_AS_IF_USER_PRIMARY
1195 0x10: FailUnimpl::stdfa_aiup();
1196 //ASI_AS_IF_USER_PRIMARY_LITTLE
1197 0x18: FailUnimpl::stdfa_aiupl();
1198 //ASI_AS_IF_USER_SECONDARY
1199 0x11: FailUnimpl::stdfa_aius();
1200 //ASI_AS_IF_USER_SECONDARY_LITTLE
1201 0x19: FailUnimpl::stdfa_aiusl();
1202 //ASI_REAL
1203 0x14: FailUnimpl::stdfa_real();
1204 //ASI_REAL_LITTLE
1205 0x1C: FailUnimpl::stdfa_real_l();
1206 //ASI_REAL_IO
1207 0x15: FailUnimpl::stdfa_real_io();
1208 //ASI_REAL_IO_LITTLE
1209 0x1D: FailUnimpl::stdfa_real_io_l();
1210 //ASI_PRIMARY
1211 0x80: FailUnimpl::stdfa_p();
1212 //ASI_PRIMARY_LITTLE
1213 0x88: FailUnimpl::stdfa_pl();
1214 //ASI_SECONDARY
1215 0x81: FailUnimpl::stdfa_s();
1216 //ASI_SECONDARY_LITTLE
1217 0x89: FailUnimpl::stdfa_sl();
1218 //ASI_PRIMARY_NO_FAULT
1219 0x82: FailUnimpl::stdfa_pnf();
1220 //ASI_PRIMARY_NO_FAULT_LITTLE
1221 0x8A: FailUnimpl::stdfa_pnfl();
1222 //ASI_SECONDARY_NO_FAULT
1223 0x83: FailUnimpl::stdfa_snf();
1224 //ASI_SECONDARY_NO_FAULT_LITTLE
1225 0x8B: FailUnimpl::stdfa_snfl();
1226
1227 format BlockStore {
1228 // STBLOCKF
1229 //ASI_BLOCK_AS_IF_USER_PRIMARY
1230 0x16: FailUnimpl::stblockf_aiup();
1231 //ASI_BLOCK_AS_IF_USER_SECONDARY
1232 0x17: FailUnimpl::stblockf_aius();
1233 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1234 0x1E: FailUnimpl::stblockf_aiupl();
1235 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1236 0x1F: FailUnimpl::stblockf_aiusl();
1237 //ASI_BLOCK_PRIMARY
| 1176 //ASI_BLOCK_SECONDARY
1177 0xF1: FailUnimpl::ldblockf_s();
1178 //ASI_BLOCK_PRIMARY_LITTLE
1179 0xF8: FailUnimpl::ldblockf_pl();
1180 //ASI_BLOCK_SECONDARY_LITTLE
1181 0xF9: FailUnimpl::ldblockf_sl();
1182 }
1183
1184 //LDSHORTF
1185 //ASI_FL8_PRIMARY
1186 0xD0: FailUnimpl::ldshortf_8p();
1187 //ASI_FL8_SECONDARY
1188 0xD1: FailUnimpl::ldshortf_8s();
1189 //ASI_FL8_PRIMARY_LITTLE
1190 0xD8: FailUnimpl::ldshortf_8pl();
1191 //ASI_FL8_SECONDARY_LITTLE
1192 0xD9: FailUnimpl::ldshortf_8sl();
1193 //ASI_FL16_PRIMARY
1194 0xD2: FailUnimpl::ldshortf_16p();
1195 //ASI_FL16_SECONDARY
1196 0xD3: FailUnimpl::ldshortf_16s();
1197 //ASI_FL16_PRIMARY_LITTLE
1198 0xDA: FailUnimpl::ldshortf_16pl();
1199 //ASI_FL16_SECONDARY_LITTLE
1200 0xDB: FailUnimpl::ldshortf_16sl();
1201 //Not an ASI which is legal with lddfa
1202 default: Trap::lddfa_bad_asi(
1203 {{fault = new DataAccessException;}});
1204 }
1205 }
1206 0x34: Store::stfa({{Mem.uw = Frd.uw;}});
1207 0x36: stqfa({{fault = new FpDisabled;}});
1208 format StoreAlt {
1209 0x37: decode EXT_ASI {
1210 //ASI_NUCLEUS
1211 0x04: FailUnimpl::stdfa_n();
1212 //ASI_NUCLEUS_LITTLE
1213 0x0C: FailUnimpl::stdfa_nl();
1214 //ASI_AS_IF_USER_PRIMARY
1215 0x10: FailUnimpl::stdfa_aiup();
1216 //ASI_AS_IF_USER_PRIMARY_LITTLE
1217 0x18: FailUnimpl::stdfa_aiupl();
1218 //ASI_AS_IF_USER_SECONDARY
1219 0x11: FailUnimpl::stdfa_aius();
1220 //ASI_AS_IF_USER_SECONDARY_LITTLE
1221 0x19: FailUnimpl::stdfa_aiusl();
1222 //ASI_REAL
1223 0x14: FailUnimpl::stdfa_real();
1224 //ASI_REAL_LITTLE
1225 0x1C: FailUnimpl::stdfa_real_l();
1226 //ASI_REAL_IO
1227 0x15: FailUnimpl::stdfa_real_io();
1228 //ASI_REAL_IO_LITTLE
1229 0x1D: FailUnimpl::stdfa_real_io_l();
1230 //ASI_PRIMARY
1231 0x80: FailUnimpl::stdfa_p();
1232 //ASI_PRIMARY_LITTLE
1233 0x88: FailUnimpl::stdfa_pl();
1234 //ASI_SECONDARY
1235 0x81: FailUnimpl::stdfa_s();
1236 //ASI_SECONDARY_LITTLE
1237 0x89: FailUnimpl::stdfa_sl();
1238 //ASI_PRIMARY_NO_FAULT
1239 0x82: FailUnimpl::stdfa_pnf();
1240 //ASI_PRIMARY_NO_FAULT_LITTLE
1241 0x8A: FailUnimpl::stdfa_pnfl();
1242 //ASI_SECONDARY_NO_FAULT
1243 0x83: FailUnimpl::stdfa_snf();
1244 //ASI_SECONDARY_NO_FAULT_LITTLE
1245 0x8B: FailUnimpl::stdfa_snfl();
1246
1247 format BlockStore {
1248 // STBLOCKF
1249 //ASI_BLOCK_AS_IF_USER_PRIMARY
1250 0x16: FailUnimpl::stblockf_aiup();
1251 //ASI_BLOCK_AS_IF_USER_SECONDARY
1252 0x17: FailUnimpl::stblockf_aius();
1253 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1254 0x1E: FailUnimpl::stblockf_aiupl();
1255 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1256 0x1F: FailUnimpl::stblockf_aiusl();
1257 //ASI_BLOCK_PRIMARY
|
1238 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}}, {{EXT_ASI}});
| 1258 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}});
|
1239 //ASI_BLOCK_SECONDARY
1240 0xF1: FailUnimpl::stblockf_s();
1241 //ASI_BLOCK_PRIMARY_LITTLE
1242 0xF8: FailUnimpl::stblockf_pl();
1243 //ASI_BLOCK_SECONDARY_LITTLE
1244 0xF9: FailUnimpl::stblockf_sl();
1245 }
1246
1247 //STSHORTF
1248 //ASI_FL8_PRIMARY
1249 0xD0: FailUnimpl::stshortf_8p();
1250 //ASI_FL8_SECONDARY
1251 0xD1: FailUnimpl::stshortf_8s();
1252 //ASI_FL8_PRIMARY_LITTLE
1253 0xD8: FailUnimpl::stshortf_8pl();
1254 //ASI_FL8_SECONDARY_LITTLE
1255 0xD9: FailUnimpl::stshortf_8sl();
1256 //ASI_FL16_PRIMARY
1257 0xD2: FailUnimpl::stshortf_16p();
1258 //ASI_FL16_SECONDARY
1259 0xD3: FailUnimpl::stshortf_16s();
1260 //ASI_FL16_PRIMARY_LITTLE
1261 0xDA: FailUnimpl::stshortf_16pl();
1262 //ASI_FL16_SECONDARY_LITTLE
1263 0xDB: FailUnimpl::stshortf_16sl();
1264 //Not an ASI which is legal with lddfa
1265 default: Trap::stdfa_bad_asi(
1266 {{fault = new DataAccessException;}});
1267 }
1268 }
1269 0x3C: Cas::casa(
1270 {{uReg0 = Mem.uw;}},
1271 {{if(Rs2.uw == uReg0)
1272 Mem.uw = Rd.uw;
1273 else
1274 storeCond = false;
| 1259 //ASI_BLOCK_SECONDARY
1260 0xF1: FailUnimpl::stblockf_s();
1261 //ASI_BLOCK_PRIMARY_LITTLE
1262 0xF8: FailUnimpl::stblockf_pl();
1263 //ASI_BLOCK_SECONDARY_LITTLE
1264 0xF9: FailUnimpl::stblockf_sl();
1265 }
1266
1267 //STSHORTF
1268 //ASI_FL8_PRIMARY
1269 0xD0: FailUnimpl::stshortf_8p();
1270 //ASI_FL8_SECONDARY
1271 0xD1: FailUnimpl::stshortf_8s();
1272 //ASI_FL8_PRIMARY_LITTLE
1273 0xD8: FailUnimpl::stshortf_8pl();
1274 //ASI_FL8_SECONDARY_LITTLE
1275 0xD9: FailUnimpl::stshortf_8sl();
1276 //ASI_FL16_PRIMARY
1277 0xD2: FailUnimpl::stshortf_16p();
1278 //ASI_FL16_SECONDARY
1279 0xD3: FailUnimpl::stshortf_16s();
1280 //ASI_FL16_PRIMARY_LITTLE
1281 0xDA: FailUnimpl::stshortf_16pl();
1282 //ASI_FL16_SECONDARY_LITTLE
1283 0xDB: FailUnimpl::stshortf_16sl();
1284 //Not an ASI which is legal with lddfa
1285 default: Trap::stdfa_bad_asi(
1286 {{fault = new DataAccessException;}});
1287 }
1288 }
1289 0x3C: Cas::casa(
1290 {{uReg0 = Mem.uw;}},
1291 {{if(Rs2.uw == uReg0)
1292 Mem.uw = Rd.uw;
1293 else
1294 storeCond = false;
|
1275 Rd.uw = uReg0;}}, {{EXT_ASI}});
| 1295 Rd.uw = uReg0;}});
|
1276 0x3D: Nop::prefetcha({{ }});
1277 0x3E: Cas::casxa(
1278 {{uReg0 = Mem.udw;}},
1279 {{if(Rs2 == uReg0)
1280 Mem.udw = Rd;
1281 else
1282 storeCond = false;
| 1296 0x3D: Nop::prefetcha({{ }});
1297 0x3E: Cas::casxa(
1298 {{uReg0 = Mem.udw;}},
1299 {{if(Rs2 == uReg0)
1300 Mem.udw = Rd;
1301 else
1302 storeCond = false;
|
1283 Rd = uReg0;}}, {{EXT_ASI}});
| 1303 Rd = uReg0;}});
|
1284 }
1285 }
1286}
| 1304 }
1305 }
1306}
|