1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OP default Unknown::unknown()
37{
38 0x0: decode OP2
39 {
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 0x1: decode COND2
45 {
46 //Branch Always
47 0x8: decode A
48 {
49 0x0: b(19, {{
50 NNPC = xc->readPC() + disp;
51 }});
52 0x1: b(19, {{
53 NPC = xc->readPC() + disp;
54 NNPC = NPC + 4;
55 }}, ',a');
56 }
57 //Branch Never
58 0x0: decode A
59 {
60 0x0: bn(19, {{
61 NNPC = NNPC;//Don't do anything
62 }});
63 0x1: bn(19, {{
64 NPC = xc->readNextPC() + 4;
65 NNPC = NPC + 4;
66 }}, ',a');
67 }
68 default: decode BPCC
69 {
70 0x0: bpcci(19, {{
71 if(passesCondition(Ccr<3:0>, COND2))
72 NNPC = xc->readPC() + disp;
73 else
74 handle_annul
75 }});
76 0x2: bpccx(19, {{
77 if(passesCondition(Ccr<7:4>, COND2))
78 NNPC = xc->readPC() + disp;
79 else
80 handle_annul
81 }});
82 }
83 }
84 0x2: bicc(22, {{
85 if(passesCondition(Ccr<3:0>, COND2))
86 NNPC = xc->readPC() + disp;
87 else
88 handle_annul
89 }});
90 }
91 0x3: decode RCOND2
92 {
93 format BranchSplit
94 {
95 0x1: bpreq({{
96 if(Rs1.sdw == 0)
97 NNPC = xc->readPC() + disp;
98 else
99 handle_annul
100 }});
101 0x2: bprle({{
102 if(Rs1.sdw <= 0)
103 NNPC = xc->readPC() + disp;
104 else
105 handle_annul
106 }});
107 0x3: bprl({{
108 if(Rs1.sdw < 0)
109 NNPC = xc->readPC() + disp;
110 else
111 handle_annul
112 }});
113 0x5: bprne({{
114 if(Rs1.sdw != 0)
115 NNPC = xc->readPC() + disp;
116 else
117 handle_annul
118 }});
119 0x6: bprg({{
120 if(Rs1.sdw > 0)
121 NNPC = xc->readPC() + disp;
122 else
123 handle_annul
124 }});
125 0x7: bprge({{
126 if(Rs1.sdw >= 0)
127 NNPC = xc->readPC() + disp;
128 else
129 handle_annul
130 }});
131 }
132 }
133 //SETHI (or NOP if rd == 0 and imm == 0)
134 0x4: SetHi::sethi({{Rd.udw = imm;}});
135 0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
136 0x6: Trap::fbfcc({{fault = new FpDisabled;}});
137 }
138 0x1: BranchN::call(30, {{
139 R15 = xc->readPC();
140 NNPC = R15 + disp;
141 }});
142 0x2: decode OP3 {
143 format IntOp {
144 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
145 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
146 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
147 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
148 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
149 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}});
150 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}});
151 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
152 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
153 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
154 0x0A: umul({{
155 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
156 Y = Rd<63:32>;
157 }});
158 0x0B: smul({{
159 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
160 Y = Rd.sdw;
161 }});
162 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
163 0x0D: udivx({{
164 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
165 else Rd.udw = Rs1.udw / Rs2_or_imm13;
166 }});
167 0x0E: udiv({{
168 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
169 else
170 {
171 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
172 if(Rd.udw >> 32 != 0)
173 Rd.udw = 0xFFFFFFFF;
174 }
175 }});
176 0x0F: sdiv({{
177 if(Rs2_or_imm13.sdw == 0)
178 fault = new DivisionByZero;
179 else
180 {
181 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
182 if(Rd.udw<63:31> != 0)
183 Rd.udw = 0x7FFFFFFF;
184 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
185 Rd.udw = 0xFFFFFFFF80000000ULL;
186 }
187 }});
188 }
189 format IntOpCc {
190 0x10: addcc({{
191 int64_t resTemp, val2 = Rs2_or_imm13;
192 Rd = resTemp = Rs1 + val2;}},
193 {{(Rs1<31:0> + val2<31:0>)<32:>}},
194 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
195 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
196 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
197 );
198 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
199 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
200 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
201 0x14: subcc({{
202 int64_t val2 = Rs2_or_imm13;
203 Rd = Rs1 - val2;}},
204 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
205 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
206 {{(~(Rs1<63:1> + (~val2)<63:1> +
207 (Rs1 | ~val2)<0:>))<63:>}},
208 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
209 );
210 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
211 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
212 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
213 0x18: addccc({{
214 int64_t resTemp, val2 = Rs2_or_imm13;
215 int64_t carryin = Ccr<0:0>;
216 Rd = resTemp = Rs1 + val2 + carryin;}},
217 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
218 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
219 {{(Rs1<63:1> + val2<63:1> +
220 ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
221 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
222 );
223 0x1A: umulcc({{
224 uint64_t resTemp;
225 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
226 Y = resTemp<63:32>;}},
227 {{0}},{{0}},{{0}},{{0}});
228 0x1B: smulcc({{
229 int64_t resTemp;
230 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>;
231 Y = resTemp<63:32>;}},
232 {{0}},{{0}},{{0}},{{0}});
233 0x1C: subccc({{
234 int64_t resTemp, val2 = Rs2_or_imm13;
235 int64_t carryin = Ccr<0:0>;
236 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
237 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
238 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
239 {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
240 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
241 );
242 0x1D: udivxcc({{
243 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
244 else Rd = Rs1.udw / Rs2_or_imm13.udw;}}
245 ,{{0}},{{0}},{{0}},{{0}});
246 0x1E: udivcc({{
247 uint32_t resTemp, val2 = Rs2_or_imm13.udw;
248 int32_t overflow = 0;
249 if(val2 == 0) fault = new DivisionByZero;
250 else
251 {
252 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
253 overflow = (resTemp<63:32> != 0);
254 if(overflow) Rd = resTemp = 0xFFFFFFFF;
255 else Rd = resTemp;
256 } }},
257 {{0}},
258 {{overflow}},
259 {{0}},
260 {{0}}
261 );
262 0x1F: sdivcc({{
263 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
264 bool overflow = false, underflow = false;
265 if(val2 == 0) fault = new DivisionByZero;
266 else
267 {
268 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
269 overflow = (Rd<63:31> != 0);
270 underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF);
271 if(overflow) Rd = 0x7FFFFFFF;
272 else if(underflow) Rd = 0xFFFFFFFF80000000ULL;
273 } }},
274 {{0}},
275 {{overflow || underflow}},
276 {{0}},
277 {{0}}
278 );
279 0x20: taddcc({{
280 int64_t resTemp, val2 = Rs2_or_imm13;
281 Rd = resTemp = Rs1 + val2;
282 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
283 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
284 {{overflow}},
285 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
286 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
287 );
288 0x21: tsubcc({{
289 int64_t resTemp, val2 = Rs2_or_imm13;
290 Rd = resTemp = Rs1 + val2;
291 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
292 {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}},
293 {{overflow}},
294 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
295 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
296 );
297 0x22: taddcctv({{
298 int64_t val2 = Rs2_or_imm13;
299 Rd = Rs1 + val2;
300 int32_t overflow = Rs1<1:0> || val2<1:0> ||
301 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
302 if(overflow) fault = new TagOverflow;}},
303 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
304 {{overflow}},
305 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
306 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}}
307 );
308 0x23: tsubcctv({{
309 int64_t resTemp, val2 = Rs2_or_imm13;
310 Rd = resTemp = Rs1 + val2;
311 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
312 if(overflow) fault = new TagOverflow;}},
313 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
314 {{overflow}},
315 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
316 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
317 );
318 0x24: mulscc({{
319 int64_t resTemp, multiplicand = Rs2_or_imm13;
320 int32_t multiplier = Rs1<31:0>;
321 int32_t savedLSB = Rs1<0:>;
322 multiplier = multiplier<31:1> |
323 ((Ccr<3:3>
324 ^ Ccr<1:1>) << 32);
325 if(!Y<0:>)
326 multiplicand = 0;
327 Rd = resTemp = multiplicand + multiplier;
328 Y = Y<31:1> | (savedLSB << 31);}},
329 {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
330 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
331 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
332 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
333 );
334 }
335 format IntOp
336 {
337 0x25: decode X {
338 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
339 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
340 }
341 0x26: decode X {
342 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
343 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
344 }
345 0x27: decode X {
346 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
347 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
348 }
349 // XXX might want a format rdipr thing here
350 0x28: decode RS1 {
351 0xF: decode I {
352 0x0: Nop::stbar({{/*stuff*/}});
353 0x1: Nop::membar({{/*stuff*/}});
354 }
355 default: rdasr({{
356 Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault);
357 }});
358 }
359 0x29: HPriv::rdhpr({{
360 Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault);
361 }});
362 0x2A: Priv::rdpr({{
363 Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault);
364 }});
365 0x2B: BasicOperate::flushw({{
366 if(NWindows - 2 - Cansave == 0)
367 {
368 if(Otherwin)
369 fault = new SpillNOther(Wstate<5:3>);
370 else
371 fault = new SpillNNormal(Wstate<2:0>);
372 }
373 }});
374 0x2C: decode MOVCC3
375 {
376 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
377 0x1: decode CC
378 {
379 0x0: movcci({{
380 if(passesCondition(Ccr<3:0>, COND4))
381 Rd = Rs2_or_imm11;
382 else
383 Rd = Rd;
384 }});
385 0x2: movccx({{
386 if(passesCondition(Ccr<7:4>, COND4))
387 Rd = Rs2_or_imm11;
388 else
389 Rd = Rd;
390 }});
391 }
392 }
393 0x2D: sdivx({{
394 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
395 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
396 }});
397 0x2E: decode RS1 {
398 0x0: IntOp::popc({{
399 int64_t count = 0;
400 uint64_t temp = Rs2_or_imm13;
401 //Count the 1s in the front 4bits until none are left
402 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
403 while(temp)
404 {
405 count += oneBits[temp & 0xF];
406 temp = temp >> 4;
407 }
408 Rd = count;
409 }});
410 }
411 0x2F: decode RCOND3
412 {
413 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
414 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
415 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
416 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
417 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
418 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
419 }
420 0x30: wrasr({{
421 xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13);
422 }});
423 0x31: decode FCN {
424 0x0: Priv::saved({{
425 assert(Cansave < NWindows - 2);
426 assert(Otherwin || Canrestore);
427 Cansave = Cansave + 1;
428 if(Otherwin == 0)
429 Canrestore = Canrestore - 1;
430 else
431 Otherwin = Otherwin - 1;
432 }});
433 0x1: BasicOperate::restored({{
434 assert(Cansave || Otherwin);
435 assert(Canrestore < NWindows - 2);
436 Canrestore = Canrestore + 1;
437 if(Otherwin == 0)
438 Cansave = Cansave - 1;
439 else
440 Otherwin = Otherwin - 1;
441 }});
442 }
443 0x32: Priv::wrpr({{
444 // XXX Need to protect with format that traps non-priv
445 // access
446 xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13);
447 }});
448 0x33: HPriv::wrhpr({{
449 // XXX Need to protect with format that traps non-priv/priv
450 // access
451 xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
452 }});
453 0x34: decode OPF{
454 format BasicOperate{
455 0x01: fmovs({{
456 Frds.uw = Frs2s.uw;
457 //fsr.ftt = fsr.cexc = 0
458 Fsr &= ~(7 << 14);
459 Fsr &= ~(0x1F);
460 }});
461 0x02: fmovd({{
462 Frd.udw = Frs2.udw;
463 //fsr.ftt = fsr.cexc = 0
464 Fsr &= ~(7 << 14);
465 Fsr &= ~(0x1F);
466 }});
467 0x03: Trap::fmovq({{fault = new FpDisabled;}});
468 0x05: fnegs({{
469 Frds.uw = Frs2s.uw ^ (1UL << 31);
470 //fsr.ftt = fsr.cexc = 0
471 Fsr &= ~(7 << 14);
472 Fsr &= ~(0x1F);
473 }});
474 0x06: fnegd({{
475 Frd.udw = Frs2.udw ^ (1ULL << 63);
476 //fsr.ftt = fsr.cexc = 0
477 Fsr &= ~(7 << 14);
478 Fsr &= ~(0x1F);
479 }});
480 0x07: Trap::fnegq({{fault = new FpDisabled;}});
481 0x09: fabss({{
482 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;
483 //fsr.ftt = fsr.cexc = 0
484 Fsr &= ~(7 << 14);
485 Fsr &= ~(0x1F);
486 }});
487 0x0A: fabsd({{
488 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;
489 //fsr.ftt = fsr.cexc = 0
490 Fsr &= ~(7 << 14);
491 Fsr &= ~(0x1F);
492 }});
493 0x0B: Trap::fabsq({{fault = new FpDisabled;}});
494 0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}});
495 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}});
496 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
497 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
498 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
499 0x43: Trap::faddq({{fault = new FpDisabled;}});
500 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
501 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
502 0x47: Trap::fsubq({{fault = new FpDisabled;}});
503 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
504 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
505 0x4B: Trap::fmulq({{fault = new FpDisabled;}});
506 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
507 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
508 0x4F: Trap::fdivq({{fault = new FpDisabled;}});
509 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
510 0x6E: Trap::fdmulq({{fault = new FpDisabled;}});
511 0x81: fstox({{
512 Frd.df = (double)static_cast<int64_t>(Frs2s.sf);
513 }});
514 0x82: fdtox({{
515 Frd.df = (double)static_cast<int64_t>(Frs2.df);
516 }});
517 0x83: Trap::fqtox({{fault = new FpDisabled;}});
518 0x84: fxtos({{
519 Frds.sf = static_cast<float>((int64_t)Frs2.df);
520 }});
521 0x88: fxtod({{
522 Frd.df = static_cast<double>((int64_t)Frs2.df);
523 }});
524 0x8C: Trap::fxtoq({{fault = new FpDisabled;}});
525 0xC4: fitos({{
526 Frds.sf = static_cast<float>((int32_t)Frs2s.sf);
527 }});
528 0xC6: fdtos({{Frds.sf = Frs2.df;}});
529 0xC7: Trap::fqtos({{fault = new FpDisabled;}});
530 0xC8: fitod({{
531 Frd.df = static_cast<double>((int32_t)Frs2s.sf);
532 }});
533 0xC9: fstod({{Frd.df = Frs2s.sf;}});
534 0xCB: Trap::fqtod({{fault = new FpDisabled;}});
535 0xCC: Trap::fitoq({{fault = new FpDisabled;}});
536 0xCD: Trap::fstoq({{fault = new FpDisabled;}});
537 0xCE: Trap::fdtoq({{fault = new FpDisabled;}});
538 0xD1: fstoi({{
539 Frds.sf = (float)static_cast<int32_t>(Frs2s.sf);
540 }});
541 0xD2: fdtoi({{
542 Frds.sf = (float)static_cast<int32_t>(Frs2.df);
543 }});
544 0xD3: Trap::fqtoi({{fault = new FpDisabled;}});
545 default: Trap::fpop1({{fault = new FpDisabled;}});
546 }
547 }
548 0x35: Trap::fpop2({{fault = new FpDisabled;}});
549 //This used to be just impdep1, but now it's a whole bunch
550 //of instructions
551 0x36: decode OPF{
552 0x00: Trap::edge8({{fault = new IllegalInstruction;}});
553 0x01: Trap::edge8n({{fault = new IllegalInstruction;}});
554 0x02: Trap::edge8l({{fault = new IllegalInstruction;}});
555 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}});
556 0x04: Trap::edge16({{fault = new IllegalInstruction;}});
557 0x05: Trap::edge16n({{fault = new IllegalInstruction;}});
558 0x06: Trap::edge16l({{fault = new IllegalInstruction;}});
559 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}});
560 0x08: Trap::edge32({{fault = new IllegalInstruction;}});
561 0x09: Trap::edge32n({{fault = new IllegalInstruction;}});
562 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}});
563 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}});
564 0x10: Trap::array8({{fault = new IllegalInstruction;}});
565 0x12: Trap::array16({{fault = new IllegalInstruction;}});
566 0x14: Trap::array32({{fault = new IllegalInstruction;}});
567 0x18: BasicOperate::alignaddr({{
568 uint64_t sum = Rs1 + Rs2;
569 Rd = sum & ~7;
570 Gsr = (Gsr & ~7) | (sum & 7);
571 }});
572 0x19: Trap::bmask({{fault = new IllegalInstruction;}});
573 0x1A: BasicOperate::alignaddresslittle({{
574 uint64_t sum = Rs1 + Rs2;
575 Rd = sum & ~7;
576 Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
577 }});
578 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}});
579 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}});
580 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}});
581 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}});
582 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}});
583 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}});
584 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}});
585 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}});
586 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}});
587 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}});
588 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}});
589 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}});
590 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}});
591 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}});
592 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}});
593 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
594 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
595 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
596 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
597 0x48: BasicOperate::faligndata({{
598 uint64_t msbX = Frs1.udw;
599 uint64_t lsbX = Frs2.udw;
600 //Some special cases need to be split out, first
601 //because they're the most likely to be used, and
602 //second because otherwise, we end up shifting by
603 //greater than the width of the type being shifted,
604 //namely 64, which produces undefined results according
605 //to the C standard.
606 switch(Gsr<2:0>)
607 {
608 case 0:
609 Frd.udw = msbX;
610 break;
611 case 8:
612 Frd.udw = lsbX;
613 break;
614 default:
615 uint64_t msbShift = Gsr<2:0> * 8;
616 uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
617 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
618 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
619 Frd.udw = ((msbX & msbMask) << msbShift) |
620 ((lsbX & lsbMask) >> lsbShift);
621 }
622 }});
623 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
624 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}});
625 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}});
626 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}});
627 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}});
628 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}});
629 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}});
630 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}});
631 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}});
632 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}});
633 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}});
634 0x60: BasicOperate::fzero({{Frd.df = 0;}});
635 0x61: BasicOperate::fzeros({{Frds.sf = 0;}});
636 0x62: Trap::fnor({{fault = new IllegalInstruction;}});
637 0x63: Trap::fnors({{fault = new IllegalInstruction;}});
638 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}});
639 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}});
640 0x66: BasicOperate::fnot2({{
641 Frd.df = (double)(~((uint64_t)Frs2.df));
642 }});
643 0x67: BasicOperate::fnot2s({{
644 Frds.sf = (float)(~((uint32_t)Frs2s.sf));
645 }});
646 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}});
647 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}});
648 0x6A: BasicOperate::fnot1({{
649 Frd.df = (double)(~((uint64_t)Frs1.df));
650 }});
651 0x6B: BasicOperate::fnot1s({{
652 Frds.sf = (float)(~((uint32_t)Frs1s.sf));
653 }});
654 0x6C: Trap::fxor({{fault = new IllegalInstruction;}});
655 0x6D: Trap::fxors({{fault = new IllegalInstruction;}});
656 0x6E: Trap::fnand({{fault = new IllegalInstruction;}});
657 0x6F: Trap::fnands({{fault = new IllegalInstruction;}});
658 0x70: Trap::fand({{fault = new IllegalInstruction;}});
659 0x71: Trap::fands({{fault = new IllegalInstruction;}});
660 0x72: Trap::fxnor({{fault = new IllegalInstruction;}});
661 0x73: Trap::fxnors({{fault = new IllegalInstruction;}});
662 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}});
663 0x75: BasicOperate::fsrc1s({{Frd.uw = Frs1.uw;}});
664 0x76: Trap::fornot2({{fault = new IllegalInstruction;}});
665 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}});
666 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}});
667 0x79: BasicOperate::fsrc2s({{Frd.uw = Frs2.uw;}});
668 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}});
669 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}});
670 0x7C: Trap::for({{fault = new IllegalInstruction;}});
671 0x7D: Trap::fors({{fault = new IllegalInstruction;}});
672 0x7E: Trap::fone({{fault = new IllegalInstruction;}});
673 0x7F: Trap::fones({{fault = new IllegalInstruction;}});
674 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
675 0x81: Trap::siam({{fault = new IllegalInstruction;}});
676 }
677 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
678 0x38: Branch::jmpl({{
679 Addr target = Rs1 + Rs2_or_imm13;
680 if(target & 0x3)
681 fault = new MemAddressNotAligned;
682 else
683 {
684 Rd = xc->readPC();
685 NNPC = target;
686 }
687 }});
688 0x39: Branch::return({{
689 //If both MemAddressNotAligned and
690 //a fill trap happen, it's not clear
691 //which one should be returned.
692 Addr target = Rs1 + Rs2_or_imm13;
693 if(target & 0x3)
694 fault = new MemAddressNotAligned;
695 else
696 NNPC = target;
697 if(fault == NoFault)
698 {
699 if(Canrestore == 0)
700 {
701 if(Otherwin)
702 fault = new FillNOther(Wstate<5:3>);
703 else
704 fault = new FillNNormal(Wstate<2:0>);
705 }
706 else
707 {
708 //CWP should be set directly so that it always happens
709 //Also, this will allow writing to the new window and
710 //reading from the old one
711 Cwp = (Cwp - 1 + NWindows) % NWindows;
712 Cansave = Cansave + 1;
713 Canrestore = Canrestore - 1;
714 //This is here to make sure the CWP is written
715 //no matter what. This ensures that the results
716 //are written in the new window as well.
717 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
718 }
719 }
720 }});
721 0x3A: decode CC
722 {
723 0x0: Trap::tcci({{
724 if(passesCondition(Ccr<3:0>, COND2))
725 {
726#if FULL_SYSTEM
727 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
728 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
729 fault = new TrapInstruction(lTrapNum);
730#else
731 DPRINTF(Sparc, "The syscall number is %d\n", R1);
732 xc->syscall(R1);
733#endif
734 }
735 }});
736 0x2: Trap::tccx({{
737 if(passesCondition(Ccr<7:4>, COND2))
738 {
739#if FULL_SYSTEM
740 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
741 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
742 fault = new TrapInstruction(lTrapNum);
743#else
744 DPRINTF(Sparc, "The syscall number is %d\n", R1);
745 xc->syscall(R1);
746#endif
747 }
748 }});
749 }
750 0x3B: Nop::flush({{/*Instruction memory flush*/}});
751 0x3C: save({{
752 //CWP should be set directly so that it always happens
753 //Also, this will allow writing to the new window and
754 //reading from the old one
755 if(Cansave == 0)
756 {
757 if(Otherwin)
758 fault = new SpillNOther(Wstate<5:3>);
759 else
760 fault = new SpillNNormal(Wstate<2:0>);
761 //Cwp = (Cwp + 2) % NWindows;
762 }
763 else if(Cleanwin - Canrestore == 0)
764 {
765 //Cwp = (Cwp + 1) % NWindows;
766 fault = new CleanWindow;
767 }
768 else
769 {
770 Cwp = (Cwp + 1) % NWindows;
771 Rd = Rs1 + Rs2_or_imm13;
772 Cansave = Cansave - 1;
773 Canrestore = Canrestore + 1;
774 //This is here to make sure the CWP is written
775 //no matter what. This ensures that the results
776 //are written in the new window as well.
777 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
778 }
779 }});
780 0x3D: restore({{
781 if(Canrestore == 0)
782 {
783 if(Otherwin)
784 fault = new FillNOther(Wstate<5:3>);
785 else
786 fault = new FillNNormal(Wstate<2:0>);
787 }
788 else
789 {
790 //CWP should be set directly so that it always happens
791 //Also, this will allow writing to the new window and
792 //reading from the old one
793 Cwp = (Cwp - 1 + NWindows) % NWindows;
794 Rd = Rs1 + Rs2_or_imm13;
795 Cansave = Cansave + 1;
796 Canrestore = Canrestore - 1;
797 //This is here to make sure the CWP is written
798 //no matter what. This ensures that the results
799 //are written in the new window as well.
800 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
801 }
802 }});
803 0x3E: decode FCN {
804 0x0: Priv::done({{
805 if(Tl == 0)
806 return new IllegalInstruction;
807
808 Cwp = Tstate<4:0>;
809 Pstate = Tstate<20:8>;
810 Asi = Tstate<31:24>;
811 Ccr = Tstate<39:32>;
812 Gl = Tstate<42:40>;
813 NPC = Tnpc;
814 NNPC = Tnpc + 4;
815 Tl = Tl - 1;
816 }});
817 0x1: Priv::retry({{
818 if(Tl == 0)
819 return new IllegalInstruction;
820 Cwp = Tstate<4:0>;
821 Pstate = Tstate<20:8>;
822 Asi = Tstate<31:24>;
823 Ccr = Tstate<39:32>;
824 Gl = Tstate<42:40>;
825 NPC = Tpc;
826 NNPC = Tnpc;
827 Tl = Tl - 1;
828 }});
829 }
830 }
831 }
832 0x3: decode OP3 {
833 format Load {
834 0x00: lduw({{Rd = Mem.uw;}});
835 0x01: ldub({{Rd = Mem.ub;}});
836 0x02: lduh({{Rd = Mem.uhw;}});
837 0x03: ldd({{
838 uint64_t val = Mem.udw;
839 RdLow = val<31:0>;
840 RdHigh = val<63:32>;
841 }});
842 }
843 format Store {
844 0x04: stw({{Mem.uw = Rd.sw;}});
845 0x05: stb({{Mem.ub = Rd.sb;}});
846 0x06: sth({{Mem.uhw = Rd.shw;}});
847 0x07: std({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
848 }
849 format Load {
850 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
851 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
852 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
853 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
854 }
855 0x0D: LoadStore::ldstub(
856 {{Rd = Mem.ub;}},
857 {{Mem.ub = 0xFF;}});
858 0x0E: Store::stx({{Mem.udw = Rd}});
859 0x0F: LoadStore::swap(
860 {{uReg0 = Rd.uw;
861 Rd.uw = Mem.uw;}},
862 {{Mem.uw = uReg0;}});
863 format Load {
864 0x10: lduwa({{Rd = Mem.uw;}});
865 0x11: lduba({{Rd = Mem.ub;}});
866 0x12: lduha({{Rd = Mem.uhw;}});
867 0x13: ldda({{
868 uint64_t val = Mem.udw;
869 RdLow = val<31:0>;
870 RdHigh = val<63:32>;
871 }});
872 }
873 format Store {
874 0x14: stwa({{Mem.uw = Rd;}});
875 0x15: stba({{Mem.ub = Rd;}});
876 0x16: stha({{Mem.uhw = Rd;}});
877 0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}});
878 }
879 format Load {
880 0x18: ldswa({{Rd = (int32_t)Mem.sw;}});
881 0x19: ldsba({{Rd = (int8_t)Mem.sb;}});
882 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}});
883 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}});
884 }
885 0x1D: LoadStore::ldstuba(
886 {{Rd = Mem.ub;}},
887 {{Mem.ub = 0xFF}});
888 0x1E: Store::stxa({{Mem.udw = Rd}});
889 0x1F: LoadStore::swapa(
890 {{uReg0 = Rd.uw;
891 Rd.uw = Mem.uw;}},
892 {{Mem.uw = uReg0;}});
893 format Trap {
894 0x20: Load::ldf({{Frd.uw = Mem.uw;}});
895 0x21: decode X {
896 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}});
897 0x1: Load::ldxfsr({{Fsr = Mem.udw;}});
898 }
899 0x22: ldqf({{fault = new FpDisabled;}});
900 0x23: Load::lddf({{Frd.udw = Mem.udw;}});
901 0x24: Store::stf({{Mem.uw = Frd.uw;}});
902 0x25: decode X {
903 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}});
904 0x1: Store::stxfsr({{Mem.udw = Fsr;}});
905 }
906 0x26: stqf({{fault = new FpDisabled;}});
907 0x27: Store::stdf({{Mem.udw = Frd.udw;}});
908 0x2D: Nop::prefetch({{ }});
909 0x30: Load::ldfa({{Frd.uw = Mem.uw;}});
910 0x32: ldqfa({{fault = new FpDisabled;}});
911 format LoadAlt {
912 0x33: decode EXT_ASI {
913 //ASI_NUCLEUS
914 0x04: FailUnimpl::lddfa_n();
915 //ASI_NUCLEUS_LITTLE
916 0x0C: FailUnimpl::lddfa_nl();
917 //ASI_AS_IF_USER_PRIMARY
918 0x10: FailUnimpl::lddfa_aiup();
919 //ASI_AS_IF_USER_PRIMARY_LITTLE
920 0x18: FailUnimpl::lddfa_aiupl();
921 //ASI_AS_IF_USER_SECONDARY
922 0x11: FailUnimpl::lddfa_aius();
923 //ASI_AS_IF_USER_SECONDARY_LITTLE
924 0x19: FailUnimpl::lddfa_aiusl();
925 //ASI_REAL
926 0x14: FailUnimpl::lddfa_real();
927 //ASI_REAL_LITTLE
928 0x1C: FailUnimpl::lddfa_real_l();
929 //ASI_REAL_IO
930 0x15: FailUnimpl::lddfa_real_io();
931 //ASI_REAL_IO_LITTLE
932 0x1D: FailUnimpl::lddfa_real_io_l();
933 //ASI_PRIMARY
934 0x80: FailUnimpl::lddfa_p();
935 //ASI_PRIMARY_LITTLE
936 0x88: FailUnimpl::lddfa_pl();
937 //ASI_SECONDARY
938 0x81: FailUnimpl::lddfa_s();
939 //ASI_SECONDARY_LITTLE
940 0x89: FailUnimpl::lddfa_sl();
941 //ASI_PRIMARY_NO_FAULT
942 0x82: FailUnimpl::lddfa_pnf();
943 //ASI_PRIMARY_NO_FAULT_LITTLE
944 0x8A: FailUnimpl::lddfa_pnfl();
945 //ASI_SECONDARY_NO_FAULT
946 0x83: FailUnimpl::lddfa_snf();
947 //ASI_SECONDARY_NO_FAULT_LITTLE
948 0x8B: FailUnimpl::lddfa_snfl();
949
950 format BlockLoad {
951 // LDBLOCKF
952 //ASI_BLOCK_AS_IF_USER_PRIMARY
953 0x16: FailUnimpl::ldblockf_aiup();
954 //ASI_BLOCK_AS_IF_USER_SECONDARY
955 0x17: FailUnimpl::ldblockf_aius();
956 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
957 0x1E: FailUnimpl::ldblockf_aiupl();
958 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
959 0x1F: FailUnimpl::ldblockf_aiusl();
960 //ASI_BLOCK_PRIMARY
961 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}});
962 //ASI_BLOCK_SECONDARY
963 0xF1: FailUnimpl::ldblockf_s();
964 //ASI_BLOCK_PRIMARY_LITTLE
965 0xF8: FailUnimpl::ldblockf_pl();
966 //ASI_BLOCK_SECONDARY_LITTLE
967 0xF9: FailUnimpl::ldblockf_sl();
968 }
969
970 //LDSHORTF
971 //ASI_FL8_PRIMARY
972 0xD0: FailUnimpl::ldshortf_8p();
973 //ASI_FL8_SECONDARY
974 0xD1: FailUnimpl::ldshortf_8s();
975 //ASI_FL8_PRIMARY_LITTLE
976 0xD8: FailUnimpl::ldshortf_8pl();
977 //ASI_FL8_SECONDARY_LITTLE
978 0xD9: FailUnimpl::ldshortf_8sl();
979 //ASI_FL16_PRIMARY
980 0xD2: FailUnimpl::ldshortf_16p();
981 //ASI_FL16_SECONDARY
982 0xD3: FailUnimpl::ldshortf_16s();
983 //ASI_FL16_PRIMARY_LITTLE
984 0xDA: FailUnimpl::ldshortf_16pl();
985 //ASI_FL16_SECONDARY_LITTLE
986 0xDB: FailUnimpl::ldshortf_16sl();
987 //Not an ASI which is legal with lddfa
988 default: Trap::lddfa_bad_asi(
989 {{fault = new DataAccessException;}});
990 }
991 }
992 0x34: Store::stfa({{Mem.uw = Frd.uw;}});
993 0x36: stqfa({{fault = new FpDisabled;}});
994 format StoreAlt {
995 0x37: decode EXT_ASI {
996 //ASI_NUCLEUS
997 0x04: FailUnimpl::stdfa_n();
998 //ASI_NUCLEUS_LITTLE
999 0x0C: FailUnimpl::stdfa_nl();
1000 //ASI_AS_IF_USER_PRIMARY
1001 0x10: FailUnimpl::stdfa_aiup();
1002 //ASI_AS_IF_USER_PRIMARY_LITTLE
1003 0x18: FailUnimpl::stdfa_aiupl();
1004 //ASI_AS_IF_USER_SECONDARY
1005 0x11: FailUnimpl::stdfa_aius();
1006 //ASI_AS_IF_USER_SECONDARY_LITTLE
1007 0x19: FailUnimpl::stdfa_aiusl();
1008 //ASI_REAL
1009 0x14: FailUnimpl::stdfa_real();
1010 //ASI_REAL_LITTLE
1011 0x1C: FailUnimpl::stdfa_real_l();
1012 //ASI_REAL_IO
1013 0x15: FailUnimpl::stdfa_real_io();
1014 //ASI_REAL_IO_LITTLE
1015 0x1D: FailUnimpl::stdfa_real_io_l();
1016 //ASI_PRIMARY
1017 0x80: FailUnimpl::stdfa_p();
1018 //ASI_PRIMARY_LITTLE
1019 0x88: FailUnimpl::stdfa_pl();
1020 //ASI_SECONDARY
1021 0x81: FailUnimpl::stdfa_s();
1022 //ASI_SECONDARY_LITTLE
1023 0x89: FailUnimpl::stdfa_sl();
1024 //ASI_PRIMARY_NO_FAULT
1025 0x82: FailUnimpl::stdfa_pnf();
1026 //ASI_PRIMARY_NO_FAULT_LITTLE
1027 0x8A: FailUnimpl::stdfa_pnfl();
1028 //ASI_SECONDARY_NO_FAULT
1029 0x83: FailUnimpl::stdfa_snf();
1030 //ASI_SECONDARY_NO_FAULT_LITTLE
1031 0x8B: FailUnimpl::stdfa_snfl();
1032
1033 format BlockStore {
1034 // STBLOCKF
1035 //ASI_BLOCK_AS_IF_USER_PRIMARY
1036 0x16: FailUnimpl::stblockf_aiup();
1037 //ASI_BLOCK_AS_IF_USER_SECONDARY
1038 0x17: FailUnimpl::stblockf_aius();
1039 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1040 0x1E: FailUnimpl::stblockf_aiupl();
1041 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1042 0x1F: FailUnimpl::stblockf_aiusl();
1043 //ASI_BLOCK_PRIMARY
1044 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}});
1045 //ASI_BLOCK_SECONDARY
1046 0xF1: FailUnimpl::stblockf_s();
1047 //ASI_BLOCK_PRIMARY_LITTLE
1048 0xF8: FailUnimpl::stblockf_pl();
1049 //ASI_BLOCK_SECONDARY_LITTLE
1050 0xF9: FailUnimpl::stblockf_sl();
1051 }
1052
1053 //STSHORTF
1054 //ASI_FL8_PRIMARY
1055 0xD0: FailUnimpl::stshortf_8p();
1056 //ASI_FL8_SECONDARY
1057 0xD1: FailUnimpl::stshortf_8s();
1058 //ASI_FL8_PRIMARY_LITTLE
1059 0xD8: FailUnimpl::stshortf_8pl();
1060 //ASI_FL8_SECONDARY_LITTLE
1061 0xD9: FailUnimpl::stshortf_8sl();
1062 //ASI_FL16_PRIMARY
1063 0xD2: FailUnimpl::stshortf_16p();
1064 //ASI_FL16_SECONDARY
1065 0xD3: FailUnimpl::stshortf_16s();
1066 //ASI_FL16_PRIMARY_LITTLE
1067 0xDA: FailUnimpl::stshortf_16pl();
1068 //ASI_FL16_SECONDARY_LITTLE
1069 0xDB: FailUnimpl::stshortf_16sl();
1070 //Not an ASI which is legal with lddfa
1071 default: Trap::stdfa_bad_asi(
1072 {{fault = new DataAccessException;}});
1073 }
1074 }
| 1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OP default Unknown::unknown()
37{
38 0x0: decode OP2
39 {
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 0x1: decode COND2
45 {
46 //Branch Always
47 0x8: decode A
48 {
49 0x0: b(19, {{
50 NNPC = xc->readPC() + disp;
51 }});
52 0x1: b(19, {{
53 NPC = xc->readPC() + disp;
54 NNPC = NPC + 4;
55 }}, ',a');
56 }
57 //Branch Never
58 0x0: decode A
59 {
60 0x0: bn(19, {{
61 NNPC = NNPC;//Don't do anything
62 }});
63 0x1: bn(19, {{
64 NPC = xc->readNextPC() + 4;
65 NNPC = NPC + 4;
66 }}, ',a');
67 }
68 default: decode BPCC
69 {
70 0x0: bpcci(19, {{
71 if(passesCondition(Ccr<3:0>, COND2))
72 NNPC = xc->readPC() + disp;
73 else
74 handle_annul
75 }});
76 0x2: bpccx(19, {{
77 if(passesCondition(Ccr<7:4>, COND2))
78 NNPC = xc->readPC() + disp;
79 else
80 handle_annul
81 }});
82 }
83 }
84 0x2: bicc(22, {{
85 if(passesCondition(Ccr<3:0>, COND2))
86 NNPC = xc->readPC() + disp;
87 else
88 handle_annul
89 }});
90 }
91 0x3: decode RCOND2
92 {
93 format BranchSplit
94 {
95 0x1: bpreq({{
96 if(Rs1.sdw == 0)
97 NNPC = xc->readPC() + disp;
98 else
99 handle_annul
100 }});
101 0x2: bprle({{
102 if(Rs1.sdw <= 0)
103 NNPC = xc->readPC() + disp;
104 else
105 handle_annul
106 }});
107 0x3: bprl({{
108 if(Rs1.sdw < 0)
109 NNPC = xc->readPC() + disp;
110 else
111 handle_annul
112 }});
113 0x5: bprne({{
114 if(Rs1.sdw != 0)
115 NNPC = xc->readPC() + disp;
116 else
117 handle_annul
118 }});
119 0x6: bprg({{
120 if(Rs1.sdw > 0)
121 NNPC = xc->readPC() + disp;
122 else
123 handle_annul
124 }});
125 0x7: bprge({{
126 if(Rs1.sdw >= 0)
127 NNPC = xc->readPC() + disp;
128 else
129 handle_annul
130 }});
131 }
132 }
133 //SETHI (or NOP if rd == 0 and imm == 0)
134 0x4: SetHi::sethi({{Rd.udw = imm;}});
135 0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
136 0x6: Trap::fbfcc({{fault = new FpDisabled;}});
137 }
138 0x1: BranchN::call(30, {{
139 R15 = xc->readPC();
140 NNPC = R15 + disp;
141 }});
142 0x2: decode OP3 {
143 format IntOp {
144 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
145 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
146 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
147 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
148 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
149 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}});
150 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}});
151 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
152 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
153 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
154 0x0A: umul({{
155 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
156 Y = Rd<63:32>;
157 }});
158 0x0B: smul({{
159 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
160 Y = Rd.sdw;
161 }});
162 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
163 0x0D: udivx({{
164 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
165 else Rd.udw = Rs1.udw / Rs2_or_imm13;
166 }});
167 0x0E: udiv({{
168 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
169 else
170 {
171 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
172 if(Rd.udw >> 32 != 0)
173 Rd.udw = 0xFFFFFFFF;
174 }
175 }});
176 0x0F: sdiv({{
177 if(Rs2_or_imm13.sdw == 0)
178 fault = new DivisionByZero;
179 else
180 {
181 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
182 if(Rd.udw<63:31> != 0)
183 Rd.udw = 0x7FFFFFFF;
184 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
185 Rd.udw = 0xFFFFFFFF80000000ULL;
186 }
187 }});
188 }
189 format IntOpCc {
190 0x10: addcc({{
191 int64_t resTemp, val2 = Rs2_or_imm13;
192 Rd = resTemp = Rs1 + val2;}},
193 {{(Rs1<31:0> + val2<31:0>)<32:>}},
194 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
195 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
196 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
197 );
198 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
199 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
200 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
201 0x14: subcc({{
202 int64_t val2 = Rs2_or_imm13;
203 Rd = Rs1 - val2;}},
204 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
205 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
206 {{(~(Rs1<63:1> + (~val2)<63:1> +
207 (Rs1 | ~val2)<0:>))<63:>}},
208 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
209 );
210 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
211 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
212 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
213 0x18: addccc({{
214 int64_t resTemp, val2 = Rs2_or_imm13;
215 int64_t carryin = Ccr<0:0>;
216 Rd = resTemp = Rs1 + val2 + carryin;}},
217 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
218 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
219 {{(Rs1<63:1> + val2<63:1> +
220 ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
221 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
222 );
223 0x1A: umulcc({{
224 uint64_t resTemp;
225 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
226 Y = resTemp<63:32>;}},
227 {{0}},{{0}},{{0}},{{0}});
228 0x1B: smulcc({{
229 int64_t resTemp;
230 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>;
231 Y = resTemp<63:32>;}},
232 {{0}},{{0}},{{0}},{{0}});
233 0x1C: subccc({{
234 int64_t resTemp, val2 = Rs2_or_imm13;
235 int64_t carryin = Ccr<0:0>;
236 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
237 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
238 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
239 {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
240 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
241 );
242 0x1D: udivxcc({{
243 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
244 else Rd = Rs1.udw / Rs2_or_imm13.udw;}}
245 ,{{0}},{{0}},{{0}},{{0}});
246 0x1E: udivcc({{
247 uint32_t resTemp, val2 = Rs2_or_imm13.udw;
248 int32_t overflow = 0;
249 if(val2 == 0) fault = new DivisionByZero;
250 else
251 {
252 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
253 overflow = (resTemp<63:32> != 0);
254 if(overflow) Rd = resTemp = 0xFFFFFFFF;
255 else Rd = resTemp;
256 } }},
257 {{0}},
258 {{overflow}},
259 {{0}},
260 {{0}}
261 );
262 0x1F: sdivcc({{
263 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
264 bool overflow = false, underflow = false;
265 if(val2 == 0) fault = new DivisionByZero;
266 else
267 {
268 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
269 overflow = (Rd<63:31> != 0);
270 underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF);
271 if(overflow) Rd = 0x7FFFFFFF;
272 else if(underflow) Rd = 0xFFFFFFFF80000000ULL;
273 } }},
274 {{0}},
275 {{overflow || underflow}},
276 {{0}},
277 {{0}}
278 );
279 0x20: taddcc({{
280 int64_t resTemp, val2 = Rs2_or_imm13;
281 Rd = resTemp = Rs1 + val2;
282 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
283 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
284 {{overflow}},
285 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
286 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
287 );
288 0x21: tsubcc({{
289 int64_t resTemp, val2 = Rs2_or_imm13;
290 Rd = resTemp = Rs1 + val2;
291 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
292 {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}},
293 {{overflow}},
294 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
295 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
296 );
297 0x22: taddcctv({{
298 int64_t val2 = Rs2_or_imm13;
299 Rd = Rs1 + val2;
300 int32_t overflow = Rs1<1:0> || val2<1:0> ||
301 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
302 if(overflow) fault = new TagOverflow;}},
303 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
304 {{overflow}},
305 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
306 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}}
307 );
308 0x23: tsubcctv({{
309 int64_t resTemp, val2 = Rs2_or_imm13;
310 Rd = resTemp = Rs1 + val2;
311 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
312 if(overflow) fault = new TagOverflow;}},
313 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
314 {{overflow}},
315 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
316 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
317 );
318 0x24: mulscc({{
319 int64_t resTemp, multiplicand = Rs2_or_imm13;
320 int32_t multiplier = Rs1<31:0>;
321 int32_t savedLSB = Rs1<0:>;
322 multiplier = multiplier<31:1> |
323 ((Ccr<3:3>
324 ^ Ccr<1:1>) << 32);
325 if(!Y<0:>)
326 multiplicand = 0;
327 Rd = resTemp = multiplicand + multiplier;
328 Y = Y<31:1> | (savedLSB << 31);}},
329 {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
330 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
331 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
332 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
333 );
334 }
335 format IntOp
336 {
337 0x25: decode X {
338 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
339 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
340 }
341 0x26: decode X {
342 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
343 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
344 }
345 0x27: decode X {
346 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
347 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
348 }
349 // XXX might want a format rdipr thing here
350 0x28: decode RS1 {
351 0xF: decode I {
352 0x0: Nop::stbar({{/*stuff*/}});
353 0x1: Nop::membar({{/*stuff*/}});
354 }
355 default: rdasr({{
356 Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault);
357 }});
358 }
359 0x29: HPriv::rdhpr({{
360 Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault);
361 }});
362 0x2A: Priv::rdpr({{
363 Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault);
364 }});
365 0x2B: BasicOperate::flushw({{
366 if(NWindows - 2 - Cansave == 0)
367 {
368 if(Otherwin)
369 fault = new SpillNOther(Wstate<5:3>);
370 else
371 fault = new SpillNNormal(Wstate<2:0>);
372 }
373 }});
374 0x2C: decode MOVCC3
375 {
376 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
377 0x1: decode CC
378 {
379 0x0: movcci({{
380 if(passesCondition(Ccr<3:0>, COND4))
381 Rd = Rs2_or_imm11;
382 else
383 Rd = Rd;
384 }});
385 0x2: movccx({{
386 if(passesCondition(Ccr<7:4>, COND4))
387 Rd = Rs2_or_imm11;
388 else
389 Rd = Rd;
390 }});
391 }
392 }
393 0x2D: sdivx({{
394 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
395 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
396 }});
397 0x2E: decode RS1 {
398 0x0: IntOp::popc({{
399 int64_t count = 0;
400 uint64_t temp = Rs2_or_imm13;
401 //Count the 1s in the front 4bits until none are left
402 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
403 while(temp)
404 {
405 count += oneBits[temp & 0xF];
406 temp = temp >> 4;
407 }
408 Rd = count;
409 }});
410 }
411 0x2F: decode RCOND3
412 {
413 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
414 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
415 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
416 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
417 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
418 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
419 }
420 0x30: wrasr({{
421 xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13);
422 }});
423 0x31: decode FCN {
424 0x0: Priv::saved({{
425 assert(Cansave < NWindows - 2);
426 assert(Otherwin || Canrestore);
427 Cansave = Cansave + 1;
428 if(Otherwin == 0)
429 Canrestore = Canrestore - 1;
430 else
431 Otherwin = Otherwin - 1;
432 }});
433 0x1: BasicOperate::restored({{
434 assert(Cansave || Otherwin);
435 assert(Canrestore < NWindows - 2);
436 Canrestore = Canrestore + 1;
437 if(Otherwin == 0)
438 Cansave = Cansave - 1;
439 else
440 Otherwin = Otherwin - 1;
441 }});
442 }
443 0x32: Priv::wrpr({{
444 // XXX Need to protect with format that traps non-priv
445 // access
446 xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13);
447 }});
448 0x33: HPriv::wrhpr({{
449 // XXX Need to protect with format that traps non-priv/priv
450 // access
451 xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
452 }});
453 0x34: decode OPF{
454 format BasicOperate{
455 0x01: fmovs({{
456 Frds.uw = Frs2s.uw;
457 //fsr.ftt = fsr.cexc = 0
458 Fsr &= ~(7 << 14);
459 Fsr &= ~(0x1F);
460 }});
461 0x02: fmovd({{
462 Frd.udw = Frs2.udw;
463 //fsr.ftt = fsr.cexc = 0
464 Fsr &= ~(7 << 14);
465 Fsr &= ~(0x1F);
466 }});
467 0x03: Trap::fmovq({{fault = new FpDisabled;}});
468 0x05: fnegs({{
469 Frds.uw = Frs2s.uw ^ (1UL << 31);
470 //fsr.ftt = fsr.cexc = 0
471 Fsr &= ~(7 << 14);
472 Fsr &= ~(0x1F);
473 }});
474 0x06: fnegd({{
475 Frd.udw = Frs2.udw ^ (1ULL << 63);
476 //fsr.ftt = fsr.cexc = 0
477 Fsr &= ~(7 << 14);
478 Fsr &= ~(0x1F);
479 }});
480 0x07: Trap::fnegq({{fault = new FpDisabled;}});
481 0x09: fabss({{
482 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;
483 //fsr.ftt = fsr.cexc = 0
484 Fsr &= ~(7 << 14);
485 Fsr &= ~(0x1F);
486 }});
487 0x0A: fabsd({{
488 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;
489 //fsr.ftt = fsr.cexc = 0
490 Fsr &= ~(7 << 14);
491 Fsr &= ~(0x1F);
492 }});
493 0x0B: Trap::fabsq({{fault = new FpDisabled;}});
494 0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}});
495 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}});
496 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
497 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
498 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
499 0x43: Trap::faddq({{fault = new FpDisabled;}});
500 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
501 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
502 0x47: Trap::fsubq({{fault = new FpDisabled;}});
503 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
504 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
505 0x4B: Trap::fmulq({{fault = new FpDisabled;}});
506 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
507 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
508 0x4F: Trap::fdivq({{fault = new FpDisabled;}});
509 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
510 0x6E: Trap::fdmulq({{fault = new FpDisabled;}});
511 0x81: fstox({{
512 Frd.df = (double)static_cast<int64_t>(Frs2s.sf);
513 }});
514 0x82: fdtox({{
515 Frd.df = (double)static_cast<int64_t>(Frs2.df);
516 }});
517 0x83: Trap::fqtox({{fault = new FpDisabled;}});
518 0x84: fxtos({{
519 Frds.sf = static_cast<float>((int64_t)Frs2.df);
520 }});
521 0x88: fxtod({{
522 Frd.df = static_cast<double>((int64_t)Frs2.df);
523 }});
524 0x8C: Trap::fxtoq({{fault = new FpDisabled;}});
525 0xC4: fitos({{
526 Frds.sf = static_cast<float>((int32_t)Frs2s.sf);
527 }});
528 0xC6: fdtos({{Frds.sf = Frs2.df;}});
529 0xC7: Trap::fqtos({{fault = new FpDisabled;}});
530 0xC8: fitod({{
531 Frd.df = static_cast<double>((int32_t)Frs2s.sf);
532 }});
533 0xC9: fstod({{Frd.df = Frs2s.sf;}});
534 0xCB: Trap::fqtod({{fault = new FpDisabled;}});
535 0xCC: Trap::fitoq({{fault = new FpDisabled;}});
536 0xCD: Trap::fstoq({{fault = new FpDisabled;}});
537 0xCE: Trap::fdtoq({{fault = new FpDisabled;}});
538 0xD1: fstoi({{
539 Frds.sf = (float)static_cast<int32_t>(Frs2s.sf);
540 }});
541 0xD2: fdtoi({{
542 Frds.sf = (float)static_cast<int32_t>(Frs2.df);
543 }});
544 0xD3: Trap::fqtoi({{fault = new FpDisabled;}});
545 default: Trap::fpop1({{fault = new FpDisabled;}});
546 }
547 }
548 0x35: Trap::fpop2({{fault = new FpDisabled;}});
549 //This used to be just impdep1, but now it's a whole bunch
550 //of instructions
551 0x36: decode OPF{
552 0x00: Trap::edge8({{fault = new IllegalInstruction;}});
553 0x01: Trap::edge8n({{fault = new IllegalInstruction;}});
554 0x02: Trap::edge8l({{fault = new IllegalInstruction;}});
555 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}});
556 0x04: Trap::edge16({{fault = new IllegalInstruction;}});
557 0x05: Trap::edge16n({{fault = new IllegalInstruction;}});
558 0x06: Trap::edge16l({{fault = new IllegalInstruction;}});
559 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}});
560 0x08: Trap::edge32({{fault = new IllegalInstruction;}});
561 0x09: Trap::edge32n({{fault = new IllegalInstruction;}});
562 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}});
563 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}});
564 0x10: Trap::array8({{fault = new IllegalInstruction;}});
565 0x12: Trap::array16({{fault = new IllegalInstruction;}});
566 0x14: Trap::array32({{fault = new IllegalInstruction;}});
567 0x18: BasicOperate::alignaddr({{
568 uint64_t sum = Rs1 + Rs2;
569 Rd = sum & ~7;
570 Gsr = (Gsr & ~7) | (sum & 7);
571 }});
572 0x19: Trap::bmask({{fault = new IllegalInstruction;}});
573 0x1A: BasicOperate::alignaddresslittle({{
574 uint64_t sum = Rs1 + Rs2;
575 Rd = sum & ~7;
576 Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
577 }});
578 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}});
579 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}});
580 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}});
581 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}});
582 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}});
583 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}});
584 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}});
585 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}});
586 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}});
587 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}});
588 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}});
589 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}});
590 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}});
591 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}});
592 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}});
593 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
594 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
595 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
596 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
597 0x48: BasicOperate::faligndata({{
598 uint64_t msbX = Frs1.udw;
599 uint64_t lsbX = Frs2.udw;
600 //Some special cases need to be split out, first
601 //because they're the most likely to be used, and
602 //second because otherwise, we end up shifting by
603 //greater than the width of the type being shifted,
604 //namely 64, which produces undefined results according
605 //to the C standard.
606 switch(Gsr<2:0>)
607 {
608 case 0:
609 Frd.udw = msbX;
610 break;
611 case 8:
612 Frd.udw = lsbX;
613 break;
614 default:
615 uint64_t msbShift = Gsr<2:0> * 8;
616 uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
617 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
618 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
619 Frd.udw = ((msbX & msbMask) << msbShift) |
620 ((lsbX & lsbMask) >> lsbShift);
621 }
622 }});
623 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
624 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}});
625 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}});
626 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}});
627 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}});
628 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}});
629 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}});
630 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}});
631 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}});
632 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}});
633 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}});
634 0x60: BasicOperate::fzero({{Frd.df = 0;}});
635 0x61: BasicOperate::fzeros({{Frds.sf = 0;}});
636 0x62: Trap::fnor({{fault = new IllegalInstruction;}});
637 0x63: Trap::fnors({{fault = new IllegalInstruction;}});
638 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}});
639 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}});
640 0x66: BasicOperate::fnot2({{
641 Frd.df = (double)(~((uint64_t)Frs2.df));
642 }});
643 0x67: BasicOperate::fnot2s({{
644 Frds.sf = (float)(~((uint32_t)Frs2s.sf));
645 }});
646 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}});
647 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}});
648 0x6A: BasicOperate::fnot1({{
649 Frd.df = (double)(~((uint64_t)Frs1.df));
650 }});
651 0x6B: BasicOperate::fnot1s({{
652 Frds.sf = (float)(~((uint32_t)Frs1s.sf));
653 }});
654 0x6C: Trap::fxor({{fault = new IllegalInstruction;}});
655 0x6D: Trap::fxors({{fault = new IllegalInstruction;}});
656 0x6E: Trap::fnand({{fault = new IllegalInstruction;}});
657 0x6F: Trap::fnands({{fault = new IllegalInstruction;}});
658 0x70: Trap::fand({{fault = new IllegalInstruction;}});
659 0x71: Trap::fands({{fault = new IllegalInstruction;}});
660 0x72: Trap::fxnor({{fault = new IllegalInstruction;}});
661 0x73: Trap::fxnors({{fault = new IllegalInstruction;}});
662 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}});
663 0x75: BasicOperate::fsrc1s({{Frd.uw = Frs1.uw;}});
664 0x76: Trap::fornot2({{fault = new IllegalInstruction;}});
665 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}});
666 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}});
667 0x79: BasicOperate::fsrc2s({{Frd.uw = Frs2.uw;}});
668 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}});
669 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}});
670 0x7C: Trap::for({{fault = new IllegalInstruction;}});
671 0x7D: Trap::fors({{fault = new IllegalInstruction;}});
672 0x7E: Trap::fone({{fault = new IllegalInstruction;}});
673 0x7F: Trap::fones({{fault = new IllegalInstruction;}});
674 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
675 0x81: Trap::siam({{fault = new IllegalInstruction;}});
676 }
677 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
678 0x38: Branch::jmpl({{
679 Addr target = Rs1 + Rs2_or_imm13;
680 if(target & 0x3)
681 fault = new MemAddressNotAligned;
682 else
683 {
684 Rd = xc->readPC();
685 NNPC = target;
686 }
687 }});
688 0x39: Branch::return({{
689 //If both MemAddressNotAligned and
690 //a fill trap happen, it's not clear
691 //which one should be returned.
692 Addr target = Rs1 + Rs2_or_imm13;
693 if(target & 0x3)
694 fault = new MemAddressNotAligned;
695 else
696 NNPC = target;
697 if(fault == NoFault)
698 {
699 if(Canrestore == 0)
700 {
701 if(Otherwin)
702 fault = new FillNOther(Wstate<5:3>);
703 else
704 fault = new FillNNormal(Wstate<2:0>);
705 }
706 else
707 {
708 //CWP should be set directly so that it always happens
709 //Also, this will allow writing to the new window and
710 //reading from the old one
711 Cwp = (Cwp - 1 + NWindows) % NWindows;
712 Cansave = Cansave + 1;
713 Canrestore = Canrestore - 1;
714 //This is here to make sure the CWP is written
715 //no matter what. This ensures that the results
716 //are written in the new window as well.
717 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
718 }
719 }
720 }});
721 0x3A: decode CC
722 {
723 0x0: Trap::tcci({{
724 if(passesCondition(Ccr<3:0>, COND2))
725 {
726#if FULL_SYSTEM
727 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
728 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
729 fault = new TrapInstruction(lTrapNum);
730#else
731 DPRINTF(Sparc, "The syscall number is %d\n", R1);
732 xc->syscall(R1);
733#endif
734 }
735 }});
736 0x2: Trap::tccx({{
737 if(passesCondition(Ccr<7:4>, COND2))
738 {
739#if FULL_SYSTEM
740 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
741 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
742 fault = new TrapInstruction(lTrapNum);
743#else
744 DPRINTF(Sparc, "The syscall number is %d\n", R1);
745 xc->syscall(R1);
746#endif
747 }
748 }});
749 }
750 0x3B: Nop::flush({{/*Instruction memory flush*/}});
751 0x3C: save({{
752 //CWP should be set directly so that it always happens
753 //Also, this will allow writing to the new window and
754 //reading from the old one
755 if(Cansave == 0)
756 {
757 if(Otherwin)
758 fault = new SpillNOther(Wstate<5:3>);
759 else
760 fault = new SpillNNormal(Wstate<2:0>);
761 //Cwp = (Cwp + 2) % NWindows;
762 }
763 else if(Cleanwin - Canrestore == 0)
764 {
765 //Cwp = (Cwp + 1) % NWindows;
766 fault = new CleanWindow;
767 }
768 else
769 {
770 Cwp = (Cwp + 1) % NWindows;
771 Rd = Rs1 + Rs2_or_imm13;
772 Cansave = Cansave - 1;
773 Canrestore = Canrestore + 1;
774 //This is here to make sure the CWP is written
775 //no matter what. This ensures that the results
776 //are written in the new window as well.
777 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
778 }
779 }});
780 0x3D: restore({{
781 if(Canrestore == 0)
782 {
783 if(Otherwin)
784 fault = new FillNOther(Wstate<5:3>);
785 else
786 fault = new FillNNormal(Wstate<2:0>);
787 }
788 else
789 {
790 //CWP should be set directly so that it always happens
791 //Also, this will allow writing to the new window and
792 //reading from the old one
793 Cwp = (Cwp - 1 + NWindows) % NWindows;
794 Rd = Rs1 + Rs2_or_imm13;
795 Cansave = Cansave + 1;
796 Canrestore = Canrestore - 1;
797 //This is here to make sure the CWP is written
798 //no matter what. This ensures that the results
799 //are written in the new window as well.
800 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
801 }
802 }});
803 0x3E: decode FCN {
804 0x0: Priv::done({{
805 if(Tl == 0)
806 return new IllegalInstruction;
807
808 Cwp = Tstate<4:0>;
809 Pstate = Tstate<20:8>;
810 Asi = Tstate<31:24>;
811 Ccr = Tstate<39:32>;
812 Gl = Tstate<42:40>;
813 NPC = Tnpc;
814 NNPC = Tnpc + 4;
815 Tl = Tl - 1;
816 }});
817 0x1: Priv::retry({{
818 if(Tl == 0)
819 return new IllegalInstruction;
820 Cwp = Tstate<4:0>;
821 Pstate = Tstate<20:8>;
822 Asi = Tstate<31:24>;
823 Ccr = Tstate<39:32>;
824 Gl = Tstate<42:40>;
825 NPC = Tpc;
826 NNPC = Tnpc;
827 Tl = Tl - 1;
828 }});
829 }
830 }
831 }
832 0x3: decode OP3 {
833 format Load {
834 0x00: lduw({{Rd = Mem.uw;}});
835 0x01: ldub({{Rd = Mem.ub;}});
836 0x02: lduh({{Rd = Mem.uhw;}});
837 0x03: ldd({{
838 uint64_t val = Mem.udw;
839 RdLow = val<31:0>;
840 RdHigh = val<63:32>;
841 }});
842 }
843 format Store {
844 0x04: stw({{Mem.uw = Rd.sw;}});
845 0x05: stb({{Mem.ub = Rd.sb;}});
846 0x06: sth({{Mem.uhw = Rd.shw;}});
847 0x07: std({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
848 }
849 format Load {
850 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
851 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
852 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
853 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
854 }
855 0x0D: LoadStore::ldstub(
856 {{Rd = Mem.ub;}},
857 {{Mem.ub = 0xFF;}});
858 0x0E: Store::stx({{Mem.udw = Rd}});
859 0x0F: LoadStore::swap(
860 {{uReg0 = Rd.uw;
861 Rd.uw = Mem.uw;}},
862 {{Mem.uw = uReg0;}});
863 format Load {
864 0x10: lduwa({{Rd = Mem.uw;}});
865 0x11: lduba({{Rd = Mem.ub;}});
866 0x12: lduha({{Rd = Mem.uhw;}});
867 0x13: ldda({{
868 uint64_t val = Mem.udw;
869 RdLow = val<31:0>;
870 RdHigh = val<63:32>;
871 }});
872 }
873 format Store {
874 0x14: stwa({{Mem.uw = Rd;}});
875 0x15: stba({{Mem.ub = Rd;}});
876 0x16: stha({{Mem.uhw = Rd;}});
877 0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}});
878 }
879 format Load {
880 0x18: ldswa({{Rd = (int32_t)Mem.sw;}});
881 0x19: ldsba({{Rd = (int8_t)Mem.sb;}});
882 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}});
883 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}});
884 }
885 0x1D: LoadStore::ldstuba(
886 {{Rd = Mem.ub;}},
887 {{Mem.ub = 0xFF}});
888 0x1E: Store::stxa({{Mem.udw = Rd}});
889 0x1F: LoadStore::swapa(
890 {{uReg0 = Rd.uw;
891 Rd.uw = Mem.uw;}},
892 {{Mem.uw = uReg0;}});
893 format Trap {
894 0x20: Load::ldf({{Frd.uw = Mem.uw;}});
895 0x21: decode X {
896 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}});
897 0x1: Load::ldxfsr({{Fsr = Mem.udw;}});
898 }
899 0x22: ldqf({{fault = new FpDisabled;}});
900 0x23: Load::lddf({{Frd.udw = Mem.udw;}});
901 0x24: Store::stf({{Mem.uw = Frd.uw;}});
902 0x25: decode X {
903 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}});
904 0x1: Store::stxfsr({{Mem.udw = Fsr;}});
905 }
906 0x26: stqf({{fault = new FpDisabled;}});
907 0x27: Store::stdf({{Mem.udw = Frd.udw;}});
908 0x2D: Nop::prefetch({{ }});
909 0x30: Load::ldfa({{Frd.uw = Mem.uw;}});
910 0x32: ldqfa({{fault = new FpDisabled;}});
911 format LoadAlt {
912 0x33: decode EXT_ASI {
913 //ASI_NUCLEUS
914 0x04: FailUnimpl::lddfa_n();
915 //ASI_NUCLEUS_LITTLE
916 0x0C: FailUnimpl::lddfa_nl();
917 //ASI_AS_IF_USER_PRIMARY
918 0x10: FailUnimpl::lddfa_aiup();
919 //ASI_AS_IF_USER_PRIMARY_LITTLE
920 0x18: FailUnimpl::lddfa_aiupl();
921 //ASI_AS_IF_USER_SECONDARY
922 0x11: FailUnimpl::lddfa_aius();
923 //ASI_AS_IF_USER_SECONDARY_LITTLE
924 0x19: FailUnimpl::lddfa_aiusl();
925 //ASI_REAL
926 0x14: FailUnimpl::lddfa_real();
927 //ASI_REAL_LITTLE
928 0x1C: FailUnimpl::lddfa_real_l();
929 //ASI_REAL_IO
930 0x15: FailUnimpl::lddfa_real_io();
931 //ASI_REAL_IO_LITTLE
932 0x1D: FailUnimpl::lddfa_real_io_l();
933 //ASI_PRIMARY
934 0x80: FailUnimpl::lddfa_p();
935 //ASI_PRIMARY_LITTLE
936 0x88: FailUnimpl::lddfa_pl();
937 //ASI_SECONDARY
938 0x81: FailUnimpl::lddfa_s();
939 //ASI_SECONDARY_LITTLE
940 0x89: FailUnimpl::lddfa_sl();
941 //ASI_PRIMARY_NO_FAULT
942 0x82: FailUnimpl::lddfa_pnf();
943 //ASI_PRIMARY_NO_FAULT_LITTLE
944 0x8A: FailUnimpl::lddfa_pnfl();
945 //ASI_SECONDARY_NO_FAULT
946 0x83: FailUnimpl::lddfa_snf();
947 //ASI_SECONDARY_NO_FAULT_LITTLE
948 0x8B: FailUnimpl::lddfa_snfl();
949
950 format BlockLoad {
951 // LDBLOCKF
952 //ASI_BLOCK_AS_IF_USER_PRIMARY
953 0x16: FailUnimpl::ldblockf_aiup();
954 //ASI_BLOCK_AS_IF_USER_SECONDARY
955 0x17: FailUnimpl::ldblockf_aius();
956 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
957 0x1E: FailUnimpl::ldblockf_aiupl();
958 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
959 0x1F: FailUnimpl::ldblockf_aiusl();
960 //ASI_BLOCK_PRIMARY
961 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}});
962 //ASI_BLOCK_SECONDARY
963 0xF1: FailUnimpl::ldblockf_s();
964 //ASI_BLOCK_PRIMARY_LITTLE
965 0xF8: FailUnimpl::ldblockf_pl();
966 //ASI_BLOCK_SECONDARY_LITTLE
967 0xF9: FailUnimpl::ldblockf_sl();
968 }
969
970 //LDSHORTF
971 //ASI_FL8_PRIMARY
972 0xD0: FailUnimpl::ldshortf_8p();
973 //ASI_FL8_SECONDARY
974 0xD1: FailUnimpl::ldshortf_8s();
975 //ASI_FL8_PRIMARY_LITTLE
976 0xD8: FailUnimpl::ldshortf_8pl();
977 //ASI_FL8_SECONDARY_LITTLE
978 0xD9: FailUnimpl::ldshortf_8sl();
979 //ASI_FL16_PRIMARY
980 0xD2: FailUnimpl::ldshortf_16p();
981 //ASI_FL16_SECONDARY
982 0xD3: FailUnimpl::ldshortf_16s();
983 //ASI_FL16_PRIMARY_LITTLE
984 0xDA: FailUnimpl::ldshortf_16pl();
985 //ASI_FL16_SECONDARY_LITTLE
986 0xDB: FailUnimpl::ldshortf_16sl();
987 //Not an ASI which is legal with lddfa
988 default: Trap::lddfa_bad_asi(
989 {{fault = new DataAccessException;}});
990 }
991 }
992 0x34: Store::stfa({{Mem.uw = Frd.uw;}});
993 0x36: stqfa({{fault = new FpDisabled;}});
994 format StoreAlt {
995 0x37: decode EXT_ASI {
996 //ASI_NUCLEUS
997 0x04: FailUnimpl::stdfa_n();
998 //ASI_NUCLEUS_LITTLE
999 0x0C: FailUnimpl::stdfa_nl();
1000 //ASI_AS_IF_USER_PRIMARY
1001 0x10: FailUnimpl::stdfa_aiup();
1002 //ASI_AS_IF_USER_PRIMARY_LITTLE
1003 0x18: FailUnimpl::stdfa_aiupl();
1004 //ASI_AS_IF_USER_SECONDARY
1005 0x11: FailUnimpl::stdfa_aius();
1006 //ASI_AS_IF_USER_SECONDARY_LITTLE
1007 0x19: FailUnimpl::stdfa_aiusl();
1008 //ASI_REAL
1009 0x14: FailUnimpl::stdfa_real();
1010 //ASI_REAL_LITTLE
1011 0x1C: FailUnimpl::stdfa_real_l();
1012 //ASI_REAL_IO
1013 0x15: FailUnimpl::stdfa_real_io();
1014 //ASI_REAL_IO_LITTLE
1015 0x1D: FailUnimpl::stdfa_real_io_l();
1016 //ASI_PRIMARY
1017 0x80: FailUnimpl::stdfa_p();
1018 //ASI_PRIMARY_LITTLE
1019 0x88: FailUnimpl::stdfa_pl();
1020 //ASI_SECONDARY
1021 0x81: FailUnimpl::stdfa_s();
1022 //ASI_SECONDARY_LITTLE
1023 0x89: FailUnimpl::stdfa_sl();
1024 //ASI_PRIMARY_NO_FAULT
1025 0x82: FailUnimpl::stdfa_pnf();
1026 //ASI_PRIMARY_NO_FAULT_LITTLE
1027 0x8A: FailUnimpl::stdfa_pnfl();
1028 //ASI_SECONDARY_NO_FAULT
1029 0x83: FailUnimpl::stdfa_snf();
1030 //ASI_SECONDARY_NO_FAULT_LITTLE
1031 0x8B: FailUnimpl::stdfa_snfl();
1032
1033 format BlockStore {
1034 // STBLOCKF
1035 //ASI_BLOCK_AS_IF_USER_PRIMARY
1036 0x16: FailUnimpl::stblockf_aiup();
1037 //ASI_BLOCK_AS_IF_USER_SECONDARY
1038 0x17: FailUnimpl::stblockf_aius();
1039 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1040 0x1E: FailUnimpl::stblockf_aiupl();
1041 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1042 0x1F: FailUnimpl::stblockf_aiusl();
1043 //ASI_BLOCK_PRIMARY
1044 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}});
1045 //ASI_BLOCK_SECONDARY
1046 0xF1: FailUnimpl::stblockf_s();
1047 //ASI_BLOCK_PRIMARY_LITTLE
1048 0xF8: FailUnimpl::stblockf_pl();
1049 //ASI_BLOCK_SECONDARY_LITTLE
1050 0xF9: FailUnimpl::stblockf_sl();
1051 }
1052
1053 //STSHORTF
1054 //ASI_FL8_PRIMARY
1055 0xD0: FailUnimpl::stshortf_8p();
1056 //ASI_FL8_SECONDARY
1057 0xD1: FailUnimpl::stshortf_8s();
1058 //ASI_FL8_PRIMARY_LITTLE
1059 0xD8: FailUnimpl::stshortf_8pl();
1060 //ASI_FL8_SECONDARY_LITTLE
1061 0xD9: FailUnimpl::stshortf_8sl();
1062 //ASI_FL16_PRIMARY
1063 0xD2: FailUnimpl::stshortf_16p();
1064 //ASI_FL16_SECONDARY
1065 0xD3: FailUnimpl::stshortf_16s();
1066 //ASI_FL16_PRIMARY_LITTLE
1067 0xDA: FailUnimpl::stshortf_16pl();
1068 //ASI_FL16_SECONDARY_LITTLE
1069 0xDB: FailUnimpl::stshortf_16sl();
1070 //Not an ASI which is legal with lddfa
1071 default: Trap::stdfa_bad_asi(
1072 {{fault = new DataAccessException;}});
1073 }
1074 }
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