1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OP default Unknown::unknown()
37{
38 0x0: decode OP2
39 {
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 0x1: decode COND2
45 {
46 //Branch Always
47 0x8: decode A
48 {
49 0x0: b(19, {{
50 NNPC = xc->readPC() + disp;
51 }});
52 0x1: b(19, {{
53 NPC = xc->readPC() + disp;
54 NNPC = NPC + 4;
55 }}, ',a');
56 }
57 //Branch Never
58 0x0: decode A
59 {
60 0x0: bn(19, {{
61 NNPC = NNPC;//Don't do anything
62 }});
63 0x1: bn(19, {{
64 NPC = xc->readNextPC() + 4;
65 NNPC = NPC + 4;
66 }}, ',a');
67 }
68 default: decode BPCC
69 {
70 0x0: bpcci(19, {{
71 if(passesCondition(Ccr<3:0>, COND2))
72 NNPC = xc->readPC() + disp;
73 else
74 handle_annul
75 }});
76 0x2: bpccx(19, {{
77 if(passesCondition(Ccr<7:4>, COND2))
78 NNPC = xc->readPC() + disp;
79 else
80 handle_annul
81 }});
82 }
83 }
84 0x2: bicc(22, {{
85 if(passesCondition(Ccr<3:0>, COND2))
86 NNPC = xc->readPC() + disp;
87 else
88 handle_annul
89 }});
90 }
91 0x3: decode RCOND2
92 {
93 format BranchSplit
94 {
95 0x1: bpreq({{
96 if(Rs1.sdw == 0)
97 NNPC = xc->readPC() + disp;
98 else
99 handle_annul
100 }});
101 0x2: bprle({{
102 if(Rs1.sdw <= 0)
103 NNPC = xc->readPC() + disp;
104 else
105 handle_annul
106 }});
107 0x3: bprl({{
108 if(Rs1.sdw < 0)
109 NNPC = xc->readPC() + disp;
110 else
111 handle_annul
112 }});
113 0x5: bprne({{
114 if(Rs1.sdw != 0)
115 NNPC = xc->readPC() + disp;
116 else
117 handle_annul
118 }});
119 0x6: bprg({{
120 if(Rs1.sdw > 0)
121 NNPC = xc->readPC() + disp;
122 else
123 handle_annul
124 }});
125 0x7: bprge({{
126 if(Rs1.sdw >= 0)
127 NNPC = xc->readPC() + disp;
128 else
129 handle_annul
130 }});
131 }
132 }
133 //SETHI (or NOP if rd == 0 and imm == 0)
134 0x4: SetHi::sethi({{Rd.udw = imm;}});
135 0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
136 0x6: Trap::fbfcc({{fault = new FpDisabled;}});
137 }
138 0x1: BranchN::call(30, {{
139 R15 = xc->readPC();
140 NNPC = R15 + disp;
141 }});
142 0x2: decode OP3 {
143 format IntOp {
144 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
145 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
146 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
147 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
148 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
149 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}});
150 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}});
151 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
152 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
153 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
154 0x0A: umul({{
155 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
156 Y = Rd<63:32>;
157 }});
158 0x0B: smul({{
159 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
160 Y = Rd.sdw;
161 }});
162 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
163 0x0D: udivx({{
164 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
165 else Rd.udw = Rs1.udw / Rs2_or_imm13;
166 }});
167 0x0E: udiv({{
168 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
169 else
170 {
171 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
172 if(Rd.udw >> 32 != 0)
173 Rd.udw = 0xFFFFFFFF;
174 }
175 }});
176 0x0F: sdiv({{
177 if(Rs2_or_imm13.sdw == 0)
178 fault = new DivisionByZero;
179 else
180 {
181 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
182 if(Rd.udw<63:31> != 0)
183 Rd.udw = 0x7FFFFFFF;
184 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
185 Rd.udw = 0xFFFFFFFF80000000ULL;
186 }
187 }});
188 }
189 format IntOpCc {
190 0x10: addcc({{
191 int64_t resTemp, val2 = Rs2_or_imm13;
192 Rd = resTemp = Rs1 + val2;}},
193 {{(Rs1<31:0> + val2<31:0>)<32:>}},
194 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
195 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
196 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
197 );
198 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
199 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
200 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
201 0x14: subcc({{
202 int64_t val2 = Rs2_or_imm13;
203 Rd = Rs1 - val2;}},
204 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
205 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
206 {{(~(Rs1<63:1> + (~val2)<63:1> +
207 (Rs1 | ~val2)<0:>))<63:>}},
208 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
209 );
210 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
211 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
212 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
213 0x18: addccc({{
214 int64_t resTemp, val2 = Rs2_or_imm13;
215 int64_t carryin = Ccr<0:0>;
216 Rd = resTemp = Rs1 + val2 + carryin;}},
217 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
218 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
219 {{(Rs1<63:1> + val2<63:1> +
220 ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
221 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
222 );
223 0x1A: umulcc({{
224 uint64_t resTemp;
225 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
226 Y = resTemp<63:32>;}},
227 {{0}},{{0}},{{0}},{{0}});
228 0x1B: smulcc({{
229 int64_t resTemp;
230 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>;
231 Y = resTemp<63:32>;}},
232 {{0}},{{0}},{{0}},{{0}});
233 0x1C: subccc({{
234 int64_t resTemp, val2 = Rs2_or_imm13;
235 int64_t carryin = Ccr<0:0>;
236 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
237 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
238 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
239 {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
240 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
241 );
242 0x1D: udivxcc({{
243 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
244 else Rd = Rs1.udw / Rs2_or_imm13.udw;}}
245 ,{{0}},{{0}},{{0}},{{0}});
246 0x1E: udivcc({{
247 uint32_t resTemp, val2 = Rs2_or_imm13.udw;
248 int32_t overflow = 0;
249 if(val2 == 0) fault = new DivisionByZero;
250 else
251 {
252 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
253 overflow = (resTemp<63:32> != 0);
254 if(overflow) Rd = resTemp = 0xFFFFFFFF;
255 else Rd = resTemp;
256 } }},
257 {{0}},
258 {{overflow}},
259 {{0}},
260 {{0}}
261 );
262 0x1F: sdivcc({{
263 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
264 bool overflow = false, underflow = false;
265 if(val2 == 0) fault = new DivisionByZero;
266 else
267 {
268 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
269 overflow = (Rd<63:31> != 0);
270 underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF);
271 if(overflow) Rd = 0x7FFFFFFF;
272 else if(underflow) Rd = 0xFFFFFFFF80000000ULL;
273 } }},
274 {{0}},
275 {{overflow || underflow}},
276 {{0}},
277 {{0}}
278 );
279 0x20: taddcc({{
280 int64_t resTemp, val2 = Rs2_or_imm13;
281 Rd = resTemp = Rs1 + val2;
282 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
283 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
284 {{overflow}},
285 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
286 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
287 );
288 0x21: tsubcc({{
289 int64_t resTemp, val2 = Rs2_or_imm13;
290 Rd = resTemp = Rs1 + val2;
291 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
292 {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}},
293 {{overflow}},
294 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
295 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
296 );
297 0x22: taddcctv({{
298 int64_t val2 = Rs2_or_imm13;
299 Rd = Rs1 + val2;
300 int32_t overflow = Rs1<1:0> || val2<1:0> ||
301 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
302 if(overflow) fault = new TagOverflow;}},
303 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
304 {{overflow}},
305 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
306 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}}
307 );
308 0x23: tsubcctv({{
309 int64_t resTemp, val2 = Rs2_or_imm13;
310 Rd = resTemp = Rs1 + val2;
311 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
312 if(overflow) fault = new TagOverflow;}},
313 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
314 {{overflow}},
315 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
316 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
317 );
318 0x24: mulscc({{
319 int64_t resTemp, multiplicand = Rs2_or_imm13;
320 int32_t multiplier = Rs1<31:0>;
321 int32_t savedLSB = Rs1<0:>;
322 multiplier = multiplier<31:1> |
323 ((Ccr<3:3>
324 ^ Ccr<1:1>) << 32);
325 if(!Y<0:>)
326 multiplicand = 0;
327 Rd = resTemp = multiplicand + multiplier;
328 Y = Y<31:1> | (savedLSB << 31);}},
329 {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
330 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
331 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
332 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
333 );
334 }
335 format IntOp
336 {
337 0x25: decode X {
338 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
339 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
340 }
341 0x26: decode X {
342 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
343 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
344 }
345 0x27: decode X {
346 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
347 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
348 }
349 // XXX might want a format rdipr thing here
350 0x28: decode RS1 {
351 0xF: decode I {
352 0x0: Nop::stbar({{/*stuff*/}});
353 0x1: Nop::membar({{/*stuff*/}});
354 }
355 default: rdasr({{
356 Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault);
357 }});
358 }
359 0x29: HPriv::rdhpr({{
360 // XXX Need to protect with format that traps non-priv/priv
361 // access
362 Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault);
363 }});
364 0x2A: Priv::rdpr({{
365 // XXX Need to protect with format that traps non-priv
366 // access
367 Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault);
368 }});
369 0x2B: BasicOperate::flushw({{
370 if(NWindows - 2 - Cansave == 0)
371 {
372 if(Otherwin)
373 fault = new SpillNOther(Wstate<5:3>);
374 else
375 fault = new SpillNNormal(Wstate<2:0>);
376 }
377 }});
378 0x2C: decode MOVCC3
379 {
380 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
381 0x1: decode CC
382 {
383 0x0: movcci({{
384 if(passesCondition(Ccr<3:0>, COND4))
385 Rd = Rs2_or_imm11;
386 else
387 Rd = Rd;
388 }});
389 0x2: movccx({{
390 if(passesCondition(Ccr<7:4>, COND4))
391 Rd = Rs2_or_imm11;
392 else
393 Rd = Rd;
394 }});
395 }
396 }
397 0x2D: sdivx({{
398 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
399 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
400 }});
401 0x2E: decode RS1 {
402 0x0: IntOp::popc({{
403 int64_t count = 0;
404 uint64_t temp = Rs2_or_imm13;
405 //Count the 1s in the front 4bits until none are left
406 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
407 while(temp)
408 {
409 count += oneBits[temp & 0xF];
410 temp = temp >> 4;
411 }
412 Rd = count;
413 }});
414 }
415 0x2F: decode RCOND3
416 {
417 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
418 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
419 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
420 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
421 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
422 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
423 }
424 0x30: wrasr({{
425 xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13);
426 }});
427 0x31: decode FCN {
428 0x0: BasicOperate::saved({{/*Boogy Boogy*/}});
429 0x1: BasicOperate::restored({{/*Boogy Boogy*/}});
430 }
431 0x32: Priv::wrpr({{
432 // XXX Need to protect with format that traps non-priv
433 // access
434 fault = xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13);
435 }});
436 0x33: HPriv::wrhpr({{
437 // XXX Need to protect with format that traps non-priv/priv
438 // access
439 fault = xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
440 }});
441 0x34: decode OPF{
442 format BasicOperate{
443 0x01: fmovs({{
444 Frds.uw = Frs2s.uw;
445 //fsr.ftt = fsr.cexc = 0
446 Fsr &= ~(7 << 14);
447 Fsr &= ~(0x1F);
448 }});
449 0x02: fmovd({{
450 Frd.udw = Frs2.udw;
451 //fsr.ftt = fsr.cexc = 0
452 Fsr &= ~(7 << 14);
453 Fsr &= ~(0x1F);
454 }});
455 0x03: Trap::fmovq({{fault = new FpDisabled;}});
456 0x05: fnegs({{
457 Frds.uw = Frs2s.uw ^ (1UL << 31);
458 //fsr.ftt = fsr.cexc = 0
459 Fsr &= ~(7 << 14);
460 Fsr &= ~(0x1F);
461 }});
462 0x06: fnegd({{
463 Frd.udw = Frs2.udw ^ (1ULL << 63);
464 //fsr.ftt = fsr.cexc = 0
465 Fsr &= ~(7 << 14);
466 Fsr &= ~(0x1F);
467 }});
468 0x07: Trap::fnegq({{fault = new FpDisabled;}});
469 0x09: fabss({{
470 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;
471 //fsr.ftt = fsr.cexc = 0
472 Fsr &= ~(7 << 14);
473 Fsr &= ~(0x1F);
474 }});
475 0x0A: fabsd({{
476 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;
477 //fsr.ftt = fsr.cexc = 0
478 Fsr &= ~(7 << 14);
479 Fsr &= ~(0x1F);
480 }});
481 0x0B: Trap::fabsq({{fault = new FpDisabled;}});
482 0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}});
483 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}});
484 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
485 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
486 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
487 0x43: Trap::faddq({{fault = new FpDisabled;}});
488 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
489 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
490 0x47: Trap::fsubq({{fault = new FpDisabled;}});
491 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
492 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
493 0x4B: Trap::fmulq({{fault = new FpDisabled;}});
494 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
495 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
496 0x4F: Trap::fdivq({{fault = new FpDisabled;}});
497 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
498 0x6E: Trap::fdmulq({{fault = new FpDisabled;}});
499 0x81: fstox({{
500 Frd.df = (double)static_cast<int64_t>(Frs2s.sf);
501 }});
502 0x82: fdtox({{
503 Frd.df = (double)static_cast<int64_t>(Frs2.df);
504 }});
505 0x83: Trap::fqtox({{fault = new FpDisabled;}});
506 0x84: fxtos({{
507 Frds.sf = static_cast<float>((int64_t)Frs2.df);
508 }});
509 0x88: fxtod({{
510 Frd.df = static_cast<double>((int64_t)Frs2.df);
511 }});
512 0x8C: Trap::fxtoq({{fault = new FpDisabled;}});
513 0xC4: fitos({{
514 Frds.sf = static_cast<float>((int32_t)Frs2s.sf);
515 }});
516 0xC6: fdtos({{Frds.sf = Frs2.df;}});
517 0xC7: Trap::fqtos({{fault = new FpDisabled;}});
518 0xC8: fitod({{
519 Frd.df = static_cast<double>((int32_t)Frs2s.sf);
520 }});
521 0xC9: fstod({{Frd.df = Frs2s.sf;}});
522 0xCB: Trap::fqtod({{fault = new FpDisabled;}});
523 0xCC: Trap::fitoq({{fault = new FpDisabled;}});
524 0xCD: Trap::fstoq({{fault = new FpDisabled;}});
525 0xCE: Trap::fdtoq({{fault = new FpDisabled;}});
526 0xD1: fstoi({{
527 Frds.sf = (float)static_cast<int32_t>(Frs2s.sf);
528 }});
529 0xD2: fdtoi({{
530 Frds.sf = (float)static_cast<int32_t>(Frs2.df);
531 }});
532 0xD3: Trap::fqtoi({{fault = new FpDisabled;}});
533 default: Trap::fpop1({{fault = new FpDisabled;}});
534 }
535 }
536 0x35: Trap::fpop2({{fault = new FpDisabled;}});
537 //This used to be just impdep1, but now it's a whole bunch
538 //of instructions
539 0x36: decode OPF{
540 0x00: Trap::edge8({{fault = new IllegalInstruction;}});
541 0x01: Trap::edge8n({{fault = new IllegalInstruction;}});
542 0x02: Trap::edge8l({{fault = new IllegalInstruction;}});
543 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}});
544 0x04: Trap::edge16({{fault = new IllegalInstruction;}});
545 0x05: Trap::edge16n({{fault = new IllegalInstruction;}});
546 0x06: Trap::edge16l({{fault = new IllegalInstruction;}});
547 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}});
548 0x08: Trap::edge32({{fault = new IllegalInstruction;}});
549 0x09: Trap::edge32n({{fault = new IllegalInstruction;}});
550 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}});
551 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}});
552 0x10: Trap::array8({{fault = new IllegalInstruction;}});
553 0x12: Trap::array16({{fault = new IllegalInstruction;}});
554 0x14: Trap::array32({{fault = new IllegalInstruction;}});
555 0x18: BasicOperate::alignaddr({{
556 uint64_t sum = Rs1 + Rs2;
557 Rd = sum & ~7;
558 Gsr = (Gsr & ~7) | (sum & 7);
559 }});
560 0x19: Trap::bmask({{fault = new IllegalInstruction;}});
561 0x1A: BasicOperate::alignaddresslittle({{
562 uint64_t sum = Rs1 + Rs2;
563 Rd = sum & ~7;
564 Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
565 }});
566 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}});
567 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}});
568 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}});
569 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}});
570 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}});
571 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}});
572 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}});
573 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}});
574 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}});
575 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}});
576 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}});
577 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}});
578 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}});
579 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}});
580 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}});
581 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
582 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
583 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
584 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
585 0x48: BasicOperate::faligndata({{
586 uint64_t msbX = Frs1.udw;
587 uint64_t lsbX = Frs2.udw;
588 //Some special cases need to be split out, first
589 //because they're the most likely to be used, and
590 //second because otherwise, we end up shifting by
591 //greater than the width of the type being shifted,
592 //namely 64, which produces undefined results according
593 //to the C standard.
594 switch(Gsr<2:0>)
595 {
596 case 0:
597 Frd.udw = msbX;
598 break;
599 case 8:
600 Frd.udw = lsbX;
601 break;
602 default:
603 uint64_t msbShift = Gsr<2:0> * 8;
604 uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
605 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
606 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
607 Frd.udw = ((msbX & msbMask) << msbShift) |
608 ((lsbX & lsbMask) >> lsbShift);
609 }
610 }});
611 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
612 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}});
613 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}});
614 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}});
615 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}});
616 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}});
617 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}});
618 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}});
619 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}});
620 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}});
621 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}});
622 0x60: BasicOperate::fzero({{Frd.df = 0;}});
623 0x61: BasicOperate::fzeros({{Frds.sf = 0;}});
624 0x62: Trap::fnor({{fault = new IllegalInstruction;}});
625 0x63: Trap::fnors({{fault = new IllegalInstruction;}});
626 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}});
627 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}});
628 0x66: BasicOperate::fnot2({{
629 Frd.df = (double)(~((uint64_t)Frs2.df));
630 }});
631 0x67: BasicOperate::fnot2s({{
632 Frds.sf = (float)(~((uint32_t)Frs2s.sf));
633 }});
634 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}});
635 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}});
636 0x6A: BasicOperate::fnot1({{
637 Frd.df = (double)(~((uint64_t)Frs1.df));
638 }});
639 0x6B: BasicOperate::fnot1s({{
640 Frds.sf = (float)(~((uint32_t)Frs1s.sf));
641 }});
642 0x6C: Trap::fxor({{fault = new IllegalInstruction;}});
643 0x6D: Trap::fxors({{fault = new IllegalInstruction;}});
644 0x6E: Trap::fnand({{fault = new IllegalInstruction;}});
645 0x6F: Trap::fnands({{fault = new IllegalInstruction;}});
646 0x70: Trap::fand({{fault = new IllegalInstruction;}});
647 0x71: Trap::fands({{fault = new IllegalInstruction;}});
648 0x72: Trap::fxnor({{fault = new IllegalInstruction;}});
649 0x73: Trap::fxnors({{fault = new IllegalInstruction;}});
650 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}});
651 0x75: BasicOperate::fsrc1s({{Frd.uw = Frs1.uw;}});
652 0x76: Trap::fornot2({{fault = new IllegalInstruction;}});
653 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}});
654 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}});
655 0x79: BasicOperate::fsrc2s({{Frd.uw = Frs2.uw;}});
656 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}});
657 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}});
658 0x7C: Trap::for({{fault = new IllegalInstruction;}});
659 0x7D: Trap::fors({{fault = new IllegalInstruction;}});
660 0x7E: Trap::fone({{fault = new IllegalInstruction;}});
661 0x7F: Trap::fones({{fault = new IllegalInstruction;}});
662 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
663 0x81: Trap::siam({{fault = new IllegalInstruction;}});
664 }
665 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
666 0x38: Branch::jmpl({{
667 Addr target = Rs1 + Rs2_or_imm13;
668 if(target & 0x3)
669 fault = new MemAddressNotAligned;
670 else
671 {
672 Rd = xc->readPC();
673 NNPC = target;
674 }
675 }});
676 0x39: Branch::return({{
677 //If both MemAddressNotAligned and
678 //a fill trap happen, it's not clear
679 //which one should be returned.
680 Addr target = Rs1 + Rs2_or_imm13;
681 if(target & 0x3)
682 fault = new MemAddressNotAligned;
683 else
684 NNPC = target;
685 if(fault == NoFault)
686 {
687 //CWP should be set directly so that it always happens
688 //Also, this will allow writing to the new window and
689 //reading from the old one
690 Cwp = (Cwp - 1 + NWindows) % NWindows;
691 if(Canrestore == 0)
692 {
693 if(Otherwin)
694 fault = new FillNOther(Wstate<5:3>);
695 else
696 fault = new FillNNormal(Wstate<2:0>);
697 }
698 else
699 {
700 Rd = Rs1 + Rs2_or_imm13;
701 Cansave = Cansave + 1;
702 Canrestore = Canrestore - 1;
703 }
704 //This is here to make sure the CWP is written
705 //no matter what. This ensures that the results
706 //are written in the new window as well.
707 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
708 }
709 }});
710 0x3A: decode CC
711 {
712 0x0: Trap::tcci({{
713 if(passesCondition(Ccr<3:0>, COND2))
714 {
715#if FULL_SYSTEM
716 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
717 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
718 fault = new TrapInstruction(lTrapNum);
719#else
720 DPRINTF(Sparc, "The syscall number is %d\n", R1);
721 xc->syscall(R1);
722#endif
723 }
724 }});
725 0x2: Trap::tccx({{
726 if(passesCondition(Ccr<7:4>, COND2))
727 {
728#if FULL_SYSTEM
729 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
730 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
731 fault = new TrapInstruction(lTrapNum);
732#else
733 DPRINTF(Sparc, "The syscall number is %d\n", R1);
734 xc->syscall(R1);
735#endif
736 }
737 }});
738 }
739 0x3B: Nop::flush({{/*Instruction memory flush*/}});
740 0x3C: save({{
741 //CWP should be set directly so that it always happens
742 //Also, this will allow writing to the new window and
743 //reading from the old one
744 if(Cansave == 0)
745 {
746 if(Otherwin)
747 fault = new SpillNOther(Wstate<5:3>);
748 else
749 fault = new SpillNNormal(Wstate<2:0>);
750 Cwp = (Cwp + 2) % NWindows;
751 }
752 else if(Cleanwin - Canrestore == 0)
753 {
754 Cwp = (Cwp + 1) % NWindows;
755 fault = new CleanWindow;
756 }
757 else
758 {
759 Cwp = (Cwp + 1) % NWindows;
760 Rd = Rs1 + Rs2_or_imm13;
761 Cansave = Cansave - 1;
762 Canrestore = Canrestore + 1;
763 }
764 //This is here to make sure the CWP is written
765 //no matter what. This ensures that the results
766 //are written in the new window as well.
767 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
768 }});
769 0x3D: restore({{
770 //CWP should be set directly so that it always happens
771 //Also, this will allow writing to the new window and
772 //reading from the old one
773 Cwp = (Cwp - 1 + NWindows) % NWindows;
774 if(Canrestore == 0)
775 {
776 if(Otherwin)
777 fault = new FillNOther(Wstate<5:3>);
778 else
779 fault = new FillNNormal(Wstate<2:0>);
780 }
781 else
782 {
783 Rd = Rs1 + Rs2_or_imm13;
784 Cansave = Cansave + 1;
785 Canrestore = Canrestore - 1;
786 }
787 //This is here to make sure the CWP is written
788 //no matter what. This ensures that the results
789 //are written in the new window as well.
790 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
791 }});
792 0x3E: decode FCN {
793 0x0: Priv::done({{
794 if(Tl == 0)
795 return new IllegalInstruction;
796
797 Cwp = Tstate<4:0>;
798 Pstate = Tstate<20:8>;
799 Asi = Tstate<31:24>;
800 Ccr = Tstate<39:32>;
801 Gl = Tstate<42:40>;
802 NPC = Tnpc;
803 NNPC = Tnpc + 4;
804 Tl = Tl - 1;
805 }});
806 0x1: Priv::retry({{
807 if(Tl == 0)
808 return new IllegalInstruction;
809 Cwp = Tstate<4:0>;
810 Pstate = Tstate<20:8>;
811 Asi = Tstate<31:24>;
812 Ccr = Tstate<39:32>;
813 Gl = Tstate<42:40>;
814 NPC = Tpc;
815 NNPC = Tnpc + 4;
816 Tl = Tl - 1;
817 }});
818 }
819 }
820 }
821 0x3: decode OP3 {
822 format Load {
823 0x00: lduw({{Rd = Mem.uw;}});
824 0x01: ldub({{Rd = Mem.ub;}});
825 0x02: lduh({{Rd = Mem.uhw;}});
826 0x03: ldd({{
827 uint64_t val = Mem.udw;
828 RdLow = val<31:0>;
829 RdHigh = val<63:32>;
830 }});
831 }
832 format Store {
833 0x04: stw({{Mem.uw = Rd.sw;}});
834 0x05: stb({{Mem.ub = Rd.sb;}});
835 0x06: sth({{Mem.uhw = Rd.shw;}});
836 0x07: std({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
837 }
838 format Load {
839 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
840 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
841 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
842 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
843 0x0D: ldstub({{
844 Rd = Mem.ub;
845 Mem.ub = 0xFF;
846 }});
847 }
848 0x0E: Store::stx({{Mem.udw = Rd}});
| 1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OP default Unknown::unknown()
37{
38 0x0: decode OP2
39 {
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 0x1: decode COND2
45 {
46 //Branch Always
47 0x8: decode A
48 {
49 0x0: b(19, {{
50 NNPC = xc->readPC() + disp;
51 }});
52 0x1: b(19, {{
53 NPC = xc->readPC() + disp;
54 NNPC = NPC + 4;
55 }}, ',a');
56 }
57 //Branch Never
58 0x0: decode A
59 {
60 0x0: bn(19, {{
61 NNPC = NNPC;//Don't do anything
62 }});
63 0x1: bn(19, {{
64 NPC = xc->readNextPC() + 4;
65 NNPC = NPC + 4;
66 }}, ',a');
67 }
68 default: decode BPCC
69 {
70 0x0: bpcci(19, {{
71 if(passesCondition(Ccr<3:0>, COND2))
72 NNPC = xc->readPC() + disp;
73 else
74 handle_annul
75 }});
76 0x2: bpccx(19, {{
77 if(passesCondition(Ccr<7:4>, COND2))
78 NNPC = xc->readPC() + disp;
79 else
80 handle_annul
81 }});
82 }
83 }
84 0x2: bicc(22, {{
85 if(passesCondition(Ccr<3:0>, COND2))
86 NNPC = xc->readPC() + disp;
87 else
88 handle_annul
89 }});
90 }
91 0x3: decode RCOND2
92 {
93 format BranchSplit
94 {
95 0x1: bpreq({{
96 if(Rs1.sdw == 0)
97 NNPC = xc->readPC() + disp;
98 else
99 handle_annul
100 }});
101 0x2: bprle({{
102 if(Rs1.sdw <= 0)
103 NNPC = xc->readPC() + disp;
104 else
105 handle_annul
106 }});
107 0x3: bprl({{
108 if(Rs1.sdw < 0)
109 NNPC = xc->readPC() + disp;
110 else
111 handle_annul
112 }});
113 0x5: bprne({{
114 if(Rs1.sdw != 0)
115 NNPC = xc->readPC() + disp;
116 else
117 handle_annul
118 }});
119 0x6: bprg({{
120 if(Rs1.sdw > 0)
121 NNPC = xc->readPC() + disp;
122 else
123 handle_annul
124 }});
125 0x7: bprge({{
126 if(Rs1.sdw >= 0)
127 NNPC = xc->readPC() + disp;
128 else
129 handle_annul
130 }});
131 }
132 }
133 //SETHI (or NOP if rd == 0 and imm == 0)
134 0x4: SetHi::sethi({{Rd.udw = imm;}});
135 0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
136 0x6: Trap::fbfcc({{fault = new FpDisabled;}});
137 }
138 0x1: BranchN::call(30, {{
139 R15 = xc->readPC();
140 NNPC = R15 + disp;
141 }});
142 0x2: decode OP3 {
143 format IntOp {
144 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
145 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
146 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
147 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
148 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
149 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}});
150 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}});
151 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
152 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
153 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
154 0x0A: umul({{
155 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
156 Y = Rd<63:32>;
157 }});
158 0x0B: smul({{
159 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
160 Y = Rd.sdw;
161 }});
162 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
163 0x0D: udivx({{
164 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
165 else Rd.udw = Rs1.udw / Rs2_or_imm13;
166 }});
167 0x0E: udiv({{
168 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
169 else
170 {
171 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
172 if(Rd.udw >> 32 != 0)
173 Rd.udw = 0xFFFFFFFF;
174 }
175 }});
176 0x0F: sdiv({{
177 if(Rs2_or_imm13.sdw == 0)
178 fault = new DivisionByZero;
179 else
180 {
181 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
182 if(Rd.udw<63:31> != 0)
183 Rd.udw = 0x7FFFFFFF;
184 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
185 Rd.udw = 0xFFFFFFFF80000000ULL;
186 }
187 }});
188 }
189 format IntOpCc {
190 0x10: addcc({{
191 int64_t resTemp, val2 = Rs2_or_imm13;
192 Rd = resTemp = Rs1 + val2;}},
193 {{(Rs1<31:0> + val2<31:0>)<32:>}},
194 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
195 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
196 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
197 );
198 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
199 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
200 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
201 0x14: subcc({{
202 int64_t val2 = Rs2_or_imm13;
203 Rd = Rs1 - val2;}},
204 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
205 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
206 {{(~(Rs1<63:1> + (~val2)<63:1> +
207 (Rs1 | ~val2)<0:>))<63:>}},
208 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
209 );
210 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
211 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
212 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
213 0x18: addccc({{
214 int64_t resTemp, val2 = Rs2_or_imm13;
215 int64_t carryin = Ccr<0:0>;
216 Rd = resTemp = Rs1 + val2 + carryin;}},
217 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
218 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
219 {{(Rs1<63:1> + val2<63:1> +
220 ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
221 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
222 );
223 0x1A: umulcc({{
224 uint64_t resTemp;
225 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
226 Y = resTemp<63:32>;}},
227 {{0}},{{0}},{{0}},{{0}});
228 0x1B: smulcc({{
229 int64_t resTemp;
230 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>;
231 Y = resTemp<63:32>;}},
232 {{0}},{{0}},{{0}},{{0}});
233 0x1C: subccc({{
234 int64_t resTemp, val2 = Rs2_or_imm13;
235 int64_t carryin = Ccr<0:0>;
236 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
237 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
238 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
239 {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
240 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
241 );
242 0x1D: udivxcc({{
243 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
244 else Rd = Rs1.udw / Rs2_or_imm13.udw;}}
245 ,{{0}},{{0}},{{0}},{{0}});
246 0x1E: udivcc({{
247 uint32_t resTemp, val2 = Rs2_or_imm13.udw;
248 int32_t overflow = 0;
249 if(val2 == 0) fault = new DivisionByZero;
250 else
251 {
252 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
253 overflow = (resTemp<63:32> != 0);
254 if(overflow) Rd = resTemp = 0xFFFFFFFF;
255 else Rd = resTemp;
256 } }},
257 {{0}},
258 {{overflow}},
259 {{0}},
260 {{0}}
261 );
262 0x1F: sdivcc({{
263 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
264 bool overflow = false, underflow = false;
265 if(val2 == 0) fault = new DivisionByZero;
266 else
267 {
268 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
269 overflow = (Rd<63:31> != 0);
270 underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF);
271 if(overflow) Rd = 0x7FFFFFFF;
272 else if(underflow) Rd = 0xFFFFFFFF80000000ULL;
273 } }},
274 {{0}},
275 {{overflow || underflow}},
276 {{0}},
277 {{0}}
278 );
279 0x20: taddcc({{
280 int64_t resTemp, val2 = Rs2_or_imm13;
281 Rd = resTemp = Rs1 + val2;
282 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
283 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
284 {{overflow}},
285 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
286 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
287 );
288 0x21: tsubcc({{
289 int64_t resTemp, val2 = Rs2_or_imm13;
290 Rd = resTemp = Rs1 + val2;
291 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
292 {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}},
293 {{overflow}},
294 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
295 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
296 );
297 0x22: taddcctv({{
298 int64_t val2 = Rs2_or_imm13;
299 Rd = Rs1 + val2;
300 int32_t overflow = Rs1<1:0> || val2<1:0> ||
301 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
302 if(overflow) fault = new TagOverflow;}},
303 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
304 {{overflow}},
305 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
306 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}}
307 );
308 0x23: tsubcctv({{
309 int64_t resTemp, val2 = Rs2_or_imm13;
310 Rd = resTemp = Rs1 + val2;
311 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
312 if(overflow) fault = new TagOverflow;}},
313 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
314 {{overflow}},
315 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
316 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
317 );
318 0x24: mulscc({{
319 int64_t resTemp, multiplicand = Rs2_or_imm13;
320 int32_t multiplier = Rs1<31:0>;
321 int32_t savedLSB = Rs1<0:>;
322 multiplier = multiplier<31:1> |
323 ((Ccr<3:3>
324 ^ Ccr<1:1>) << 32);
325 if(!Y<0:>)
326 multiplicand = 0;
327 Rd = resTemp = multiplicand + multiplier;
328 Y = Y<31:1> | (savedLSB << 31);}},
329 {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
330 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
331 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
332 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
333 );
334 }
335 format IntOp
336 {
337 0x25: decode X {
338 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
339 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
340 }
341 0x26: decode X {
342 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
343 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
344 }
345 0x27: decode X {
346 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
347 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
348 }
349 // XXX might want a format rdipr thing here
350 0x28: decode RS1 {
351 0xF: decode I {
352 0x0: Nop::stbar({{/*stuff*/}});
353 0x1: Nop::membar({{/*stuff*/}});
354 }
355 default: rdasr({{
356 Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault);
357 }});
358 }
359 0x29: HPriv::rdhpr({{
360 // XXX Need to protect with format that traps non-priv/priv
361 // access
362 Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault);
363 }});
364 0x2A: Priv::rdpr({{
365 // XXX Need to protect with format that traps non-priv
366 // access
367 Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault);
368 }});
369 0x2B: BasicOperate::flushw({{
370 if(NWindows - 2 - Cansave == 0)
371 {
372 if(Otherwin)
373 fault = new SpillNOther(Wstate<5:3>);
374 else
375 fault = new SpillNNormal(Wstate<2:0>);
376 }
377 }});
378 0x2C: decode MOVCC3
379 {
380 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
381 0x1: decode CC
382 {
383 0x0: movcci({{
384 if(passesCondition(Ccr<3:0>, COND4))
385 Rd = Rs2_or_imm11;
386 else
387 Rd = Rd;
388 }});
389 0x2: movccx({{
390 if(passesCondition(Ccr<7:4>, COND4))
391 Rd = Rs2_or_imm11;
392 else
393 Rd = Rd;
394 }});
395 }
396 }
397 0x2D: sdivx({{
398 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
399 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
400 }});
401 0x2E: decode RS1 {
402 0x0: IntOp::popc({{
403 int64_t count = 0;
404 uint64_t temp = Rs2_or_imm13;
405 //Count the 1s in the front 4bits until none are left
406 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
407 while(temp)
408 {
409 count += oneBits[temp & 0xF];
410 temp = temp >> 4;
411 }
412 Rd = count;
413 }});
414 }
415 0x2F: decode RCOND3
416 {
417 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
418 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
419 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
420 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
421 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
422 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
423 }
424 0x30: wrasr({{
425 xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13);
426 }});
427 0x31: decode FCN {
428 0x0: BasicOperate::saved({{/*Boogy Boogy*/}});
429 0x1: BasicOperate::restored({{/*Boogy Boogy*/}});
430 }
431 0x32: Priv::wrpr({{
432 // XXX Need to protect with format that traps non-priv
433 // access
434 fault = xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13);
435 }});
436 0x33: HPriv::wrhpr({{
437 // XXX Need to protect with format that traps non-priv/priv
438 // access
439 fault = xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
440 }});
441 0x34: decode OPF{
442 format BasicOperate{
443 0x01: fmovs({{
444 Frds.uw = Frs2s.uw;
445 //fsr.ftt = fsr.cexc = 0
446 Fsr &= ~(7 << 14);
447 Fsr &= ~(0x1F);
448 }});
449 0x02: fmovd({{
450 Frd.udw = Frs2.udw;
451 //fsr.ftt = fsr.cexc = 0
452 Fsr &= ~(7 << 14);
453 Fsr &= ~(0x1F);
454 }});
455 0x03: Trap::fmovq({{fault = new FpDisabled;}});
456 0x05: fnegs({{
457 Frds.uw = Frs2s.uw ^ (1UL << 31);
458 //fsr.ftt = fsr.cexc = 0
459 Fsr &= ~(7 << 14);
460 Fsr &= ~(0x1F);
461 }});
462 0x06: fnegd({{
463 Frd.udw = Frs2.udw ^ (1ULL << 63);
464 //fsr.ftt = fsr.cexc = 0
465 Fsr &= ~(7 << 14);
466 Fsr &= ~(0x1F);
467 }});
468 0x07: Trap::fnegq({{fault = new FpDisabled;}});
469 0x09: fabss({{
470 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;
471 //fsr.ftt = fsr.cexc = 0
472 Fsr &= ~(7 << 14);
473 Fsr &= ~(0x1F);
474 }});
475 0x0A: fabsd({{
476 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;
477 //fsr.ftt = fsr.cexc = 0
478 Fsr &= ~(7 << 14);
479 Fsr &= ~(0x1F);
480 }});
481 0x0B: Trap::fabsq({{fault = new FpDisabled;}});
482 0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}});
483 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}});
484 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
485 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
486 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
487 0x43: Trap::faddq({{fault = new FpDisabled;}});
488 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
489 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
490 0x47: Trap::fsubq({{fault = new FpDisabled;}});
491 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
492 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
493 0x4B: Trap::fmulq({{fault = new FpDisabled;}});
494 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
495 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
496 0x4F: Trap::fdivq({{fault = new FpDisabled;}});
497 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
498 0x6E: Trap::fdmulq({{fault = new FpDisabled;}});
499 0x81: fstox({{
500 Frd.df = (double)static_cast<int64_t>(Frs2s.sf);
501 }});
502 0x82: fdtox({{
503 Frd.df = (double)static_cast<int64_t>(Frs2.df);
504 }});
505 0x83: Trap::fqtox({{fault = new FpDisabled;}});
506 0x84: fxtos({{
507 Frds.sf = static_cast<float>((int64_t)Frs2.df);
508 }});
509 0x88: fxtod({{
510 Frd.df = static_cast<double>((int64_t)Frs2.df);
511 }});
512 0x8C: Trap::fxtoq({{fault = new FpDisabled;}});
513 0xC4: fitos({{
514 Frds.sf = static_cast<float>((int32_t)Frs2s.sf);
515 }});
516 0xC6: fdtos({{Frds.sf = Frs2.df;}});
517 0xC7: Trap::fqtos({{fault = new FpDisabled;}});
518 0xC8: fitod({{
519 Frd.df = static_cast<double>((int32_t)Frs2s.sf);
520 }});
521 0xC9: fstod({{Frd.df = Frs2s.sf;}});
522 0xCB: Trap::fqtod({{fault = new FpDisabled;}});
523 0xCC: Trap::fitoq({{fault = new FpDisabled;}});
524 0xCD: Trap::fstoq({{fault = new FpDisabled;}});
525 0xCE: Trap::fdtoq({{fault = new FpDisabled;}});
526 0xD1: fstoi({{
527 Frds.sf = (float)static_cast<int32_t>(Frs2s.sf);
528 }});
529 0xD2: fdtoi({{
530 Frds.sf = (float)static_cast<int32_t>(Frs2.df);
531 }});
532 0xD3: Trap::fqtoi({{fault = new FpDisabled;}});
533 default: Trap::fpop1({{fault = new FpDisabled;}});
534 }
535 }
536 0x35: Trap::fpop2({{fault = new FpDisabled;}});
537 //This used to be just impdep1, but now it's a whole bunch
538 //of instructions
539 0x36: decode OPF{
540 0x00: Trap::edge8({{fault = new IllegalInstruction;}});
541 0x01: Trap::edge8n({{fault = new IllegalInstruction;}});
542 0x02: Trap::edge8l({{fault = new IllegalInstruction;}});
543 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}});
544 0x04: Trap::edge16({{fault = new IllegalInstruction;}});
545 0x05: Trap::edge16n({{fault = new IllegalInstruction;}});
546 0x06: Trap::edge16l({{fault = new IllegalInstruction;}});
547 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}});
548 0x08: Trap::edge32({{fault = new IllegalInstruction;}});
549 0x09: Trap::edge32n({{fault = new IllegalInstruction;}});
550 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}});
551 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}});
552 0x10: Trap::array8({{fault = new IllegalInstruction;}});
553 0x12: Trap::array16({{fault = new IllegalInstruction;}});
554 0x14: Trap::array32({{fault = new IllegalInstruction;}});
555 0x18: BasicOperate::alignaddr({{
556 uint64_t sum = Rs1 + Rs2;
557 Rd = sum & ~7;
558 Gsr = (Gsr & ~7) | (sum & 7);
559 }});
560 0x19: Trap::bmask({{fault = new IllegalInstruction;}});
561 0x1A: BasicOperate::alignaddresslittle({{
562 uint64_t sum = Rs1 + Rs2;
563 Rd = sum & ~7;
564 Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
565 }});
566 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}});
567 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}});
568 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}});
569 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}});
570 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}});
571 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}});
572 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}});
573 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}});
574 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}});
575 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}});
576 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}});
577 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}});
578 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}});
579 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}});
580 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}});
581 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
582 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
583 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
584 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
585 0x48: BasicOperate::faligndata({{
586 uint64_t msbX = Frs1.udw;
587 uint64_t lsbX = Frs2.udw;
588 //Some special cases need to be split out, first
589 //because they're the most likely to be used, and
590 //second because otherwise, we end up shifting by
591 //greater than the width of the type being shifted,
592 //namely 64, which produces undefined results according
593 //to the C standard.
594 switch(Gsr<2:0>)
595 {
596 case 0:
597 Frd.udw = msbX;
598 break;
599 case 8:
600 Frd.udw = lsbX;
601 break;
602 default:
603 uint64_t msbShift = Gsr<2:0> * 8;
604 uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
605 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
606 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
607 Frd.udw = ((msbX & msbMask) << msbShift) |
608 ((lsbX & lsbMask) >> lsbShift);
609 }
610 }});
611 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
612 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}});
613 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}});
614 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}});
615 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}});
616 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}});
617 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}});
618 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}});
619 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}});
620 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}});
621 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}});
622 0x60: BasicOperate::fzero({{Frd.df = 0;}});
623 0x61: BasicOperate::fzeros({{Frds.sf = 0;}});
624 0x62: Trap::fnor({{fault = new IllegalInstruction;}});
625 0x63: Trap::fnors({{fault = new IllegalInstruction;}});
626 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}});
627 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}});
628 0x66: BasicOperate::fnot2({{
629 Frd.df = (double)(~((uint64_t)Frs2.df));
630 }});
631 0x67: BasicOperate::fnot2s({{
632 Frds.sf = (float)(~((uint32_t)Frs2s.sf));
633 }});
634 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}});
635 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}});
636 0x6A: BasicOperate::fnot1({{
637 Frd.df = (double)(~((uint64_t)Frs1.df));
638 }});
639 0x6B: BasicOperate::fnot1s({{
640 Frds.sf = (float)(~((uint32_t)Frs1s.sf));
641 }});
642 0x6C: Trap::fxor({{fault = new IllegalInstruction;}});
643 0x6D: Trap::fxors({{fault = new IllegalInstruction;}});
644 0x6E: Trap::fnand({{fault = new IllegalInstruction;}});
645 0x6F: Trap::fnands({{fault = new IllegalInstruction;}});
646 0x70: Trap::fand({{fault = new IllegalInstruction;}});
647 0x71: Trap::fands({{fault = new IllegalInstruction;}});
648 0x72: Trap::fxnor({{fault = new IllegalInstruction;}});
649 0x73: Trap::fxnors({{fault = new IllegalInstruction;}});
650 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}});
651 0x75: BasicOperate::fsrc1s({{Frd.uw = Frs1.uw;}});
652 0x76: Trap::fornot2({{fault = new IllegalInstruction;}});
653 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}});
654 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}});
655 0x79: BasicOperate::fsrc2s({{Frd.uw = Frs2.uw;}});
656 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}});
657 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}});
658 0x7C: Trap::for({{fault = new IllegalInstruction;}});
659 0x7D: Trap::fors({{fault = new IllegalInstruction;}});
660 0x7E: Trap::fone({{fault = new IllegalInstruction;}});
661 0x7F: Trap::fones({{fault = new IllegalInstruction;}});
662 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
663 0x81: Trap::siam({{fault = new IllegalInstruction;}});
664 }
665 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
666 0x38: Branch::jmpl({{
667 Addr target = Rs1 + Rs2_or_imm13;
668 if(target & 0x3)
669 fault = new MemAddressNotAligned;
670 else
671 {
672 Rd = xc->readPC();
673 NNPC = target;
674 }
675 }});
676 0x39: Branch::return({{
677 //If both MemAddressNotAligned and
678 //a fill trap happen, it's not clear
679 //which one should be returned.
680 Addr target = Rs1 + Rs2_or_imm13;
681 if(target & 0x3)
682 fault = new MemAddressNotAligned;
683 else
684 NNPC = target;
685 if(fault == NoFault)
686 {
687 //CWP should be set directly so that it always happens
688 //Also, this will allow writing to the new window and
689 //reading from the old one
690 Cwp = (Cwp - 1 + NWindows) % NWindows;
691 if(Canrestore == 0)
692 {
693 if(Otherwin)
694 fault = new FillNOther(Wstate<5:3>);
695 else
696 fault = new FillNNormal(Wstate<2:0>);
697 }
698 else
699 {
700 Rd = Rs1 + Rs2_or_imm13;
701 Cansave = Cansave + 1;
702 Canrestore = Canrestore - 1;
703 }
704 //This is here to make sure the CWP is written
705 //no matter what. This ensures that the results
706 //are written in the new window as well.
707 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
708 }
709 }});
710 0x3A: decode CC
711 {
712 0x0: Trap::tcci({{
713 if(passesCondition(Ccr<3:0>, COND2))
714 {
715#if FULL_SYSTEM
716 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
717 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
718 fault = new TrapInstruction(lTrapNum);
719#else
720 DPRINTF(Sparc, "The syscall number is %d\n", R1);
721 xc->syscall(R1);
722#endif
723 }
724 }});
725 0x2: Trap::tccx({{
726 if(passesCondition(Ccr<7:4>, COND2))
727 {
728#if FULL_SYSTEM
729 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
730 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
731 fault = new TrapInstruction(lTrapNum);
732#else
733 DPRINTF(Sparc, "The syscall number is %d\n", R1);
734 xc->syscall(R1);
735#endif
736 }
737 }});
738 }
739 0x3B: Nop::flush({{/*Instruction memory flush*/}});
740 0x3C: save({{
741 //CWP should be set directly so that it always happens
742 //Also, this will allow writing to the new window and
743 //reading from the old one
744 if(Cansave == 0)
745 {
746 if(Otherwin)
747 fault = new SpillNOther(Wstate<5:3>);
748 else
749 fault = new SpillNNormal(Wstate<2:0>);
750 Cwp = (Cwp + 2) % NWindows;
751 }
752 else if(Cleanwin - Canrestore == 0)
753 {
754 Cwp = (Cwp + 1) % NWindows;
755 fault = new CleanWindow;
756 }
757 else
758 {
759 Cwp = (Cwp + 1) % NWindows;
760 Rd = Rs1 + Rs2_or_imm13;
761 Cansave = Cansave - 1;
762 Canrestore = Canrestore + 1;
763 }
764 //This is here to make sure the CWP is written
765 //no matter what. This ensures that the results
766 //are written in the new window as well.
767 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
768 }});
769 0x3D: restore({{
770 //CWP should be set directly so that it always happens
771 //Also, this will allow writing to the new window and
772 //reading from the old one
773 Cwp = (Cwp - 1 + NWindows) % NWindows;
774 if(Canrestore == 0)
775 {
776 if(Otherwin)
777 fault = new FillNOther(Wstate<5:3>);
778 else
779 fault = new FillNNormal(Wstate<2:0>);
780 }
781 else
782 {
783 Rd = Rs1 + Rs2_or_imm13;
784 Cansave = Cansave + 1;
785 Canrestore = Canrestore - 1;
786 }
787 //This is here to make sure the CWP is written
788 //no matter what. This ensures that the results
789 //are written in the new window as well.
790 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
791 }});
792 0x3E: decode FCN {
793 0x0: Priv::done({{
794 if(Tl == 0)
795 return new IllegalInstruction;
796
797 Cwp = Tstate<4:0>;
798 Pstate = Tstate<20:8>;
799 Asi = Tstate<31:24>;
800 Ccr = Tstate<39:32>;
801 Gl = Tstate<42:40>;
802 NPC = Tnpc;
803 NNPC = Tnpc + 4;
804 Tl = Tl - 1;
805 }});
806 0x1: Priv::retry({{
807 if(Tl == 0)
808 return new IllegalInstruction;
809 Cwp = Tstate<4:0>;
810 Pstate = Tstate<20:8>;
811 Asi = Tstate<31:24>;
812 Ccr = Tstate<39:32>;
813 Gl = Tstate<42:40>;
814 NPC = Tpc;
815 NNPC = Tnpc + 4;
816 Tl = Tl - 1;
817 }});
818 }
819 }
820 }
821 0x3: decode OP3 {
822 format Load {
823 0x00: lduw({{Rd = Mem.uw;}});
824 0x01: ldub({{Rd = Mem.ub;}});
825 0x02: lduh({{Rd = Mem.uhw;}});
826 0x03: ldd({{
827 uint64_t val = Mem.udw;
828 RdLow = val<31:0>;
829 RdHigh = val<63:32>;
830 }});
831 }
832 format Store {
833 0x04: stw({{Mem.uw = Rd.sw;}});
834 0x05: stb({{Mem.ub = Rd.sb;}});
835 0x06: sth({{Mem.uhw = Rd.shw;}});
836 0x07: std({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
837 }
838 format Load {
839 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
840 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
841 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
842 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
843 0x0D: ldstub({{
844 Rd = Mem.ub;
845 Mem.ub = 0xFF;
846 }});
847 }
848 0x0E: Store::stx({{Mem.udw = Rd}});
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