1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OP default Unknown::unknown()
37{
38 0x0: decode OP2
39 {
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 0x1: decode BPCC
45 {
46 0x0: bpcci(19, {{
47 if(passesCondition(Ccr<3:0>, COND2))
48 NNPC = xc->readPC() + disp;
49 else
50 handle_annul
51 }});
52 0x2: bpccx(19, {{
53 if(passesCondition(Ccr<7:4>, COND2))
54 NNPC = xc->readPC() + disp;
55 else
56 handle_annul
57 }});
58 }
59 0x2: bicc(22, {{
60 if(passesCondition(Ccr<3:0>, COND2))
61 NNPC = xc->readPC() + disp;
62 else
63 handle_annul
64 }});
65 }
66 0x3: decode RCOND2
67 {
68 format BranchSplit
69 {
70 0x1: bpreq({{
71 if(Rs1.sdw == 0)
72 NNPC = xc->readPC() + disp;
73 else
74 handle_annul
75 }});
76 0x2: bprle({{
77 if(Rs1.sdw <= 0)
78 NNPC = xc->readPC() + disp;
79 else
80 handle_annul
81 }});
82 0x3: bprl({{
83 if(Rs1.sdw < 0)
84 NNPC = xc->readPC() + disp;
85 else
86 handle_annul
87 }});
88 0x5: bprne({{
89 if(Rs1.sdw != 0)
90 NNPC = xc->readPC() + disp;
91 else
92 handle_annul
93 }});
94 0x6: bprg({{
95 if(Rs1.sdw > 0)
96 NNPC = xc->readPC() + disp;
97 else
98 handle_annul
99 }});
100 0x7: bprge({{
101 if(Rs1.sdw >= 0)
102 NNPC = xc->readPC() + disp;
103 else
104 handle_annul
105 }});
106 }
107 }
108 //SETHI (or NOP if rd == 0 and imm == 0)
| 1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OP default Unknown::unknown()
37{
38 0x0: decode OP2
39 {
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 0x1: decode BPCC
45 {
46 0x0: bpcci(19, {{
47 if(passesCondition(Ccr<3:0>, COND2))
48 NNPC = xc->readPC() + disp;
49 else
50 handle_annul
51 }});
52 0x2: bpccx(19, {{
53 if(passesCondition(Ccr<7:4>, COND2))
54 NNPC = xc->readPC() + disp;
55 else
56 handle_annul
57 }});
58 }
59 0x2: bicc(22, {{
60 if(passesCondition(Ccr<3:0>, COND2))
61 NNPC = xc->readPC() + disp;
62 else
63 handle_annul
64 }});
65 }
66 0x3: decode RCOND2
67 {
68 format BranchSplit
69 {
70 0x1: bpreq({{
71 if(Rs1.sdw == 0)
72 NNPC = xc->readPC() + disp;
73 else
74 handle_annul
75 }});
76 0x2: bprle({{
77 if(Rs1.sdw <= 0)
78 NNPC = xc->readPC() + disp;
79 else
80 handle_annul
81 }});
82 0x3: bprl({{
83 if(Rs1.sdw < 0)
84 NNPC = xc->readPC() + disp;
85 else
86 handle_annul
87 }});
88 0x5: bprne({{
89 if(Rs1.sdw != 0)
90 NNPC = xc->readPC() + disp;
91 else
92 handle_annul
93 }});
94 0x6: bprg({{
95 if(Rs1.sdw > 0)
96 NNPC = xc->readPC() + disp;
97 else
98 handle_annul
99 }});
100 0x7: bprge({{
101 if(Rs1.sdw >= 0)
102 NNPC = xc->readPC() + disp;
103 else
104 handle_annul
105 }});
106 }
107 }
108 //SETHI (or NOP if rd == 0 and imm == 0)
|
109 0x4: SetHi::sethi({{Rd = imm;}});
| 109 0x4: SetHi::sethi({{Rd.udw = imm;}});
|
110 0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
111 0x6: Trap::fbfcc({{fault = new FpDisabled;}});
112 }
113 0x1: BranchN::call(30, {{
114 R15 = xc->readPC();
115 NNPC = R15 + disp;
116 }});
117 0x2: decode OP3 {
118 format IntOp {
119 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
120 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
121 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
122 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
123 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
124 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}});
125 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}});
126 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
127 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
128 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
129 0x0A: umul({{
130 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
131 Y = Rd<63:32>;
132 }});
133 0x0B: smul({{
134 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
135 Y = Rd.sdw;
136 }});
137 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
138 0x0D: udivx({{
139 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
140 else Rd.udw = Rs1.udw / Rs2_or_imm13;
141 }});
142 0x0E: udiv({{
143 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
144 else
145 {
146 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
147 if(Rd.udw >> 32 != 0)
148 Rd.udw = 0xFFFFFFFF;
149 }
150 }});
151 0x0F: sdiv({{
152 if(Rs2_or_imm13.sdw == 0)
153 fault = new DivisionByZero;
154 else
155 {
156 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
157 if(Rd.udw<63:31> != 0)
158 Rd.udw = 0x7FFFFFFF;
159 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
160 Rd.udw = 0xFFFFFFFF80000000ULL;
161 }
162 }});
163 }
164 format IntOpCc {
165 0x10: addcc({{
166 int64_t resTemp, val2 = Rs2_or_imm13;
167 Rd = resTemp = Rs1 + val2;}},
168 {{(Rs1<31:0> + val2<31:0>)<32:>}},
169 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
170 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
171 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
172 );
173 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
174 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
175 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
176 0x14: subcc({{
177 int64_t val2 = Rs2_or_imm13;
178 Rd = Rs1 - val2;}},
179 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
180 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
181 {{(~(Rs1<63:1> + (~val2)<63:1> +
182 (Rs1 | ~val2)<0:>))<63:>}},
183 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
184 );
185 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
186 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
187 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
188 0x18: addccc({{
189 int64_t resTemp, val2 = Rs2_or_imm13;
190 int64_t carryin = Ccr<0:0>;
191 Rd = resTemp = Rs1 + val2 + carryin;}},
192 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
193 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
194 {{(Rs1<63:1> + val2<63:1> +
195 ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
196 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
197 );
198 0x1A: umulcc({{
199 uint64_t resTemp;
200 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
201 Y = resTemp<63:32>;}},
202 {{0}},{{0}},{{0}},{{0}});
203 0x1B: smulcc({{
204 int64_t resTemp;
205 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>;
206 Y = resTemp<63:32>;}},
207 {{0}},{{0}},{{0}},{{0}});
208 0x1C: subccc({{
209 int64_t resTemp, val2 = Rs2_or_imm13;
210 int64_t carryin = Ccr<0:0>;
211 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
212 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
213 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
214 {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
215 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
216 );
217 0x1D: udivxcc({{
218 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
219 else Rd = Rs1.udw / Rs2_or_imm13.udw;}}
220 ,{{0}},{{0}},{{0}},{{0}});
221 0x1E: udivcc({{
222 uint32_t resTemp, val2 = Rs2_or_imm13.udw;
223 int32_t overflow = 0;
224 if(val2 == 0) fault = new DivisionByZero;
225 else
226 {
227 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
228 overflow = (resTemp<63:32> != 0);
229 if(overflow) Rd = resTemp = 0xFFFFFFFF;
230 else Rd = resTemp;
231 } }},
232 {{0}},
233 {{overflow}},
234 {{0}},
235 {{0}}
236 );
237 0x1F: sdivcc({{
238 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
239 bool overflow = false, underflow = false;
240 if(val2 == 0) fault = new DivisionByZero;
241 else
242 {
243 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
244 overflow = (Rd<63:31> != 0);
245 underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF);
246 if(overflow) Rd = 0x7FFFFFFF;
247 else if(underflow) Rd = 0xFFFFFFFF80000000ULL;
248 } }},
249 {{0}},
250 {{overflow || underflow}},
251 {{0}},
252 {{0}}
253 );
254 0x20: taddcc({{
255 int64_t resTemp, val2 = Rs2_or_imm13;
256 Rd = resTemp = Rs1 + val2;
257 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
258 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
259 {{overflow}},
260 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
261 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
262 );
263 0x21: tsubcc({{
264 int64_t resTemp, val2 = Rs2_or_imm13;
265 Rd = resTemp = Rs1 + val2;
266 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
267 {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}},
268 {{overflow}},
269 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
270 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
271 );
272 0x22: taddcctv({{
273 int64_t val2 = Rs2_or_imm13;
274 Rd = Rs1 + val2;
275 int32_t overflow = Rs1<1:0> || val2<1:0> ||
276 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
277 if(overflow) fault = new TagOverflow;}},
278 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
279 {{overflow}},
280 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
281 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}}
282 );
283 0x23: tsubcctv({{
284 int64_t resTemp, val2 = Rs2_or_imm13;
285 Rd = resTemp = Rs1 + val2;
286 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
287 if(overflow) fault = new TagOverflow;}},
288 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
289 {{overflow}},
290 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
291 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
292 );
293 0x24: mulscc({{
294 int64_t resTemp, multiplicand = Rs2_or_imm13;
295 int32_t multiplier = Rs1<31:0>;
296 int32_t savedLSB = Rs1<0:>;
297 multiplier = multiplier<31:1> |
298 ((Ccr<3:3>
299 ^ Ccr<1:1>) << 32);
300 if(!Y<0:>)
301 multiplicand = 0;
302 Rd = resTemp = multiplicand + multiplier;
303 Y = Y<31:1> | (savedLSB << 31);}},
304 {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
305 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
306 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
307 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
308 );
309 }
310 format IntOp
311 {
312 0x25: decode X {
313 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
314 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
315 }
316 0x26: decode X {
317 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
318 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
319 }
320 0x27: decode X {
321 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
322 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
323 }
324 // XXX might want a format rdipr thing here
325 0x28: decode RS1 {
326 0xF: decode I {
327 0x0: Nop::stbar({{/*stuff*/}});
328 0x1: Nop::membar({{/*stuff*/}});
329 }
330 default: rdasr({{
331 Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault);
332 }});
333 }
334 0x29: HPriv::rdhpr({{
335 // XXX Need to protect with format that traps non-priv/priv
336 // access
337 Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault);
338 }});
339 0x2A: Priv::rdpr({{
340 // XXX Need to protect with format that traps non-priv
341 // access
342 Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault);
343 }});
344 0x2B: BasicOperate::flushw({{
345 if(NWindows - 2 - Cansave == 0)
346 {
347 if(Otherwin)
348 fault = new SpillNOther(Wstate<5:3>);
349 else
350 fault = new SpillNNormal(Wstate<2:0>);
351 }
352 }});
353 0x2C: decode MOVCC3
354 {
355 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
356 0x1: decode CC
357 {
358 0x0: movcci({{
359 if(passesCondition(Ccr<3:0>, COND4))
360 Rd = Rs2_or_imm11;
361 else
362 Rd = Rd;
363 }});
364 0x2: movccx({{
365 if(passesCondition(Ccr<7:4>, COND4))
366 Rd = Rs2_or_imm11;
367 else
368 Rd = Rd;
369 }});
370 }
371 }
372 0x2D: sdivx({{
373 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
374 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
375 }});
376 0x2E: decode RS1 {
377 0x0: IntOp::popc({{
378 int64_t count = 0;
379 uint64_t temp = Rs2_or_imm13;
380 //Count the 1s in the front 4bits until none are left
381 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
382 while(temp)
383 {
384 count += oneBits[temp & 0xF];
385 temp = temp >> 4;
386 }
387 Rd = count;
388 }});
389 }
390 0x2F: decode RCOND3
391 {
392 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
393 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
394 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
395 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
396 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
397 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
398 }
399 0x30: wrasr({{
400 xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13);
401 }});
402 0x31: decode FCN {
403 0x0: BasicOperate::saved({{/*Boogy Boogy*/}});
404 0x1: BasicOperate::restored({{/*Boogy Boogy*/}});
405 }
406 0x32: Priv::wrpr({{
407 // XXX Need to protect with format that traps non-priv
408 // access
409 fault = xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13);
410 }});
411 0x33: HPriv::wrhpr({{
412 // XXX Need to protect with format that traps non-priv/priv
413 // access
414 fault = xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
415 }});
416 0x34: decode OPF{
417 format BasicOperate{
418 0x01: fmovs({{
419 Frd.sf = Frs2.sf;
420 //fsr.ftt = fsr.cexc = 0
421 Fsr &= ~(7 << 14);
422 Fsr &= ~(0x1F);
423 }});
424 0x02: fmovd({{
425 Frd.df = Frs2.df;
426 //fsr.ftt = fsr.cexc = 0
427 Fsr &= ~(7 << 14);
428 Fsr &= ~(0x1F);
429 }});
430 0x03: Trap::fmovq({{fault = new FpDisabled;}});
431 0x05: fnegs({{
432 //XXX might want to explicitly flip the sign bit
433 //So cases with Nan and +/-0 don't do weird things
434 Frd.sf = -Frs2.sf;
435 //fsr.ftt = fsr.cexc = 0
436 Fsr &= ~(7 << 14);
437 Fsr &= ~(0x1F);
438 }});
439 0x06: fnegd({{
440 //XXX might want to explicitly flip the sign bit
441 //So cases with Nan and +/-0 don't do weird things
442 Frd.df = -Frs2.df;
443 //fsr.ftt = fsr.cexc = 0
444 Fsr &= ~(7 << 14);
445 Fsr &= ~(0x1F);
446 }});
447 0x07: Trap::fnegq({{fault = new FpDisabled;}});
448 0x09: fabss({{
449 //XXX this instruction should be tested individually
450 //Clear the sign bit
451 Frd.sf = (float)(~(1 << 31) & ((uint32_t)Frs2.sf));
452 //fsr.ftt = fsr.cexc = 0
453 Fsr &= ~(7 << 14);
454 Fsr &= ~(0x1F);
455 }});
456 0x0A: fabsd({{
457 //XXX this instruction should be tested individually
458 //Clear the sign bit
459 Frd.df = (float)(~((uint64_t)1 << 63) & ((uint64_t)Frs2.df));
460 //fsr.ftt = fsr.cexc = 0
461 Fsr &= ~(7 << 14);
462 Fsr &= ~(0x1F);
463 }});
464 0x0B: Trap::fabsq({{fault = new FpDisabled;}});
465 0x29: fsqrts({{Frd.sf = sqrt(Frs2.sf);}});
466 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}});
467 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
468 0x41: fadds({{Frd.sf = Frs1.sf + Frs2.sf;}});
469 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
470 0x43: Trap::faddq({{fault = new FpDisabled;}});
471 0x45: fsubs({{Frd.sf = Frs1.sf - Frs2.sf;}});
472 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
473 0x47: Trap::fsubq({{fault = new FpDisabled;}});
474 0x49: fmuls({{Frd.sf = Frs1.sf * Frs2.sf;}});
475 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
476 0x4B: Trap::fmulq({{fault = new FpDisabled;}});
477 0x4D: fdivs({{Frd.sf = Frs1.sf / Frs2.sf;}});
478 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
479 0x4F: Trap::fdivq({{fault = new FpDisabled;}});
480 0x69: fsmuld({{Frd.df = Frs1.sf * Frs2.sf;}});
481 0x6E: Trap::fdmulq({{fault = new FpDisabled;}});
482 0x81: fstox({{
483 Frd.df = (double)static_cast<int64_t>(Frs2.sf);
484 }});
485 0x82: fdtox({{
486 Frd.df = (double)static_cast<int64_t>(Frs2.df);
487 }});
488 0x83: Trap::fqtox({{fault = new FpDisabled;}});
489 0x84: fxtos({{
490 Frd.sf = static_cast<float>((int64_t)Frs2.df);
491 }});
492 0x88: fxtod({{
493 Frd.df = static_cast<double>((int64_t)Frs2.df);
494 }});
495 0x8C: Trap::fxtoq({{fault = new FpDisabled;}});
496 0xC4: fitos({{
497 Frd.sf = static_cast<float>((int32_t)Frs2.sf);
498 }});
499 0xC6: fdtos({{Frd.sf = Frs2.df;}});
500 0xC7: Trap::fqtos({{fault = new FpDisabled;}});
501 0xC8: fitod({{
502 Frd.df = static_cast<double>((int32_t)Frs2.sf);
503 }});
504 0xC9: fstod({{Frd.df = Frs2.sf;}});
505 0xCB: Trap::fqtod({{fault = new FpDisabled;}});
506 0xCC: Trap::fitoq({{fault = new FpDisabled;}});
507 0xCD: Trap::fstoq({{fault = new FpDisabled;}});
508 0xCE: Trap::fdtoq({{fault = new FpDisabled;}});
509 0xD1: fstoi({{
510 Frd.sf = (float)static_cast<int32_t>(Frs2.sf);
511 }});
512 0xD2: fdtoi({{
513 Frd.sf = (float)static_cast<int32_t>(Frs2.df);
514 }});
515 0xD3: Trap::fqtoi({{fault = new FpDisabled;}});
516 default: Trap::fpop1({{fault = new FpDisabled;}});
517 }
518 }
519 0x35: Trap::fpop2({{fault = new FpDisabled;}});
520 //This used to be just impdep1, but now it's a whole bunch
521 //of instructions
522 0x36: decode OPF{
523 0x00: Trap::edge8({{fault = new IllegalInstruction;}});
524 0x01: Trap::edge8n({{fault = new IllegalInstruction;}});
525 0x02: Trap::edge8l({{fault = new IllegalInstruction;}});
526 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}});
527 0x04: Trap::edge16({{fault = new IllegalInstruction;}});
528 0x05: Trap::edge16n({{fault = new IllegalInstruction;}});
529 0x06: Trap::edge16l({{fault = new IllegalInstruction;}});
530 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}});
531 0x08: Trap::edge32({{fault = new IllegalInstruction;}});
532 0x09: Trap::edge32n({{fault = new IllegalInstruction;}});
533 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}});
534 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}});
535 0x10: Trap::array8({{fault = new IllegalInstruction;}});
536 0x12: Trap::array16({{fault = new IllegalInstruction;}});
537 0x14: Trap::array32({{fault = new IllegalInstruction;}});
| 110 0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
111 0x6: Trap::fbfcc({{fault = new FpDisabled;}});
112 }
113 0x1: BranchN::call(30, {{
114 R15 = xc->readPC();
115 NNPC = R15 + disp;
116 }});
117 0x2: decode OP3 {
118 format IntOp {
119 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
120 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
121 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
122 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
123 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
124 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}});
125 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}});
126 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
127 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
128 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
129 0x0A: umul({{
130 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
131 Y = Rd<63:32>;
132 }});
133 0x0B: smul({{
134 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
135 Y = Rd.sdw;
136 }});
137 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
138 0x0D: udivx({{
139 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
140 else Rd.udw = Rs1.udw / Rs2_or_imm13;
141 }});
142 0x0E: udiv({{
143 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
144 else
145 {
146 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
147 if(Rd.udw >> 32 != 0)
148 Rd.udw = 0xFFFFFFFF;
149 }
150 }});
151 0x0F: sdiv({{
152 if(Rs2_or_imm13.sdw == 0)
153 fault = new DivisionByZero;
154 else
155 {
156 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
157 if(Rd.udw<63:31> != 0)
158 Rd.udw = 0x7FFFFFFF;
159 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
160 Rd.udw = 0xFFFFFFFF80000000ULL;
161 }
162 }});
163 }
164 format IntOpCc {
165 0x10: addcc({{
166 int64_t resTemp, val2 = Rs2_or_imm13;
167 Rd = resTemp = Rs1 + val2;}},
168 {{(Rs1<31:0> + val2<31:0>)<32:>}},
169 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
170 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
171 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
172 );
173 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
174 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
175 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
176 0x14: subcc({{
177 int64_t val2 = Rs2_or_imm13;
178 Rd = Rs1 - val2;}},
179 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
180 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
181 {{(~(Rs1<63:1> + (~val2)<63:1> +
182 (Rs1 | ~val2)<0:>))<63:>}},
183 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
184 );
185 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
186 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
187 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
188 0x18: addccc({{
189 int64_t resTemp, val2 = Rs2_or_imm13;
190 int64_t carryin = Ccr<0:0>;
191 Rd = resTemp = Rs1 + val2 + carryin;}},
192 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
193 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
194 {{(Rs1<63:1> + val2<63:1> +
195 ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
196 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
197 );
198 0x1A: umulcc({{
199 uint64_t resTemp;
200 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
201 Y = resTemp<63:32>;}},
202 {{0}},{{0}},{{0}},{{0}});
203 0x1B: smulcc({{
204 int64_t resTemp;
205 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>;
206 Y = resTemp<63:32>;}},
207 {{0}},{{0}},{{0}},{{0}});
208 0x1C: subccc({{
209 int64_t resTemp, val2 = Rs2_or_imm13;
210 int64_t carryin = Ccr<0:0>;
211 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
212 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
213 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
214 {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
215 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
216 );
217 0x1D: udivxcc({{
218 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
219 else Rd = Rs1.udw / Rs2_or_imm13.udw;}}
220 ,{{0}},{{0}},{{0}},{{0}});
221 0x1E: udivcc({{
222 uint32_t resTemp, val2 = Rs2_or_imm13.udw;
223 int32_t overflow = 0;
224 if(val2 == 0) fault = new DivisionByZero;
225 else
226 {
227 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
228 overflow = (resTemp<63:32> != 0);
229 if(overflow) Rd = resTemp = 0xFFFFFFFF;
230 else Rd = resTemp;
231 } }},
232 {{0}},
233 {{overflow}},
234 {{0}},
235 {{0}}
236 );
237 0x1F: sdivcc({{
238 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
239 bool overflow = false, underflow = false;
240 if(val2 == 0) fault = new DivisionByZero;
241 else
242 {
243 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
244 overflow = (Rd<63:31> != 0);
245 underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF);
246 if(overflow) Rd = 0x7FFFFFFF;
247 else if(underflow) Rd = 0xFFFFFFFF80000000ULL;
248 } }},
249 {{0}},
250 {{overflow || underflow}},
251 {{0}},
252 {{0}}
253 );
254 0x20: taddcc({{
255 int64_t resTemp, val2 = Rs2_or_imm13;
256 Rd = resTemp = Rs1 + val2;
257 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
258 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
259 {{overflow}},
260 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
261 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
262 );
263 0x21: tsubcc({{
264 int64_t resTemp, val2 = Rs2_or_imm13;
265 Rd = resTemp = Rs1 + val2;
266 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
267 {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}},
268 {{overflow}},
269 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
270 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
271 );
272 0x22: taddcctv({{
273 int64_t val2 = Rs2_or_imm13;
274 Rd = Rs1 + val2;
275 int32_t overflow = Rs1<1:0> || val2<1:0> ||
276 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
277 if(overflow) fault = new TagOverflow;}},
278 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
279 {{overflow}},
280 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
281 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}}
282 );
283 0x23: tsubcctv({{
284 int64_t resTemp, val2 = Rs2_or_imm13;
285 Rd = resTemp = Rs1 + val2;
286 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
287 if(overflow) fault = new TagOverflow;}},
288 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
289 {{overflow}},
290 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
291 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
292 );
293 0x24: mulscc({{
294 int64_t resTemp, multiplicand = Rs2_or_imm13;
295 int32_t multiplier = Rs1<31:0>;
296 int32_t savedLSB = Rs1<0:>;
297 multiplier = multiplier<31:1> |
298 ((Ccr<3:3>
299 ^ Ccr<1:1>) << 32);
300 if(!Y<0:>)
301 multiplicand = 0;
302 Rd = resTemp = multiplicand + multiplier;
303 Y = Y<31:1> | (savedLSB << 31);}},
304 {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
305 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
306 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
307 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
308 );
309 }
310 format IntOp
311 {
312 0x25: decode X {
313 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
314 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
315 }
316 0x26: decode X {
317 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
318 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
319 }
320 0x27: decode X {
321 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
322 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
323 }
324 // XXX might want a format rdipr thing here
325 0x28: decode RS1 {
326 0xF: decode I {
327 0x0: Nop::stbar({{/*stuff*/}});
328 0x1: Nop::membar({{/*stuff*/}});
329 }
330 default: rdasr({{
331 Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault);
332 }});
333 }
334 0x29: HPriv::rdhpr({{
335 // XXX Need to protect with format that traps non-priv/priv
336 // access
337 Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault);
338 }});
339 0x2A: Priv::rdpr({{
340 // XXX Need to protect with format that traps non-priv
341 // access
342 Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault);
343 }});
344 0x2B: BasicOperate::flushw({{
345 if(NWindows - 2 - Cansave == 0)
346 {
347 if(Otherwin)
348 fault = new SpillNOther(Wstate<5:3>);
349 else
350 fault = new SpillNNormal(Wstate<2:0>);
351 }
352 }});
353 0x2C: decode MOVCC3
354 {
355 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
356 0x1: decode CC
357 {
358 0x0: movcci({{
359 if(passesCondition(Ccr<3:0>, COND4))
360 Rd = Rs2_or_imm11;
361 else
362 Rd = Rd;
363 }});
364 0x2: movccx({{
365 if(passesCondition(Ccr<7:4>, COND4))
366 Rd = Rs2_or_imm11;
367 else
368 Rd = Rd;
369 }});
370 }
371 }
372 0x2D: sdivx({{
373 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
374 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
375 }});
376 0x2E: decode RS1 {
377 0x0: IntOp::popc({{
378 int64_t count = 0;
379 uint64_t temp = Rs2_or_imm13;
380 //Count the 1s in the front 4bits until none are left
381 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
382 while(temp)
383 {
384 count += oneBits[temp & 0xF];
385 temp = temp >> 4;
386 }
387 Rd = count;
388 }});
389 }
390 0x2F: decode RCOND3
391 {
392 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
393 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
394 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
395 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
396 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
397 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
398 }
399 0x30: wrasr({{
400 xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13);
401 }});
402 0x31: decode FCN {
403 0x0: BasicOperate::saved({{/*Boogy Boogy*/}});
404 0x1: BasicOperate::restored({{/*Boogy Boogy*/}});
405 }
406 0x32: Priv::wrpr({{
407 // XXX Need to protect with format that traps non-priv
408 // access
409 fault = xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13);
410 }});
411 0x33: HPriv::wrhpr({{
412 // XXX Need to protect with format that traps non-priv/priv
413 // access
414 fault = xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
415 }});
416 0x34: decode OPF{
417 format BasicOperate{
418 0x01: fmovs({{
419 Frd.sf = Frs2.sf;
420 //fsr.ftt = fsr.cexc = 0
421 Fsr &= ~(7 << 14);
422 Fsr &= ~(0x1F);
423 }});
424 0x02: fmovd({{
425 Frd.df = Frs2.df;
426 //fsr.ftt = fsr.cexc = 0
427 Fsr &= ~(7 << 14);
428 Fsr &= ~(0x1F);
429 }});
430 0x03: Trap::fmovq({{fault = new FpDisabled;}});
431 0x05: fnegs({{
432 //XXX might want to explicitly flip the sign bit
433 //So cases with Nan and +/-0 don't do weird things
434 Frd.sf = -Frs2.sf;
435 //fsr.ftt = fsr.cexc = 0
436 Fsr &= ~(7 << 14);
437 Fsr &= ~(0x1F);
438 }});
439 0x06: fnegd({{
440 //XXX might want to explicitly flip the sign bit
441 //So cases with Nan and +/-0 don't do weird things
442 Frd.df = -Frs2.df;
443 //fsr.ftt = fsr.cexc = 0
444 Fsr &= ~(7 << 14);
445 Fsr &= ~(0x1F);
446 }});
447 0x07: Trap::fnegq({{fault = new FpDisabled;}});
448 0x09: fabss({{
449 //XXX this instruction should be tested individually
450 //Clear the sign bit
451 Frd.sf = (float)(~(1 << 31) & ((uint32_t)Frs2.sf));
452 //fsr.ftt = fsr.cexc = 0
453 Fsr &= ~(7 << 14);
454 Fsr &= ~(0x1F);
455 }});
456 0x0A: fabsd({{
457 //XXX this instruction should be tested individually
458 //Clear the sign bit
459 Frd.df = (float)(~((uint64_t)1 << 63) & ((uint64_t)Frs2.df));
460 //fsr.ftt = fsr.cexc = 0
461 Fsr &= ~(7 << 14);
462 Fsr &= ~(0x1F);
463 }});
464 0x0B: Trap::fabsq({{fault = new FpDisabled;}});
465 0x29: fsqrts({{Frd.sf = sqrt(Frs2.sf);}});
466 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}});
467 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
468 0x41: fadds({{Frd.sf = Frs1.sf + Frs2.sf;}});
469 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
470 0x43: Trap::faddq({{fault = new FpDisabled;}});
471 0x45: fsubs({{Frd.sf = Frs1.sf - Frs2.sf;}});
472 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
473 0x47: Trap::fsubq({{fault = new FpDisabled;}});
474 0x49: fmuls({{Frd.sf = Frs1.sf * Frs2.sf;}});
475 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
476 0x4B: Trap::fmulq({{fault = new FpDisabled;}});
477 0x4D: fdivs({{Frd.sf = Frs1.sf / Frs2.sf;}});
478 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
479 0x4F: Trap::fdivq({{fault = new FpDisabled;}});
480 0x69: fsmuld({{Frd.df = Frs1.sf * Frs2.sf;}});
481 0x6E: Trap::fdmulq({{fault = new FpDisabled;}});
482 0x81: fstox({{
483 Frd.df = (double)static_cast<int64_t>(Frs2.sf);
484 }});
485 0x82: fdtox({{
486 Frd.df = (double)static_cast<int64_t>(Frs2.df);
487 }});
488 0x83: Trap::fqtox({{fault = new FpDisabled;}});
489 0x84: fxtos({{
490 Frd.sf = static_cast<float>((int64_t)Frs2.df);
491 }});
492 0x88: fxtod({{
493 Frd.df = static_cast<double>((int64_t)Frs2.df);
494 }});
495 0x8C: Trap::fxtoq({{fault = new FpDisabled;}});
496 0xC4: fitos({{
497 Frd.sf = static_cast<float>((int32_t)Frs2.sf);
498 }});
499 0xC6: fdtos({{Frd.sf = Frs2.df;}});
500 0xC7: Trap::fqtos({{fault = new FpDisabled;}});
501 0xC8: fitod({{
502 Frd.df = static_cast<double>((int32_t)Frs2.sf);
503 }});
504 0xC9: fstod({{Frd.df = Frs2.sf;}});
505 0xCB: Trap::fqtod({{fault = new FpDisabled;}});
506 0xCC: Trap::fitoq({{fault = new FpDisabled;}});
507 0xCD: Trap::fstoq({{fault = new FpDisabled;}});
508 0xCE: Trap::fdtoq({{fault = new FpDisabled;}});
509 0xD1: fstoi({{
510 Frd.sf = (float)static_cast<int32_t>(Frs2.sf);
511 }});
512 0xD2: fdtoi({{
513 Frd.sf = (float)static_cast<int32_t>(Frs2.df);
514 }});
515 0xD3: Trap::fqtoi({{fault = new FpDisabled;}});
516 default: Trap::fpop1({{fault = new FpDisabled;}});
517 }
518 }
519 0x35: Trap::fpop2({{fault = new FpDisabled;}});
520 //This used to be just impdep1, but now it's a whole bunch
521 //of instructions
522 0x36: decode OPF{
523 0x00: Trap::edge8({{fault = new IllegalInstruction;}});
524 0x01: Trap::edge8n({{fault = new IllegalInstruction;}});
525 0x02: Trap::edge8l({{fault = new IllegalInstruction;}});
526 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}});
527 0x04: Trap::edge16({{fault = new IllegalInstruction;}});
528 0x05: Trap::edge16n({{fault = new IllegalInstruction;}});
529 0x06: Trap::edge16l({{fault = new IllegalInstruction;}});
530 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}});
531 0x08: Trap::edge32({{fault = new IllegalInstruction;}});
532 0x09: Trap::edge32n({{fault = new IllegalInstruction;}});
533 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}});
534 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}});
535 0x10: Trap::array8({{fault = new IllegalInstruction;}});
536 0x12: Trap::array16({{fault = new IllegalInstruction;}});
537 0x14: Trap::array32({{fault = new IllegalInstruction;}});
|
538 0x18: BasicOperate::alignaddress({{
| 538 0x18: BasicOperate::alignaddr({{
|
539 uint64_t sum = Rs1 + Rs2;
| 539 uint64_t sum = Rs1 + Rs2;
|
540 Frd = sum & ~7;
| 540 Rd = sum & ~7;
|
541 Gsr = (Gsr & ~7) | (sum & 7);
542 }});
543 0x19: Trap::bmask({{fault = new IllegalInstruction;}});
544 0x1A: BasicOperate::alignaddresslittle({{
545 uint64_t sum = Rs1 + Rs2;
| 541 Gsr = (Gsr & ~7) | (sum & 7);
542 }});
543 0x19: Trap::bmask({{fault = new IllegalInstruction;}});
544 0x1A: BasicOperate::alignaddresslittle({{
545 uint64_t sum = Rs1 + Rs2;
|
546 Frd = sum & ~7;
| 546 Rd = sum & ~7;
|
547 Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
548 }});
549 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}});
550 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}});
551 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}});
552 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}});
553 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}});
554 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}});
555 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}});
556 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}});
557 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}});
558 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}});
559 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}});
560 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}});
561 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}});
562 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}});
563 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}});
564 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
565 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
566 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
567 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
568 0x48: BasicOperate::faligndata({{
569 uint64_t msbX = (uint64_t)Frs1;
570 uint64_t lsbX = (uint64_t)Frs2;
571 uint64_t msbShift = Gsr<2:0> * 8;
572 uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
573 uint64_t msbMask = ((uint64_t)(-1)) << msbShift;
574 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
575 Frd = ((msbX << msbShift) & msbMask) |
576 ((lsbX << lsbShift) & lsbMask);
577 }});
578 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
579 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}});
580 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}});
581 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}});
582 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}});
583 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}});
584 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}});
585 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}});
586 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}});
587 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}});
588 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}});
589 0x60: BasicOperate::fzero({{Frd.df = 0;}});
590 0x61: BasicOperate::fzeros({{Frd.sf = 0;}});
591 0x62: Trap::fnor({{fault = new IllegalInstruction;}});
592 0x63: Trap::fnors({{fault = new IllegalInstruction;}});
593 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}});
594 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}});
595 0x66: BasicOperate::fnot2({{
596 Frd.df = (double)(~((uint64_t)Frs2.df));
597 }});
598 0x67: BasicOperate::fnot2s({{
599 Frd.sf = (float)(~((uint32_t)Frs2.sf));
600 }});
601 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}});
602 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}});
603 0x6A: BasicOperate::fnot1({{
604 Frd.df = (double)(~((uint64_t)Frs1.df));
605 }});
606 0x6B: BasicOperate::fnot1s({{
607 Frd.sf = (float)(~((uint32_t)Frs1.sf));
608 }});
609 0x6C: Trap::fxor({{fault = new IllegalInstruction;}});
610 0x6D: Trap::fxors({{fault = new IllegalInstruction;}});
611 0x6E: Trap::fnand({{fault = new IllegalInstruction;}});
612 0x6F: Trap::fnands({{fault = new IllegalInstruction;}});
613 0x70: Trap::fand({{fault = new IllegalInstruction;}});
614 0x71: Trap::fands({{fault = new IllegalInstruction;}});
615 0x72: Trap::fxnor({{fault = new IllegalInstruction;}});
616 0x73: Trap::fxnors({{fault = new IllegalInstruction;}});
617 0x74: BasicOperate::fsrc1({{Frd.df = Frs1.df;}});
618 0x75: BasicOperate::fsrc1s({{Frd.sf = Frs1.sf;}});
619 0x76: Trap::fornot2({{fault = new IllegalInstruction;}});
620 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}});
621 0x78: BasicOperate::fsrc2({{Frd.df = Frs2.df;}});
622 0x79: BasicOperate::fsrc2s({{Frd.sf = Frs2.sf;}});
623 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}});
624 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}});
625 0x7C: Trap::for({{fault = new IllegalInstruction;}});
626 0x7D: Trap::fors({{fault = new IllegalInstruction;}});
627 0x7E: Trap::fone({{fault = new IllegalInstruction;}});
628 0x7F: Trap::fones({{fault = new IllegalInstruction;}});
629 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
630 0x81: Trap::siam({{fault = new IllegalInstruction;}});
631 }
632 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
633 0x38: Branch::jmpl({{
634 Addr target = Rs1 + Rs2_or_imm13;
635 if(target & 0x3)
636 fault = new MemAddressNotAligned;
637 else
638 {
639 Rd = xc->readPC();
640 NNPC = target;
641 }
642 }});
643 0x39: Branch::return({{
644 //If both MemAddressNotAligned and
645 //a fill trap happen, it's not clear
646 //which one should be returned.
647 Addr target = Rs1 + Rs2_or_imm13;
648 if(target & 0x3)
649 fault = new MemAddressNotAligned;
650 else
651 NNPC = target;
652 if(fault == NoFault)
653 {
654 //CWP should be set directly so that it always happens
655 //Also, this will allow writing to the new window and
656 //reading from the old one
657 Cwp = (Cwp - 1 + NWindows) % NWindows;
658 if(Canrestore == 0)
659 {
660 if(Otherwin)
661 fault = new FillNOther(Wstate<5:3>);
662 else
663 fault = new FillNNormal(Wstate<2:0>);
664 }
665 else
666 {
667 Rd = Rs1 + Rs2_or_imm13;
668 Cansave = Cansave + 1;
669 Canrestore = Canrestore - 1;
670 }
671 //This is here to make sure the CWP is written
672 //no matter what. This ensures that the results
673 //are written in the new window as well.
674 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
675 }
676 }});
677 0x3A: decode CC
678 {
679 0x0: Trap::tcci({{
680 if(passesCondition(Ccr<3:0>, COND2))
681 {
682#if FULL_SYSTEM
683 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
684 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
685 fault = new TrapInstruction(lTrapNum);
686#else
687 DPRINTF(Sparc, "The syscall number is %d\n", R1);
688 xc->syscall(R1);
689#endif
690 }
691 }});
692 0x2: Trap::tccx({{
693 if(passesCondition(Ccr<7:4>, COND2))
694 {
695#if FULL_SYSTEM
696 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
697 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
698 fault = new TrapInstruction(lTrapNum);
699#else
700 DPRINTF(Sparc, "The syscall number is %d\n", R1);
701 xc->syscall(R1);
702#endif
703 }
704 }});
705 }
706 0x3B: Nop::flush({{/*Instruction memory flush*/}});
707 0x3C: save({{
708 //CWP should be set directly so that it always happens
709 //Also, this will allow writing to the new window and
710 //reading from the old one
711 if(Cansave == 0)
712 {
713 if(Otherwin)
714 fault = new SpillNOther(Wstate<5:3>);
715 else
716 fault = new SpillNNormal(Wstate<2:0>);
717 Cwp = (Cwp + 2) % NWindows;
718 }
719 else if(Cleanwin - Canrestore == 0)
720 {
721 Cwp = (Cwp + 1) % NWindows;
722 fault = new CleanWindow;
723 }
724 else
725 {
726 Cwp = (Cwp + 1) % NWindows;
727 Rd = Rs1 + Rs2_or_imm13;
728 Cansave = Cansave - 1;
729 Canrestore = Canrestore + 1;
730 }
731 //This is here to make sure the CWP is written
732 //no matter what. This ensures that the results
733 //are written in the new window as well.
734 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
735 }});
736 0x3D: restore({{
737 //CWP should be set directly so that it always happens
738 //Also, this will allow writing to the new window and
739 //reading from the old one
740 Cwp = (Cwp - 1 + NWindows) % NWindows;
741 if(Canrestore == 0)
742 {
743 if(Otherwin)
744 fault = new FillNOther(Wstate<5:3>);
745 else
746 fault = new FillNNormal(Wstate<2:0>);
747 }
748 else
749 {
750 Rd = Rs1 + Rs2_or_imm13;
751 Cansave = Cansave + 1;
752 Canrestore = Canrestore - 1;
753 }
754 //This is here to make sure the CWP is written
755 //no matter what. This ensures that the results
756 //are written in the new window as well.
757 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
758 }});
759 0x3E: decode FCN {
760 0x0: Priv::done({{
761 if(Tl == 0)
762 return new IllegalInstruction;
763
764 Cwp = Tstate<4:0>;
765 Pstate = Tstate<20:8>;
766 Asi = Tstate<31:24>;
767 Ccr = Tstate<39:32>;
768 Gl = Tstate<42:40>;
769 NPC = Tnpc;
770 NNPC = Tnpc + 4;
771 Tl = Tl - 1;
772 }});
773 0x1: Priv::retry({{
774 if(Tl == 0)
775 return new IllegalInstruction;
776 Cwp = Tstate<4:0>;
777 Pstate = Tstate<20:8>;
778 Asi = Tstate<31:24>;
779 Ccr = Tstate<39:32>;
780 Gl = Tstate<42:40>;
781 NPC = Tpc;
782 NNPC = Tnpc + 4;
783 Tl = Tl - 1;
784 }});
785 }
786 }
787 }
788 0x3: decode OP3 {
789 format Load {
790 0x00: lduw({{Rd = Mem;}}, {{32}});
791 0x01: ldub({{Rd = Mem;}}, {{8}});
792 0x02: lduh({{Rd = Mem;}}, {{16}});
793 0x03: ldd({{
794 uint64_t val = Mem;
795 RdLow = val<31:0>;
796 RdHigh = val<63:32>;
797 }}, {{64}});
798 }
799 format Store {
800 0x04: stw({{Mem = Rd.sw;}}, {{32}});
801 0x05: stb({{Mem = Rd.sb;}}, {{8}});
802 0x06: sth({{Mem = Rd.shw;}}, {{16}});
803 0x07: std({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}});
804 }
805 format Load {
806 0x08: ldsw({{Rd = (int32_t)Mem;}}, {{32}});
807 0x09: ldsb({{Rd = (int8_t)Mem;}}, {{8}});
808 0x0A: ldsh({{Rd = (int16_t)Mem;}}, {{16}});
809 0x0B: ldx({{Rd = (int64_t)Mem;}}, {{64}});
810 0x0D: ldstub({{
811 Rd = Mem;
812 Mem = 0xFF;
813 }}, {{8}});
814 }
815 0x0E: Store::stx({{Mem = Rd}}, {{64}});
816 0x0F: LoadStore::swap({{
817 uint32_t temp = Rd;
818 Rd = Mem;
819 Mem = temp;
820 }}, {{32}});
821 format Load {
822 0x10: lduwa({{Rd = Mem;}}, {{32}});
823 0x11: lduba({{Rd = Mem;}}, {{8}});
824 0x12: lduha({{Rd = Mem;}}, {{16}});
825 0x13: ldda({{
826 uint64_t val = Mem;
827 RdLow = val<31:0>;
828 RdHigh = val<63:32>;
829 }}, {{64}});
830 }
831 format Store {
832 0x14: stwa({{Mem = Rd;}}, {{32}});
833 0x15: stba({{Mem = Rd;}}, {{8}});
834 0x16: stha({{Mem = Rd;}}, {{16}});
835 0x17: stda({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}});
836 }
837 format Load {
838 0x18: ldswa({{Rd = (int32_t)Mem;}}, {{32}});
839 0x19: ldsba({{Rd = (int8_t)Mem;}}, {{8}});
840 0x1A: ldsha({{Rd = (int16_t)Mem;}}, {{16}});
841 0x1B: ldxa({{Rd = (int64_t)Mem;}}, {{64}});
842 }
843 0x1D: LoadStore::ldstuba({{
844 Rd = Mem;
845 Mem = 0xFF;
846 }}, {{8}});
847 0x1E: Store::stxa({{Mem = Rd}}, {{64}});
848 0x1F: LoadStore::swapa({{
849 uint32_t temp = Rd;
850 Rd = Mem;
851 Mem = temp;
852 }}, {{32}});
853 format Trap {
854 0x20: Load::ldf({{Frd.sf = ((float)Mem);}}, {{32}});
855 0x21: decode X {
856 0x0: Load::ldfsr({{Fsr = Mem<31:0> | Fsr<63:32>;}}, {{32}});
857 0x1: Load::ldxfsr({{Fsr = Mem;}}, {{64}});
858 }
859 0x22: ldqf({{fault = new FpDisabled;}});
860 0x23: Load::lddf({{Frd.df = ((double)Mem);}}, {{64}});
861 0x24: Store::stf({{Mem = ((int32_t)Frd.sf);}}, {{32}});
862 0x25: decode X {
863 0x0: Store::stfsr({{Mem = Fsr<31:0>;}}, {{32}});
864 0x1: Store::stxfsr({{Mem = Fsr;}}, {{64}});
865 }
866 0x26: stqf({{fault = new FpDisabled;}});
867 0x27: Store::stdf({{Mem = ((int64_t)Frd.df);}}, {{64}});
868 0x2D: Nop::prefetch({{ }});
869 0x30: Load::ldfa({{Frd.sf = ((float)Mem);}}, {{32}});
870 0x32: ldqfa({{fault = new FpDisabled;}});
871 0x33: Load::lddfa({{Frd.df = ((double)Mem);}}, {{64}});
872 0x34: Store::stfa({{Mem = ((int32_t)Frd.sf);}}, {{32}});
873 0x36: stqfa({{fault = new FpDisabled;}});
874 //XXX need to work in the ASI thing
875 0x37: Store::stdfa({{Mem = ((uint64_t)Frd.df);}}, {{64}});
876 0x3C: Cas::casa({{
877 uint64_t val = Mem.uw;
878 if(Rs2.uw == val)
879 Mem.uw = Rd.uw;
880 Rd.uw = val;
881 }});
882 0x3D: Nop::prefetcha({{ }});
883 0x3E: Cas::casxa({{
884 uint64_t val = Mem.udw;
885 if(Rs2 == val)
886 Mem.udw = Rd;
887 Rd = val;
888 }});
889 }
890 }
891}
| 547 Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
548 }});
549 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}});
550 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}});
551 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}});
552 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}});
553 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}});
554 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}});
555 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}});
556 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}});
557 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}});
558 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}});
559 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}});
560 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}});
561 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}});
562 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}});
563 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}});
564 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
565 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
566 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
567 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
568 0x48: BasicOperate::faligndata({{
569 uint64_t msbX = (uint64_t)Frs1;
570 uint64_t lsbX = (uint64_t)Frs2;
571 uint64_t msbShift = Gsr<2:0> * 8;
572 uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
573 uint64_t msbMask = ((uint64_t)(-1)) << msbShift;
574 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
575 Frd = ((msbX << msbShift) & msbMask) |
576 ((lsbX << lsbShift) & lsbMask);
577 }});
578 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
579 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}});
580 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}});
581 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}});
582 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}});
583 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}});
584 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}});
585 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}});
586 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}});
587 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}});
588 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}});
589 0x60: BasicOperate::fzero({{Frd.df = 0;}});
590 0x61: BasicOperate::fzeros({{Frd.sf = 0;}});
591 0x62: Trap::fnor({{fault = new IllegalInstruction;}});
592 0x63: Trap::fnors({{fault = new IllegalInstruction;}});
593 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}});
594 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}});
595 0x66: BasicOperate::fnot2({{
596 Frd.df = (double)(~((uint64_t)Frs2.df));
597 }});
598 0x67: BasicOperate::fnot2s({{
599 Frd.sf = (float)(~((uint32_t)Frs2.sf));
600 }});
601 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}});
602 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}});
603 0x6A: BasicOperate::fnot1({{
604 Frd.df = (double)(~((uint64_t)Frs1.df));
605 }});
606 0x6B: BasicOperate::fnot1s({{
607 Frd.sf = (float)(~((uint32_t)Frs1.sf));
608 }});
609 0x6C: Trap::fxor({{fault = new IllegalInstruction;}});
610 0x6D: Trap::fxors({{fault = new IllegalInstruction;}});
611 0x6E: Trap::fnand({{fault = new IllegalInstruction;}});
612 0x6F: Trap::fnands({{fault = new IllegalInstruction;}});
613 0x70: Trap::fand({{fault = new IllegalInstruction;}});
614 0x71: Trap::fands({{fault = new IllegalInstruction;}});
615 0x72: Trap::fxnor({{fault = new IllegalInstruction;}});
616 0x73: Trap::fxnors({{fault = new IllegalInstruction;}});
617 0x74: BasicOperate::fsrc1({{Frd.df = Frs1.df;}});
618 0x75: BasicOperate::fsrc1s({{Frd.sf = Frs1.sf;}});
619 0x76: Trap::fornot2({{fault = new IllegalInstruction;}});
620 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}});
621 0x78: BasicOperate::fsrc2({{Frd.df = Frs2.df;}});
622 0x79: BasicOperate::fsrc2s({{Frd.sf = Frs2.sf;}});
623 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}});
624 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}});
625 0x7C: Trap::for({{fault = new IllegalInstruction;}});
626 0x7D: Trap::fors({{fault = new IllegalInstruction;}});
627 0x7E: Trap::fone({{fault = new IllegalInstruction;}});
628 0x7F: Trap::fones({{fault = new IllegalInstruction;}});
629 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
630 0x81: Trap::siam({{fault = new IllegalInstruction;}});
631 }
632 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
633 0x38: Branch::jmpl({{
634 Addr target = Rs1 + Rs2_or_imm13;
635 if(target & 0x3)
636 fault = new MemAddressNotAligned;
637 else
638 {
639 Rd = xc->readPC();
640 NNPC = target;
641 }
642 }});
643 0x39: Branch::return({{
644 //If both MemAddressNotAligned and
645 //a fill trap happen, it's not clear
646 //which one should be returned.
647 Addr target = Rs1 + Rs2_or_imm13;
648 if(target & 0x3)
649 fault = new MemAddressNotAligned;
650 else
651 NNPC = target;
652 if(fault == NoFault)
653 {
654 //CWP should be set directly so that it always happens
655 //Also, this will allow writing to the new window and
656 //reading from the old one
657 Cwp = (Cwp - 1 + NWindows) % NWindows;
658 if(Canrestore == 0)
659 {
660 if(Otherwin)
661 fault = new FillNOther(Wstate<5:3>);
662 else
663 fault = new FillNNormal(Wstate<2:0>);
664 }
665 else
666 {
667 Rd = Rs1 + Rs2_or_imm13;
668 Cansave = Cansave + 1;
669 Canrestore = Canrestore - 1;
670 }
671 //This is here to make sure the CWP is written
672 //no matter what. This ensures that the results
673 //are written in the new window as well.
674 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
675 }
676 }});
677 0x3A: decode CC
678 {
679 0x0: Trap::tcci({{
680 if(passesCondition(Ccr<3:0>, COND2))
681 {
682#if FULL_SYSTEM
683 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
684 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
685 fault = new TrapInstruction(lTrapNum);
686#else
687 DPRINTF(Sparc, "The syscall number is %d\n", R1);
688 xc->syscall(R1);
689#endif
690 }
691 }});
692 0x2: Trap::tccx({{
693 if(passesCondition(Ccr<7:4>, COND2))
694 {
695#if FULL_SYSTEM
696 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
697 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
698 fault = new TrapInstruction(lTrapNum);
699#else
700 DPRINTF(Sparc, "The syscall number is %d\n", R1);
701 xc->syscall(R1);
702#endif
703 }
704 }});
705 }
706 0x3B: Nop::flush({{/*Instruction memory flush*/}});
707 0x3C: save({{
708 //CWP should be set directly so that it always happens
709 //Also, this will allow writing to the new window and
710 //reading from the old one
711 if(Cansave == 0)
712 {
713 if(Otherwin)
714 fault = new SpillNOther(Wstate<5:3>);
715 else
716 fault = new SpillNNormal(Wstate<2:0>);
717 Cwp = (Cwp + 2) % NWindows;
718 }
719 else if(Cleanwin - Canrestore == 0)
720 {
721 Cwp = (Cwp + 1) % NWindows;
722 fault = new CleanWindow;
723 }
724 else
725 {
726 Cwp = (Cwp + 1) % NWindows;
727 Rd = Rs1 + Rs2_or_imm13;
728 Cansave = Cansave - 1;
729 Canrestore = Canrestore + 1;
730 }
731 //This is here to make sure the CWP is written
732 //no matter what. This ensures that the results
733 //are written in the new window as well.
734 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
735 }});
736 0x3D: restore({{
737 //CWP should be set directly so that it always happens
738 //Also, this will allow writing to the new window and
739 //reading from the old one
740 Cwp = (Cwp - 1 + NWindows) % NWindows;
741 if(Canrestore == 0)
742 {
743 if(Otherwin)
744 fault = new FillNOther(Wstate<5:3>);
745 else
746 fault = new FillNNormal(Wstate<2:0>);
747 }
748 else
749 {
750 Rd = Rs1 + Rs2_or_imm13;
751 Cansave = Cansave + 1;
752 Canrestore = Canrestore - 1;
753 }
754 //This is here to make sure the CWP is written
755 //no matter what. This ensures that the results
756 //are written in the new window as well.
757 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
758 }});
759 0x3E: decode FCN {
760 0x0: Priv::done({{
761 if(Tl == 0)
762 return new IllegalInstruction;
763
764 Cwp = Tstate<4:0>;
765 Pstate = Tstate<20:8>;
766 Asi = Tstate<31:24>;
767 Ccr = Tstate<39:32>;
768 Gl = Tstate<42:40>;
769 NPC = Tnpc;
770 NNPC = Tnpc + 4;
771 Tl = Tl - 1;
772 }});
773 0x1: Priv::retry({{
774 if(Tl == 0)
775 return new IllegalInstruction;
776 Cwp = Tstate<4:0>;
777 Pstate = Tstate<20:8>;
778 Asi = Tstate<31:24>;
779 Ccr = Tstate<39:32>;
780 Gl = Tstate<42:40>;
781 NPC = Tpc;
782 NNPC = Tnpc + 4;
783 Tl = Tl - 1;
784 }});
785 }
786 }
787 }
788 0x3: decode OP3 {
789 format Load {
790 0x00: lduw({{Rd = Mem;}}, {{32}});
791 0x01: ldub({{Rd = Mem;}}, {{8}});
792 0x02: lduh({{Rd = Mem;}}, {{16}});
793 0x03: ldd({{
794 uint64_t val = Mem;
795 RdLow = val<31:0>;
796 RdHigh = val<63:32>;
797 }}, {{64}});
798 }
799 format Store {
800 0x04: stw({{Mem = Rd.sw;}}, {{32}});
801 0x05: stb({{Mem = Rd.sb;}}, {{8}});
802 0x06: sth({{Mem = Rd.shw;}}, {{16}});
803 0x07: std({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}});
804 }
805 format Load {
806 0x08: ldsw({{Rd = (int32_t)Mem;}}, {{32}});
807 0x09: ldsb({{Rd = (int8_t)Mem;}}, {{8}});
808 0x0A: ldsh({{Rd = (int16_t)Mem;}}, {{16}});
809 0x0B: ldx({{Rd = (int64_t)Mem;}}, {{64}});
810 0x0D: ldstub({{
811 Rd = Mem;
812 Mem = 0xFF;
813 }}, {{8}});
814 }
815 0x0E: Store::stx({{Mem = Rd}}, {{64}});
816 0x0F: LoadStore::swap({{
817 uint32_t temp = Rd;
818 Rd = Mem;
819 Mem = temp;
820 }}, {{32}});
821 format Load {
822 0x10: lduwa({{Rd = Mem;}}, {{32}});
823 0x11: lduba({{Rd = Mem;}}, {{8}});
824 0x12: lduha({{Rd = Mem;}}, {{16}});
825 0x13: ldda({{
826 uint64_t val = Mem;
827 RdLow = val<31:0>;
828 RdHigh = val<63:32>;
829 }}, {{64}});
830 }
831 format Store {
832 0x14: stwa({{Mem = Rd;}}, {{32}});
833 0x15: stba({{Mem = Rd;}}, {{8}});
834 0x16: stha({{Mem = Rd;}}, {{16}});
835 0x17: stda({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}});
836 }
837 format Load {
838 0x18: ldswa({{Rd = (int32_t)Mem;}}, {{32}});
839 0x19: ldsba({{Rd = (int8_t)Mem;}}, {{8}});
840 0x1A: ldsha({{Rd = (int16_t)Mem;}}, {{16}});
841 0x1B: ldxa({{Rd = (int64_t)Mem;}}, {{64}});
842 }
843 0x1D: LoadStore::ldstuba({{
844 Rd = Mem;
845 Mem = 0xFF;
846 }}, {{8}});
847 0x1E: Store::stxa({{Mem = Rd}}, {{64}});
848 0x1F: LoadStore::swapa({{
849 uint32_t temp = Rd;
850 Rd = Mem;
851 Mem = temp;
852 }}, {{32}});
853 format Trap {
854 0x20: Load::ldf({{Frd.sf = ((float)Mem);}}, {{32}});
855 0x21: decode X {
856 0x0: Load::ldfsr({{Fsr = Mem<31:0> | Fsr<63:32>;}}, {{32}});
857 0x1: Load::ldxfsr({{Fsr = Mem;}}, {{64}});
858 }
859 0x22: ldqf({{fault = new FpDisabled;}});
860 0x23: Load::lddf({{Frd.df = ((double)Mem);}}, {{64}});
861 0x24: Store::stf({{Mem = ((int32_t)Frd.sf);}}, {{32}});
862 0x25: decode X {
863 0x0: Store::stfsr({{Mem = Fsr<31:0>;}}, {{32}});
864 0x1: Store::stxfsr({{Mem = Fsr;}}, {{64}});
865 }
866 0x26: stqf({{fault = new FpDisabled;}});
867 0x27: Store::stdf({{Mem = ((int64_t)Frd.df);}}, {{64}});
868 0x2D: Nop::prefetch({{ }});
869 0x30: Load::ldfa({{Frd.sf = ((float)Mem);}}, {{32}});
870 0x32: ldqfa({{fault = new FpDisabled;}});
871 0x33: Load::lddfa({{Frd.df = ((double)Mem);}}, {{64}});
872 0x34: Store::stfa({{Mem = ((int32_t)Frd.sf);}}, {{32}});
873 0x36: stqfa({{fault = new FpDisabled;}});
874 //XXX need to work in the ASI thing
875 0x37: Store::stdfa({{Mem = ((uint64_t)Frd.df);}}, {{64}});
876 0x3C: Cas::casa({{
877 uint64_t val = Mem.uw;
878 if(Rs2.uw == val)
879 Mem.uw = Rd.uw;
880 Rd.uw = val;
881 }});
882 0x3D: Nop::prefetcha({{ }});
883 0x3E: Cas::casxa({{
884 uint64_t val = Mem.udw;
885 if(Rs2 == val)
886 Mem.udw = Rd;
887 Rd = val;
888 }});
889 }
890 }
891}
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