1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OP default Unknown::unknown()
37{
38 0x0: decode OP2
39 {
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 0x1: decode BPCC
45 {
46 0x0: bpcci(19, {{
47 if(passesCondition(Ccr<3:0>, COND2))
48 NNPC = xc->readPC() + disp;
49 else
50 handle_annul
51 }});
52 0x2: bpccx(19, {{
53 if(passesCondition(Ccr<7:4>, COND2))
54 NNPC = xc->readPC() + disp;
55 else
56 handle_annul
57 }});
58 }
59 0x2: bicc(22, {{
60 if(passesCondition(Ccr<3:0>, COND2))
61 NNPC = xc->readPC() + disp;
62 else
63 handle_annul
64 }});
65 }
66 0x3: decode RCOND2
67 {
68 format BranchSplit
69 {
70 0x1: bpreq({{
71 if(Rs1.sdw == 0)
72 NNPC = xc->readPC() + disp;
73 else
74 handle_annul
75 }});
76 0x2: bprle({{
77 if(Rs1.sdw <= 0)
78 NNPC = xc->readPC() + disp;
79 else
80 handle_annul
81 }});
82 0x3: bprl({{
83 if(Rs1.sdw < 0)
84 NNPC = xc->readPC() + disp;
85 else
86 handle_annul
87 }});
88 0x5: bprne({{
89 if(Rs1.sdw != 0)
90 NNPC = xc->readPC() + disp;
91 else
92 handle_annul
93 }});
94 0x6: bprg({{
95 if(Rs1.sdw > 0)
96 NNPC = xc->readPC() + disp;
97 else
98 handle_annul
99 }});
100 0x7: bprge({{
101 if(Rs1.sdw >= 0)
102 NNPC = xc->readPC() + disp;
103 else
104 handle_annul
105 }});
106 }
107 }
108 //SETHI (or NOP if rd == 0 and imm == 0)
109 0x4: SetHi::sethi({{Rd = imm;}});
110 0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
111 0x6: Trap::fbfcc({{fault = new FpDisabled;}});
112 }
113 0x1: BranchN::call(30, {{
114 R15 = xc->readPC();
115 NNPC = R15 + disp;
116 }});
117 0x2: decode OP3 {
118 format IntOp {
119 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
120 0x01: and({{Rd = Rs1.udw & Rs2_or_imm13;}});
121 0x02: or({{Rd = Rs1.udw | Rs2_or_imm13;}});
122 0x03: xor({{Rd = Rs1.udw ^ Rs2_or_imm13;}});
123 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
124 0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm13;}});
125 0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm13;}});
126 0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm13);}});
127 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
128 0x09: mulx({{Rd = Rs1 * Rs2_or_imm13;}});
129 0x0A: umul({{
130 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
131 Y = Rd<63:32>;
132 }});
133 0x0B: smul({{
134 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
135 Y = Rd.sdw;
136 }});
| 1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright
9// notice, this list of conditions and the following disclaimer in the
10// documentation and/or other materials provided with the distribution;
11// neither the name of the copyright holders nor the names of its
12// contributors may be used to endorse or promote products derived from
13// this software without specific prior written permission.
14//
15// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26//
27// Authors: Ali Saidi
28// Gabe Black
29// Steve Reinhardt
30
31////////////////////////////////////////////////////////////////////
32//
33// The actual decoder specification
34//
35
36decode OP default Unknown::unknown()
37{
38 0x0: decode OP2
39 {
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 0x1: decode BPCC
45 {
46 0x0: bpcci(19, {{
47 if(passesCondition(Ccr<3:0>, COND2))
48 NNPC = xc->readPC() + disp;
49 else
50 handle_annul
51 }});
52 0x2: bpccx(19, {{
53 if(passesCondition(Ccr<7:4>, COND2))
54 NNPC = xc->readPC() + disp;
55 else
56 handle_annul
57 }});
58 }
59 0x2: bicc(22, {{
60 if(passesCondition(Ccr<3:0>, COND2))
61 NNPC = xc->readPC() + disp;
62 else
63 handle_annul
64 }});
65 }
66 0x3: decode RCOND2
67 {
68 format BranchSplit
69 {
70 0x1: bpreq({{
71 if(Rs1.sdw == 0)
72 NNPC = xc->readPC() + disp;
73 else
74 handle_annul
75 }});
76 0x2: bprle({{
77 if(Rs1.sdw <= 0)
78 NNPC = xc->readPC() + disp;
79 else
80 handle_annul
81 }});
82 0x3: bprl({{
83 if(Rs1.sdw < 0)
84 NNPC = xc->readPC() + disp;
85 else
86 handle_annul
87 }});
88 0x5: bprne({{
89 if(Rs1.sdw != 0)
90 NNPC = xc->readPC() + disp;
91 else
92 handle_annul
93 }});
94 0x6: bprg({{
95 if(Rs1.sdw > 0)
96 NNPC = xc->readPC() + disp;
97 else
98 handle_annul
99 }});
100 0x7: bprge({{
101 if(Rs1.sdw >= 0)
102 NNPC = xc->readPC() + disp;
103 else
104 handle_annul
105 }});
106 }
107 }
108 //SETHI (or NOP if rd == 0 and imm == 0)
109 0x4: SetHi::sethi({{Rd = imm;}});
110 0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
111 0x6: Trap::fbfcc({{fault = new FpDisabled;}});
112 }
113 0x1: BranchN::call(30, {{
114 R15 = xc->readPC();
115 NNPC = R15 + disp;
116 }});
117 0x2: decode OP3 {
118 format IntOp {
119 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
120 0x01: and({{Rd = Rs1.udw & Rs2_or_imm13;}});
121 0x02: or({{Rd = Rs1.udw | Rs2_or_imm13;}});
122 0x03: xor({{Rd = Rs1.udw ^ Rs2_or_imm13;}});
123 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
124 0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm13;}});
125 0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm13;}});
126 0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm13);}});
127 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
128 0x09: mulx({{Rd = Rs1 * Rs2_or_imm13;}});
129 0x0A: umul({{
130 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
131 Y = Rd<63:32>;
132 }});
133 0x0B: smul({{
134 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
135 Y = Rd.sdw;
136 }});
|
137 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 + Ccr<0:0>}});
| 137 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
|
138 0x0D: udivx({{
139 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
140 else Rd.udw = Rs1.udw / Rs2_or_imm13;
141 }});
142 0x0E: udiv({{
143 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
144 else
145 {
146 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
147 if(Rd.udw >> 32 != 0)
148 Rd.udw = 0xFFFFFFFF;
149 }
150 }});
151 0x0F: sdiv({{
152 if(Rs2_or_imm13.sdw == 0)
153 fault = new DivisionByZero;
154 else
155 {
156 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
157 if(Rd.udw<63:31> != 0)
158 Rd.udw = 0x7FFFFFFF;
159 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
160 Rd.udw = 0xFFFFFFFF80000000ULL;
161 }
162 }});
163 }
164 format IntOpCc {
165 0x10: addcc({{
166 int64_t resTemp, val2 = Rs2_or_imm13;
167 Rd = resTemp = Rs1 + val2;}},
168 {{(Rs1<31:0> + val2<31:0>)<32:>}},
169 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
170 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
171 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
172 );
173 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
174 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
175 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
176 0x14: subcc({{
177 int64_t val2 = Rs2_or_imm13;
178 Rd = Rs1 - val2;}},
179 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
180 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
181 {{(~(Rs1<63:1> + (~val2)<63:1> +
182 (Rs1 | ~val2)<0:>))<63:>}},
183 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
184 );
185 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
186 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
187 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
188 0x18: addccc({{
189 int64_t resTemp, val2 = Rs2_or_imm13;
190 int64_t carryin = Ccr<0:0>;
191 Rd = resTemp = Rs1 + val2 + carryin;}},
192 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
193 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
194 {{(Rs1<63:1> + val2<63:1> +
195 ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
196 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
197 );
198 0x1A: umulcc({{
199 uint64_t resTemp;
200 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
201 Y = resTemp<63:32>;}},
202 {{0}},{{0}},{{0}},{{0}});
203 0x1B: smulcc({{
204 int64_t resTemp;
205 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>;
206 Y = resTemp<63:32>;}},
207 {{0}},{{0}},{{0}},{{0}});
208 0x1C: subccc({{
209 int64_t resTemp, val2 = Rs2_or_imm13;
210 int64_t carryin = Ccr<0:0>;
| 138 0x0D: udivx({{
139 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
140 else Rd.udw = Rs1.udw / Rs2_or_imm13;
141 }});
142 0x0E: udiv({{
143 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
144 else
145 {
146 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
147 if(Rd.udw >> 32 != 0)
148 Rd.udw = 0xFFFFFFFF;
149 }
150 }});
151 0x0F: sdiv({{
152 if(Rs2_or_imm13.sdw == 0)
153 fault = new DivisionByZero;
154 else
155 {
156 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
157 if(Rd.udw<63:31> != 0)
158 Rd.udw = 0x7FFFFFFF;
159 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
160 Rd.udw = 0xFFFFFFFF80000000ULL;
161 }
162 }});
163 }
164 format IntOpCc {
165 0x10: addcc({{
166 int64_t resTemp, val2 = Rs2_or_imm13;
167 Rd = resTemp = Rs1 + val2;}},
168 {{(Rs1<31:0> + val2<31:0>)<32:>}},
169 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
170 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
171 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
172 );
173 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
174 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
175 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
176 0x14: subcc({{
177 int64_t val2 = Rs2_or_imm13;
178 Rd = Rs1 - val2;}},
179 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
180 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
181 {{(~(Rs1<63:1> + (~val2)<63:1> +
182 (Rs1 | ~val2)<0:>))<63:>}},
183 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
184 );
185 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
186 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
187 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
188 0x18: addccc({{
189 int64_t resTemp, val2 = Rs2_or_imm13;
190 int64_t carryin = Ccr<0:0>;
191 Rd = resTemp = Rs1 + val2 + carryin;}},
192 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
193 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
194 {{(Rs1<63:1> + val2<63:1> +
195 ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
196 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
197 );
198 0x1A: umulcc({{
199 uint64_t resTemp;
200 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
201 Y = resTemp<63:32>;}},
202 {{0}},{{0}},{{0}},{{0}});
203 0x1B: smulcc({{
204 int64_t resTemp;
205 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>;
206 Y = resTemp<63:32>;}},
207 {{0}},{{0}},{{0}},{{0}});
208 0x1C: subccc({{
209 int64_t resTemp, val2 = Rs2_or_imm13;
210 int64_t carryin = Ccr<0:0>;
|
211 Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}},
| 211 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
|
212 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
213 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
214 {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
215 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
216 );
217 0x1D: udivxcc({{
218 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
219 else Rd = Rs1.udw / Rs2_or_imm13.udw;}}
220 ,{{0}},{{0}},{{0}},{{0}});
221 0x1E: udivcc({{
222 uint32_t resTemp, val2 = Rs2_or_imm13.udw;
223 int32_t overflow;
224 if(val2 == 0) fault = new DivisionByZero;
225 else
226 {
227 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
228 overflow = (resTemp<63:32> != 0);
229 if(overflow) Rd = resTemp = 0xFFFFFFFF;
230 else Rd = resTemp;
231 } }},
232 {{0}},
233 {{overflow}},
234 {{0}},
235 {{0}}
236 );
237 0x1F: sdivcc({{
238 int32_t resTemp, val2 = Rs2_or_imm13.sdw;
239 int32_t overflow, underflow;
240 if(val2 == 0) fault = new DivisionByZero;
241 else
242 {
243 Rd = resTemp = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
244 overflow = (resTemp<63:31> != 0);
245 underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
246 if(overflow) Rd = resTemp = 0x7FFFFFFF;
247 else if(underflow) Rd = resTemp = 0xFFFFFFFF80000000ULL;
248 else Rd = resTemp;
249 } }},
250 {{0}},
251 {{overflow || underflow}},
252 {{0}},
253 {{0}}
254 );
255 0x20: taddcc({{
256 int64_t resTemp, val2 = Rs2_or_imm13;
257 Rd = resTemp = Rs1 + val2;
258 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
259 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
260 {{overflow}},
261 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
262 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
263 );
264 0x21: tsubcc({{
265 int64_t resTemp, val2 = Rs2_or_imm13;
266 Rd = resTemp = Rs1 + val2;
267 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
268 {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}},
269 {{overflow}},
270 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
271 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
272 );
273 0x22: taddcctv({{
274 int64_t resTemp, val2 = Rs2_or_imm13;
| 212 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
213 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
214 {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
215 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
216 );
217 0x1D: udivxcc({{
218 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
219 else Rd = Rs1.udw / Rs2_or_imm13.udw;}}
220 ,{{0}},{{0}},{{0}},{{0}});
221 0x1E: udivcc({{
222 uint32_t resTemp, val2 = Rs2_or_imm13.udw;
223 int32_t overflow;
224 if(val2 == 0) fault = new DivisionByZero;
225 else
226 {
227 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
228 overflow = (resTemp<63:32> != 0);
229 if(overflow) Rd = resTemp = 0xFFFFFFFF;
230 else Rd = resTemp;
231 } }},
232 {{0}},
233 {{overflow}},
234 {{0}},
235 {{0}}
236 );
237 0x1F: sdivcc({{
238 int32_t resTemp, val2 = Rs2_or_imm13.sdw;
239 int32_t overflow, underflow;
240 if(val2 == 0) fault = new DivisionByZero;
241 else
242 {
243 Rd = resTemp = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
244 overflow = (resTemp<63:31> != 0);
245 underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
246 if(overflow) Rd = resTemp = 0x7FFFFFFF;
247 else if(underflow) Rd = resTemp = 0xFFFFFFFF80000000ULL;
248 else Rd = resTemp;
249 } }},
250 {{0}},
251 {{overflow || underflow}},
252 {{0}},
253 {{0}}
254 );
255 0x20: taddcc({{
256 int64_t resTemp, val2 = Rs2_or_imm13;
257 Rd = resTemp = Rs1 + val2;
258 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
259 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
260 {{overflow}},
261 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
262 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
263 );
264 0x21: tsubcc({{
265 int64_t resTemp, val2 = Rs2_or_imm13;
266 Rd = resTemp = Rs1 + val2;
267 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
268 {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}},
269 {{overflow}},
270 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
271 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
272 );
273 0x22: taddcctv({{
274 int64_t resTemp, val2 = Rs2_or_imm13;
|
275 Rd = resTemp = Rs1 + val2;
276 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
| 275 Rd = Rs1 + val2;
276 int32_t overflow = Rs1<1:0> || val2<1:0> ||
277 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
|
277 if(overflow) fault = new TagOverflow;}},
278 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
279 {{overflow}},
280 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
281 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
282 );
283 0x23: tsubcctv({{
284 int64_t resTemp, val2 = Rs2_or_imm13;
285 Rd = resTemp = Rs1 + val2;
286 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
287 if(overflow) fault = new TagOverflow;}},
288 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
289 {{overflow}},
290 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
291 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
292 );
293 0x24: mulscc({{
294 int64_t resTemp, multiplicand = Rs2_or_imm13;
295 int32_t multiplier = Rs1<31:0>;
296 int32_t savedLSB = Rs1<0:>;
297 multiplier = multiplier<31:1> |
298 ((Ccr<3:3>
299 ^ Ccr<1:1>) << 32);
300 if(!Y<0:>)
301 multiplicand = 0;
302 Rd = resTemp = multiplicand + multiplier;
303 Y = Y<31:1> | (savedLSB << 31);}},
304 {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
305 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
306 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
307 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
308 );
309 }
310 format IntOp
311 {
312 0x25: decode X {
313 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
314 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
315 }
316 0x26: decode X {
317 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
318 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
319 }
320 0x27: decode X {
321 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
322 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
323 }
324 // XXX might want a format rdipr thing here
| 278 if(overflow) fault = new TagOverflow;}},
279 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
280 {{overflow}},
281 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
282 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
283 );
284 0x23: tsubcctv({{
285 int64_t resTemp, val2 = Rs2_or_imm13;
286 Rd = resTemp = Rs1 + val2;
287 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
288 if(overflow) fault = new TagOverflow;}},
289 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
290 {{overflow}},
291 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
292 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
293 );
294 0x24: mulscc({{
295 int64_t resTemp, multiplicand = Rs2_or_imm13;
296 int32_t multiplier = Rs1<31:0>;
297 int32_t savedLSB = Rs1<0:>;
298 multiplier = multiplier<31:1> |
299 ((Ccr<3:3>
300 ^ Ccr<1:1>) << 32);
301 if(!Y<0:>)
302 multiplicand = 0;
303 Rd = resTemp = multiplicand + multiplier;
304 Y = Y<31:1> | (savedLSB << 31);}},
305 {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
306 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
307 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
308 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
309 );
310 }
311 format IntOp
312 {
313 0x25: decode X {
314 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
315 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
316 }
317 0x26: decode X {
318 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
319 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
320 }
321 0x27: decode X {
322 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
323 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
324 }
325 // XXX might want a format rdipr thing here
|
325 0x28: rdasr({{
| 326 0x28: decode RS1 {
327 0xF: decode I {
328 0x0: Nop::stbar({{/*stuff*/}});
329 0x1: Nop::membar({{/*stuff*/}});
330 }
331 default: rdasr({{
|
326 Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault);
| 332 Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault);
|
327 }});
| 333 }});
334 }
|
328 0x29: HPriv::rdhpr({{
329 // XXX Need to protect with format that traps non-priv/priv
330 // access
331 Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault);
332 }});
333 0x2A: Priv::rdpr({{
334 // XXX Need to protect with format that traps non-priv
335 // access
336 Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault);
337 }});
338 0x2B: BasicOperate::flushw({{
339 if(NWindows - 2 - Cansave == 0)
340 {
341 if(Otherwin)
342 fault = new SpillNOther(Wstate<5:3>);
343 else
344 fault = new SpillNNormal(Wstate<2:0>);
345 }
346 }});
347 0x2C: decode MOVCC3
348 {
349 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
350 0x1: decode CC
351 {
352 0x0: movcci({{
353 if(passesCondition(Ccr<3:0>, COND4))
354 Rd = Rs2_or_imm11;
355 else
356 Rd = Rd;
357 }});
358 0x2: movccx({{
359 if(passesCondition(Ccr<7:4>, COND4))
360 Rd = Rs2_or_imm11;
361 else
362 Rd = Rd;
363 }});
364 }
365 }
366 0x2D: sdivx({{
367 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
368 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
369 }});
370 0x2E: decode RS1 {
371 0x0: IntOp::popc({{
372 int64_t count = 0;
373 uint64_t temp = Rs2_or_imm13;
374 //Count the 1s in the front 4bits until none are left
375 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
376 while(temp)
377 {
378 count += oneBits[temp & 0xF];
379 temp = temp >> 4;
380 }
381 Rd = count;
382 }});
383 }
384 0x2F: decode RCOND3
385 {
386 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
387 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
388 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
389 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
390 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
391 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
392 }
393 0x30: wrasr({{
394 xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13);
395 }});
396 0x31: decode FCN {
397 0x0: BasicOperate::saved({{/*Boogy Boogy*/}});
398 0x1: BasicOperate::restored({{/*Boogy Boogy*/}});
399 }
400 0x32: Priv::wrpr({{
401 // XXX Need to protect with format that traps non-priv
402 // access
403 fault = xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13);
404 }});
405 0x33: HPriv::wrhpr({{
406 // XXX Need to protect with format that traps non-priv/priv
407 // access
408 fault = xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
409 }});
| 335 0x29: HPriv::rdhpr({{
336 // XXX Need to protect with format that traps non-priv/priv
337 // access
338 Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault);
339 }});
340 0x2A: Priv::rdpr({{
341 // XXX Need to protect with format that traps non-priv
342 // access
343 Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault);
344 }});
345 0x2B: BasicOperate::flushw({{
346 if(NWindows - 2 - Cansave == 0)
347 {
348 if(Otherwin)
349 fault = new SpillNOther(Wstate<5:3>);
350 else
351 fault = new SpillNNormal(Wstate<2:0>);
352 }
353 }});
354 0x2C: decode MOVCC3
355 {
356 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
357 0x1: decode CC
358 {
359 0x0: movcci({{
360 if(passesCondition(Ccr<3:0>, COND4))
361 Rd = Rs2_or_imm11;
362 else
363 Rd = Rd;
364 }});
365 0x2: movccx({{
366 if(passesCondition(Ccr<7:4>, COND4))
367 Rd = Rs2_or_imm11;
368 else
369 Rd = Rd;
370 }});
371 }
372 }
373 0x2D: sdivx({{
374 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
375 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
376 }});
377 0x2E: decode RS1 {
378 0x0: IntOp::popc({{
379 int64_t count = 0;
380 uint64_t temp = Rs2_or_imm13;
381 //Count the 1s in the front 4bits until none are left
382 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
383 while(temp)
384 {
385 count += oneBits[temp & 0xF];
386 temp = temp >> 4;
387 }
388 Rd = count;
389 }});
390 }
391 0x2F: decode RCOND3
392 {
393 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
394 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
395 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
396 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
397 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
398 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
399 }
400 0x30: wrasr({{
401 xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13);
402 }});
403 0x31: decode FCN {
404 0x0: BasicOperate::saved({{/*Boogy Boogy*/}});
405 0x1: BasicOperate::restored({{/*Boogy Boogy*/}});
406 }
407 0x32: Priv::wrpr({{
408 // XXX Need to protect with format that traps non-priv
409 // access
410 fault = xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13);
411 }});
412 0x33: HPriv::wrhpr({{
413 // XXX Need to protect with format that traps non-priv/priv
414 // access
415 fault = xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
416 }});
|
410 0x34: Trap::fpop1({{fault = new FpDisabled;}});
| 417 0x34: decode OPF{
418 0x01: Trap::fmovs({{fault = new FpDisabled;}});
419 0x02: Trap::fmovd({{fault = new FpDisabled;}});
420 0x03: Trap::fmovq({{fault = new FpDisabled;}});
421 0x05: Trap::fnegs({{fault = new FpDisabled;}});
422 0x06: Trap::fnegd({{fault = new FpDisabled;}});
423 0x07: Trap::fnegq({{fault = new FpDisabled;}});
424 0x09: Trap::fabss({{fault = new FpDisabled;}});
425 0x0A: Trap::fabsd({{fault = new FpDisabled;}});
426 0x0B: Trap::fabsq({{fault = new FpDisabled;}});
427 0x29: Trap::fsqrts({{fault = new FpDisabled;}});
428 0x2A: Trap::fsqrtd({{fault = new FpDisabled;}});
429 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
430 0x41: Trap::fadds({{fault = new FpDisabled;}});
431 0x42: BasicOperate::faddd({{Frd = Frs1 + Frs2;}});
432 0x43: Trap::faddq({{fault = new FpDisabled;}});
433 0x45: Trap::fsubs({{fault = new FpDisabled;}});
434 0x46: Trap::fsubd({{fault = new FpDisabled;}});
435 0x47: Trap::fsubq({{fault = new FpDisabled;}});
436 0x49: Trap::fmuls({{fault = new FpDisabled;}});
437 0x4A: BasicOperate::fmuld({{Frd = Frs1.sf * Frs2.sf;}});
438 0x4B: Trap::fmulq({{fault = new FpDisabled;}});
439 0x4D: Trap::fdivs({{fault = new FpDisabled;}});
440 0x4E: Trap::fdivd({{fault = new FpDisabled;}});
441 0x4F: Trap::fdivq({{fault = new FpDisabled;}});
442 0x69: Trap::fsmuld({{fault = new FpDisabled;}});
443 0x6E: Trap::fdmulq({{fault = new FpDisabled;}});
444 0x81: Trap::fstox({{fault = new FpDisabled;}});
445 0x82: Trap::fdtox({{fault = new FpDisabled;}});
446 0x83: Trap::fqtox({{fault = new FpDisabled;}});
447 0x84: Trap::fxtos({{fault = new FpDisabled;}});
448 0x88: Trap::fxtod({{fault = new FpDisabled;}});
449 0x8C: Trap::fxtoq({{fault = new FpDisabled;}});
450 0xC4: Trap::fitos({{fault = new FpDisabled;}});
451 0xC6: Trap::fdtos({{fault = new FpDisabled;}});
452 0xC7: Trap::fqtos({{fault = new FpDisabled;}});
453 0xC8: Trap::fitod({{fault = new FpDisabled;}});
454 0xC9: Trap::fstod({{fault = new FpDisabled;}});
455 0xCB: Trap::fqtod({{fault = new FpDisabled;}});
456 0xCC: Trap::fitoq({{fault = new FpDisabled;}});
457 0xCD: Trap::fstoq({{fault = new FpDisabled;}});
458 0xCE: Trap::fdtoq({{fault = new FpDisabled;}});
459 0xD1: Trap::fstoi({{fault = new FpDisabled;}});
460 0xD2: Trap::fdtoi({{fault = new FpDisabled;}});
461 0xD3: Trap::fqtoi({{fault = new FpDisabled;}});
462 default: Trap::fpop1({{fault = new FpDisabled;}});
463 }
|
411 0x35: Trap::fpop2({{fault = new FpDisabled;}});
| 464 0x35: Trap::fpop2({{fault = new FpDisabled;}});
|
| 465 //This used to be just impdep1, but now it's a whole bunch
466 //of instructions
467 0x36: decode OPF{
468 0x00: Trap::edge8({{fault = new IllegalInstruction;}});
469 0x01: Trap::edge8n({{fault = new IllegalInstruction;}});
470 0x02: Trap::edge8l({{fault = new IllegalInstruction;}});
471 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}});
472 0x04: Trap::edge16({{fault = new IllegalInstruction;}});
473 0x05: Trap::edge16n({{fault = new IllegalInstruction;}});
474 0x06: Trap::edge16l({{fault = new IllegalInstruction;}});
475 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}});
476 0x08: Trap::edge32({{fault = new IllegalInstruction;}});
477 0x09: Trap::edge32n({{fault = new IllegalInstruction;}});
478 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}});
479 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}});
480 0x10: Trap::array8({{fault = new IllegalInstruction;}});
481 0x12: Trap::array16({{fault = new IllegalInstruction;}});
482 0x14: Trap::array32({{fault = new IllegalInstruction;}});
483 0x18: Trap::alignaddress({{fault = new IllegalInstruction;}});
484 0x19: Trap::bmask({{fault = new IllegalInstruction;}});
485 0x1A: Trap::alignaddresslittle({{fault = new IllegalInstruction;}});
486 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}});
487 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}});
488 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}});
489 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}});
490 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}});
491 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}});
492 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}});
493 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}});
494 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}});
495 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}});
496 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}});
497 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}});
498 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}});
499 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}});
500 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}});
501 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
502 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
503 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
504 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
505 0x48: Trap::faligndata({{fault = new IllegalInstruction;}});
506 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
507 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}});
508 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}});
509 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}});
510 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}});
511 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}});
512 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}});
513 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}});
514 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}});
515 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}});
516 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}});
517 0x60: BasicOperate::fzero({{Frd = 0;}});
518 0x61: Trap::fzeros({{fault = new IllegalInstruction;}});
519 0x62: Trap::fnor({{fault = new IllegalInstruction;}});
520 0x63: Trap::fnors({{fault = new IllegalInstruction;}});
521 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}});
522 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}});
523 0x66: Trap::fnot2({{fault = new IllegalInstruction;}});
524 0x67: Trap::fnot2s({{fault = new IllegalInstruction;}});
525 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}});
526 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}});
527 0x6A: Trap::fnot1({{fault = new IllegalInstruction;}});
528 0x6B: Trap::fnot1s({{fault = new IllegalInstruction;}});
529 0x6C: Trap::fxor({{fault = new IllegalInstruction;}});
530 0x6D: Trap::fxors({{fault = new IllegalInstruction;}});
531 0x6E: Trap::fnand({{fault = new IllegalInstruction;}});
532 0x6F: Trap::fnands({{fault = new IllegalInstruction;}});
533 0x70: Trap::fand({{fault = new IllegalInstruction;}});
534 0x71: Trap::fands({{fault = new IllegalInstruction;}});
535 0x72: Trap::fxnor({{fault = new IllegalInstruction;}});
536 0x73: Trap::fxnors({{fault = new IllegalInstruction;}});
537 0x74: Trap::fsrc1({{fault = new IllegalInstruction;}});
538 0x75: Trap::fsrc1s({{fault = new IllegalInstruction;}});
539 0x76: Trap::fornot2({{fault = new IllegalInstruction;}});
540 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}});
541 0x78: Trap::fsrc2({{fault = new IllegalInstruction;}});
542 0x79: Trap::fsrc2s({{fault = new IllegalInstruction;}});
543 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}});
544 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}});
545 0x7C: Trap::for({{fault = new IllegalInstruction;}});
546 0x7D: Trap::fors({{fault = new IllegalInstruction;}});
547 0x7E: Trap::fone({{fault = new IllegalInstruction;}});
548 0x7F: Trap::fones({{fault = new IllegalInstruction;}});
549 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
550 0x81: Trap::siam({{fault = new IllegalInstruction;}});
551 }
552 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
|
412 0x38: Branch::jmpl({{
413 Addr target = Rs1 + Rs2_or_imm13;
414 if(target & 0x3)
415 fault = new MemAddressNotAligned;
416 else
417 {
418 Rd = xc->readPC();
419 NNPC = target;
420 }
421 }});
422 0x39: Branch::return({{
423 //If both MemAddressNotAligned and
424 //a fill trap happen, it's not clear
425 //which one should be returned.
426 Addr target = Rs1 + Rs2_or_imm13;
427 if(target & 0x3)
428 fault = new MemAddressNotAligned;
429 else
430 NNPC = target;
431 if(fault == NoFault)
432 {
433 //CWP should be set directly so that it always happens
434 //Also, this will allow writing to the new window and
435 //reading from the old one
436 Cwp = (Cwp - 1 + NWindows) % NWindows;
437 if(Canrestore == 0)
438 {
439 if(Otherwin)
440 fault = new FillNOther(Wstate<5:3>);
441 else
442 fault = new FillNNormal(Wstate<2:0>);
443 }
444 else
445 {
446 Rd = Rs1 + Rs2_or_imm13;
447 Cansave = Cansave + 1;
448 Canrestore = Canrestore - 1;
449 }
450 //This is here to make sure the CWP is written
451 //no matter what. This ensures that the results
452 //are written in the new window as well.
453 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
454 }
455 }});
456 0x3A: decode CC
457 {
458 0x0: Trap::tcci({{
459 if(passesCondition(Ccr<3:0>, COND2))
460 {
461 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
462 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
463#if FULL_SYSTEM
464 fault = new TrapInstruction(lTrapNum);
465#else
466 DPRINTF(Sparc, "The syscall number is %d\n", R1);
467 xc->syscall(R1);
468#endif
469 }
470 }});
471 0x2: Trap::tccx({{
472 if(passesCondition(Ccr<7:4>, COND2))
473 {
474 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
475 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
476#if FULL_SYSTEM
477 fault = new TrapInstruction(lTrapNum);
478#else
479 DPRINTF(Sparc, "The syscall number is %d\n", R1);
480 xc->syscall(R1);
481#endif
482 }
483 }});
484 }
485 0x3B: Nop::flush({{/*Instruction memory flush*/}});
486 0x3C: save({{
487 //CWP should be set directly so that it always happens
488 //Also, this will allow writing to the new window and
489 //reading from the old one
490 if(Cansave == 0)
491 {
492 if(Otherwin)
493 fault = new SpillNOther(Wstate<5:3>);
494 else
495 fault = new SpillNNormal(Wstate<2:0>);
496 Cwp = (Cwp + 2) % NWindows;
497 }
498 else if(Cleanwin - Canrestore == 0)
499 {
500 Cwp = (Cwp + 1) % NWindows;
501 fault = new CleanWindow;
502 }
503 else
504 {
505 Cwp = (Cwp + 1) % NWindows;
506 Rd = Rs1 + Rs2_or_imm13;
507 Cansave = Cansave - 1;
508 Canrestore = Canrestore + 1;
509 }
510 //This is here to make sure the CWP is written
511 //no matter what. This ensures that the results
512 //are written in the new window as well.
513 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
514 }});
515 0x3D: restore({{
516 //CWP should be set directly so that it always happens
517 //Also, this will allow writing to the new window and
518 //reading from the old one
519 Cwp = (Cwp - 1 + NWindows) % NWindows;
520 if(Canrestore == 0)
521 {
522 if(Otherwin)
523 fault = new FillNOther(Wstate<5:3>);
524 else
525 fault = new FillNNormal(Wstate<2:0>);
526 }
527 else
528 {
529 Rd = Rs1 + Rs2_or_imm13;
530 Cansave = Cansave + 1;
531 Canrestore = Canrestore - 1;
532 }
533 //This is here to make sure the CWP is written
534 //no matter what. This ensures that the results
535 //are written in the new window as well.
536 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
537 }});
538 0x3E: decode FCN {
539 0x0: Priv::done({{
540 if(Tl == 0)
541 return new IllegalInstruction;
542
543 Cwp = Tstate<4:0>;
544 Pstate = Tstate<20:8>;
545 Asi = Tstate<31:24>;
546 Ccr = Tstate<39:32>;
547 Gl = Tstate<42:40>;
548 NPC = Tnpc;
549 NNPC = Tnpc + 4;
550 Tl = Tl - 1;
551 }});
552 0x1: Priv::retry({{
553 if(Tl == 0)
554 return new IllegalInstruction;
555 Cwp = Tstate<4:0>;
556 Pstate = Tstate<20:8>;
557 Asi = Tstate<31:24>;
558 Ccr = Tstate<39:32>;
559 Gl = Tstate<42:40>;
560 NPC = Tpc;
561 NNPC = Tnpc + 4;
562 Tl = Tl - 1;
563 }});
564 }
565 }
566 }
567 0x3: decode OP3 {
568 format Load {
569 0x00: lduw({{Rd = Mem;}}, {{32}});
570 0x01: ldub({{Rd = Mem;}}, {{8}});
571 0x02: lduh({{Rd = Mem;}}, {{16}});
572 0x03: ldd({{
573 uint64_t val = Mem;
574 RdLow = val<31:0>;
575 RdHigh = val<63:32>;
576 }}, {{64}});
577 }
578 format Store {
579 0x04: stw({{Mem = Rd.sw;}}, {{32}});
580 0x05: stb({{Mem = Rd.sb;}}, {{8}});
581 0x06: sth({{Mem = Rd.shw;}}, {{16}});
582 0x07: std({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}});
583 }
584 format Load {
585 0x08: ldsw({{Rd = (int32_t)Mem;}}, {{32}});
586 0x09: ldsb({{Rd = (int8_t)Mem;}}, {{8}});
587 0x0A: ldsh({{Rd = (int16_t)Mem;}}, {{16}});
588 0x0B: ldx({{Rd = (int64_t)Mem;}}, {{64}});
589 0x0D: ldstub({{
590 Rd = Mem;
591 Mem = 0xFF;
592 }}, {{8}});
593 }
594 0x0E: Store::stx({{Mem = Rd}}, {{64}});
595 0x0F: LoadStore::swap({{
596 uint32_t temp = Rd;
597 Rd = Mem;
598 Mem = temp;
599 }}, {{32}});
600 format Load {
601 0x10: lduwa({{Rd = Mem;}}, {{32}});
602 0x11: lduba({{Rd = Mem;}}, {{8}});
603 0x12: lduha({{Rd = Mem;}}, {{16}});
604 0x13: ldda({{
605 uint64_t val = Mem;
606 RdLow = val<31:0>;
607 RdHigh = val<63:32>;
608 }}, {{64}});
609 }
610 format Store {
611 0x14: stwa({{Mem = Rd;}}, {{32}});
612 0x15: stba({{Mem = Rd;}}, {{8}});
613 0x16: stha({{Mem = Rd;}}, {{16}});
614 0x17: stda({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}});
615 }
616 format Load {
617 0x18: ldswa({{Rd = (int32_t)Mem;}}, {{32}});
618 0x19: ldsba({{Rd = (int8_t)Mem;}}, {{8}});
619 0x1A: ldsha({{Rd = (int16_t)Mem;}}, {{16}});
620 0x1B: ldxa({{Rd = (int64_t)Mem;}}, {{64}});
621 }
622 0x1D: LoadStore::ldstuba({{
623 Rd = Mem;
624 Mem = 0xFF;
625 }}, {{8}});
626 0x1E: Store::stxa({{Mem = Rd}}, {{64}});
627 0x1F: LoadStore::swapa({{
628 uint32_t temp = Rd;
629 Rd = Mem;
630 Mem = temp;
631 }}, {{32}});
632 format Trap {
633 0x20: ldf({{fault = new FpDisabled;}});
634 0x21: decode X {
635 0x0: Load::ldfsr({{Fsr = Mem<31:0> | Fsr<63:32>;}}, {{32}});
636 0x1: Load::ldxfsr({{Fsr = Mem;}}, {{64}});
637 }
638 0x22: ldqf({{fault = new FpDisabled;}});
639 0x23: lddf({{fault = new FpDisabled;}});
640 0x24: stf({{fault = new FpDisabled;}});
641 0x25: decode X {
642 0x0: Store::stfsr({{Mem = Fsr<31:0>;}}, {{32}});
643 0x1: Store::stxfsr({{Mem = Fsr;}}, {{64}});
644 }
645 0x26: stqf({{fault = new FpDisabled;}});
646 0x27: stdf({{fault = new FpDisabled;}});
647 0x2D: Nop::prefetch({{ }});
| 553 0x38: Branch::jmpl({{
554 Addr target = Rs1 + Rs2_or_imm13;
555 if(target & 0x3)
556 fault = new MemAddressNotAligned;
557 else
558 {
559 Rd = xc->readPC();
560 NNPC = target;
561 }
562 }});
563 0x39: Branch::return({{
564 //If both MemAddressNotAligned and
565 //a fill trap happen, it's not clear
566 //which one should be returned.
567 Addr target = Rs1 + Rs2_or_imm13;
568 if(target & 0x3)
569 fault = new MemAddressNotAligned;
570 else
571 NNPC = target;
572 if(fault == NoFault)
573 {
574 //CWP should be set directly so that it always happens
575 //Also, this will allow writing to the new window and
576 //reading from the old one
577 Cwp = (Cwp - 1 + NWindows) % NWindows;
578 if(Canrestore == 0)
579 {
580 if(Otherwin)
581 fault = new FillNOther(Wstate<5:3>);
582 else
583 fault = new FillNNormal(Wstate<2:0>);
584 }
585 else
586 {
587 Rd = Rs1 + Rs2_or_imm13;
588 Cansave = Cansave + 1;
589 Canrestore = Canrestore - 1;
590 }
591 //This is here to make sure the CWP is written
592 //no matter what. This ensures that the results
593 //are written in the new window as well.
594 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
595 }
596 }});
597 0x3A: decode CC
598 {
599 0x0: Trap::tcci({{
600 if(passesCondition(Ccr<3:0>, COND2))
601 {
602 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
603 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
604#if FULL_SYSTEM
605 fault = new TrapInstruction(lTrapNum);
606#else
607 DPRINTF(Sparc, "The syscall number is %d\n", R1);
608 xc->syscall(R1);
609#endif
610 }
611 }});
612 0x2: Trap::tccx({{
613 if(passesCondition(Ccr<7:4>, COND2))
614 {
615 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
616 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
617#if FULL_SYSTEM
618 fault = new TrapInstruction(lTrapNum);
619#else
620 DPRINTF(Sparc, "The syscall number is %d\n", R1);
621 xc->syscall(R1);
622#endif
623 }
624 }});
625 }
626 0x3B: Nop::flush({{/*Instruction memory flush*/}});
627 0x3C: save({{
628 //CWP should be set directly so that it always happens
629 //Also, this will allow writing to the new window and
630 //reading from the old one
631 if(Cansave == 0)
632 {
633 if(Otherwin)
634 fault = new SpillNOther(Wstate<5:3>);
635 else
636 fault = new SpillNNormal(Wstate<2:0>);
637 Cwp = (Cwp + 2) % NWindows;
638 }
639 else if(Cleanwin - Canrestore == 0)
640 {
641 Cwp = (Cwp + 1) % NWindows;
642 fault = new CleanWindow;
643 }
644 else
645 {
646 Cwp = (Cwp + 1) % NWindows;
647 Rd = Rs1 + Rs2_or_imm13;
648 Cansave = Cansave - 1;
649 Canrestore = Canrestore + 1;
650 }
651 //This is here to make sure the CWP is written
652 //no matter what. This ensures that the results
653 //are written in the new window as well.
654 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
655 }});
656 0x3D: restore({{
657 //CWP should be set directly so that it always happens
658 //Also, this will allow writing to the new window and
659 //reading from the old one
660 Cwp = (Cwp - 1 + NWindows) % NWindows;
661 if(Canrestore == 0)
662 {
663 if(Otherwin)
664 fault = new FillNOther(Wstate<5:3>);
665 else
666 fault = new FillNNormal(Wstate<2:0>);
667 }
668 else
669 {
670 Rd = Rs1 + Rs2_or_imm13;
671 Cansave = Cansave + 1;
672 Canrestore = Canrestore - 1;
673 }
674 //This is here to make sure the CWP is written
675 //no matter what. This ensures that the results
676 //are written in the new window as well.
677 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
678 }});
679 0x3E: decode FCN {
680 0x0: Priv::done({{
681 if(Tl == 0)
682 return new IllegalInstruction;
683
684 Cwp = Tstate<4:0>;
685 Pstate = Tstate<20:8>;
686 Asi = Tstate<31:24>;
687 Ccr = Tstate<39:32>;
688 Gl = Tstate<42:40>;
689 NPC = Tnpc;
690 NNPC = Tnpc + 4;
691 Tl = Tl - 1;
692 }});
693 0x1: Priv::retry({{
694 if(Tl == 0)
695 return new IllegalInstruction;
696 Cwp = Tstate<4:0>;
697 Pstate = Tstate<20:8>;
698 Asi = Tstate<31:24>;
699 Ccr = Tstate<39:32>;
700 Gl = Tstate<42:40>;
701 NPC = Tpc;
702 NNPC = Tnpc + 4;
703 Tl = Tl - 1;
704 }});
705 }
706 }
707 }
708 0x3: decode OP3 {
709 format Load {
710 0x00: lduw({{Rd = Mem;}}, {{32}});
711 0x01: ldub({{Rd = Mem;}}, {{8}});
712 0x02: lduh({{Rd = Mem;}}, {{16}});
713 0x03: ldd({{
714 uint64_t val = Mem;
715 RdLow = val<31:0>;
716 RdHigh = val<63:32>;
717 }}, {{64}});
718 }
719 format Store {
720 0x04: stw({{Mem = Rd.sw;}}, {{32}});
721 0x05: stb({{Mem = Rd.sb;}}, {{8}});
722 0x06: sth({{Mem = Rd.shw;}}, {{16}});
723 0x07: std({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}});
724 }
725 format Load {
726 0x08: ldsw({{Rd = (int32_t)Mem;}}, {{32}});
727 0x09: ldsb({{Rd = (int8_t)Mem;}}, {{8}});
728 0x0A: ldsh({{Rd = (int16_t)Mem;}}, {{16}});
729 0x0B: ldx({{Rd = (int64_t)Mem;}}, {{64}});
730 0x0D: ldstub({{
731 Rd = Mem;
732 Mem = 0xFF;
733 }}, {{8}});
734 }
735 0x0E: Store::stx({{Mem = Rd}}, {{64}});
736 0x0F: LoadStore::swap({{
737 uint32_t temp = Rd;
738 Rd = Mem;
739 Mem = temp;
740 }}, {{32}});
741 format Load {
742 0x10: lduwa({{Rd = Mem;}}, {{32}});
743 0x11: lduba({{Rd = Mem;}}, {{8}});
744 0x12: lduha({{Rd = Mem;}}, {{16}});
745 0x13: ldda({{
746 uint64_t val = Mem;
747 RdLow = val<31:0>;
748 RdHigh = val<63:32>;
749 }}, {{64}});
750 }
751 format Store {
752 0x14: stwa({{Mem = Rd;}}, {{32}});
753 0x15: stba({{Mem = Rd;}}, {{8}});
754 0x16: stha({{Mem = Rd;}}, {{16}});
755 0x17: stda({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}});
756 }
757 format Load {
758 0x18: ldswa({{Rd = (int32_t)Mem;}}, {{32}});
759 0x19: ldsba({{Rd = (int8_t)Mem;}}, {{8}});
760 0x1A: ldsha({{Rd = (int16_t)Mem;}}, {{16}});
761 0x1B: ldxa({{Rd = (int64_t)Mem;}}, {{64}});
762 }
763 0x1D: LoadStore::ldstuba({{
764 Rd = Mem;
765 Mem = 0xFF;
766 }}, {{8}});
767 0x1E: Store::stxa({{Mem = Rd}}, {{64}});
768 0x1F: LoadStore::swapa({{
769 uint32_t temp = Rd;
770 Rd = Mem;
771 Mem = temp;
772 }}, {{32}});
773 format Trap {
774 0x20: ldf({{fault = new FpDisabled;}});
775 0x21: decode X {
776 0x0: Load::ldfsr({{Fsr = Mem<31:0> | Fsr<63:32>;}}, {{32}});
777 0x1: Load::ldxfsr({{Fsr = Mem;}}, {{64}});
778 }
779 0x22: ldqf({{fault = new FpDisabled;}});
780 0x23: lddf({{fault = new FpDisabled;}});
781 0x24: stf({{fault = new FpDisabled;}});
782 0x25: decode X {
783 0x0: Store::stfsr({{Mem = Fsr<31:0>;}}, {{32}});
784 0x1: Store::stxfsr({{Mem = Fsr;}}, {{64}});
785 }
786 0x26: stqf({{fault = new FpDisabled;}});
787 0x27: stdf({{fault = new FpDisabled;}});
788 0x2D: Nop::prefetch({{ }});
|
648 0x30: ldfa({{return new FpDisabled;}});
| 789 0x30: ldfa({{fault = new FpDisabled;}});
|
649 0x32: ldqfa({{fault = new FpDisabled;}});
650 0x33: lddfa({{fault = new FpDisabled;}});
651 0x34: stfa({{fault = new FpDisabled;}});
| 790 0x32: ldqfa({{fault = new FpDisabled;}});
791 0x33: lddfa({{fault = new FpDisabled;}});
792 0x34: stfa({{fault = new FpDisabled;}});
|
652 0x35: stqfa({{fault = new FpDisabled;}});
653 0x36: stdfa({{fault = new FpDisabled;}});
| 793 0x36: stqfa({{fault = new FpDisabled;}});
794 //XXX need to work in the ASI thing
795 0x37: Store::stdfa({{Mem = ((uint64_t)Frd);}}, {{64}});
|
654 0x3C: Cas::casa({{
655 uint64_t val = Mem.uw;
656 if(Rs2.uw == val)
657 Mem.uw = Rd.uw;
658 Rd.uw = val;
659 }});
660 0x3D: Nop::prefetcha({{ }});
661 0x3E: Cas::casxa({{
662 uint64_t val = Mem.udw;
663 if(Rs2 == val)
664 Mem.udw = Rd;
665 Rd = val;
666 }});
667 }
668 }
669}
| 796 0x3C: Cas::casa({{
797 uint64_t val = Mem.uw;
798 if(Rs2.uw == val)
799 Mem.uw = Rd.uw;
800 Rd.uw = val;
801 }});
802 0x3D: Nop::prefetcha({{ }});
803 0x3E: Cas::casxa({{
804 uint64_t val = Mem.udw;
805 if(Rs2 == val)
806 Mem.udw = Rd;
807 Rd = val;
808 }});
809 }
810 }
811}
|