decoder.isa (3952:092d03b2ab95) | decoder.isa (3970:d54945bab95d) |
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1// Copyright (c) 2006 The Regents of The University of Michigan | 1// Copyright (c) 2006-2007 The Regents of The University of Michigan |
2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the --- 1024 unchanged lines hidden (view full) --- 1034 0x0F: LoadStore::swap( 1035 {{uReg0 = Rd.uw; 1036 Rd.uw = Mem.uw;}}, 1037 {{Mem.uw = uReg0;}}); 1038 format LoadAlt { 1039 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}}); 1040 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}}); 1041 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}}); | 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright 9// notice, this list of conditions and the following disclaimer in the --- 1024 unchanged lines hidden (view full) --- 1034 0x0F: LoadStore::swap( 1035 {{uReg0 = Rd.uw; 1036 Rd.uw = Mem.uw;}}, 1037 {{Mem.uw = uReg0;}}); 1038 format LoadAlt { 1039 0x10: lduwa({{Rd = Mem.uw;}}, {{EXT_ASI}}); 1040 0x11: lduba({{Rd = Mem.ub;}}, {{EXT_ASI}}); 1041 0x12: lduha({{Rd = Mem.uhw;}}, {{EXT_ASI}}); |
1042 0x13: ldtwa({{ 1043 uint64_t val = Mem.udw; 1044 RdLow = val<31:0>; 1045 RdHigh = val<63:32>; 1046 }}, {{EXT_ASI}}); | 1042 0x13: decode EXT_ASI { 1043 //ASI_QUAD_LDD 1044 0x24: TwinLoad::ldtx_quad_ldd( 1045 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); 1046 //ASI_LDTX_REAL 1047 0x26: TwinLoad::ldtx_real( 1048 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); 1049 //ASI_LDTX_N 1050 0x27: TwinLoad::ldtx_n( 1051 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); 1052 //ASI_LDTX_L 1053 0x2C: TwinLoad::ldtx_l( 1054 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); 1055 //ASI_LDTX_REAL_L 1056 0x2E: TwinLoad::ldtx_real_l( 1057 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); 1058 //ASI_LDTX_N_L 1059 0x2F: TwinLoad::ldtx_n_l( 1060 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); 1061 default: ldtwa({{ 1062 uint64_t val = Mem.udw; 1063 RdLow = val<31:0>; 1064 RdHigh = val<63:32>; 1065 }}, {{EXT_ASI}}); 1066 } |
1047 } 1048 format StoreAlt { 1049 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}}); 1050 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}}); 1051 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}}); 1052 0x17: sttwa({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}}); 1053 } 1054 format LoadAlt { --- 45 unchanged lines hidden (view full) --- 1100 //ASI_REAL 1101 0x14: FailUnimpl::lddfa_real(); 1102 //ASI_REAL_LITTLE 1103 0x1C: FailUnimpl::lddfa_real_l(); 1104 //ASI_REAL_IO 1105 0x15: FailUnimpl::lddfa_real_io(); 1106 //ASI_REAL_IO_LITTLE 1107 0x1D: FailUnimpl::lddfa_real_io_l(); | 1067 } 1068 format StoreAlt { 1069 0x14: stwa({{Mem.uw = Rd;}}, {{EXT_ASI}}); 1070 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}}); 1071 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}}); 1072 0x17: sttwa({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{EXT_ASI}}); 1073 } 1074 format LoadAlt { --- 45 unchanged lines hidden (view full) --- 1120 //ASI_REAL 1121 0x14: FailUnimpl::lddfa_real(); 1122 //ASI_REAL_LITTLE 1123 0x1C: FailUnimpl::lddfa_real_l(); 1124 //ASI_REAL_IO 1125 0x15: FailUnimpl::lddfa_real_io(); 1126 //ASI_REAL_IO_LITTLE 1127 0x1D: FailUnimpl::lddfa_real_io_l(); |
1108 //ASI_LDTX_REAL 1109 0x26: TwinLoad::ldtx_real( 1110 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); 1111 //ASI_LDTX_N 1112 0x27: TwinLoad::ldtx_n( 1113 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); 1114 //ASI_LDTX_REAL_L 1115 0x2E: TwinLoad::ldtx_real_l( 1116 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); 1117 //ASI_LDTX_N_L 1118 0x2F: TwinLoad::ldtx_n_l( 1119 {{RdTwin.udw = Mem.udw}}, {{EXT_ASI}}); | |
1120 //ASI_PRIMARY 1121 0x80: FailUnimpl::lddfa_p(); 1122 //ASI_PRIMARY_LITTLE 1123 0x88: FailUnimpl::lddfa_pl(); 1124 //ASI_SECONDARY 1125 0x81: FailUnimpl::lddfa_s(); 1126 //ASI_SECONDARY_LITTLE 1127 0x89: FailUnimpl::lddfa_sl(); --- 152 unchanged lines hidden --- | 1128 //ASI_PRIMARY 1129 0x80: FailUnimpl::lddfa_p(); 1130 //ASI_PRIMARY_LITTLE 1131 0x88: FailUnimpl::lddfa_pl(); 1132 //ASI_SECONDARY 1133 0x81: FailUnimpl::lddfa_s(); 1134 //ASI_SECONDARY_LITTLE 1135 0x89: FailUnimpl::lddfa_sl(); --- 152 unchanged lines hidden --- |