1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 427 unchanged lines hidden (view full) ---

436 0x33: HPriv::wrhpr({{
437 // XXX Need to protect with format that traps non-priv/priv
438 // access
439 fault = xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
440 }});
441 0x34: decode OPF{
442 format BasicOperate{
443 0x01: fmovs({{
444 Frd.sf = Frs2.sf;
445 //fsr.ftt = fsr.cexc = 0
446 Fsr &= ~(7 << 14);
447 Fsr &= ~(0x1F);
448 }});
449 0x02: fmovd({{
450 Frd.df = Frs2.df;
451 //fsr.ftt = fsr.cexc = 0
452 Fsr &= ~(7 << 14);
453 Fsr &= ~(0x1F);
454 }});
455 0x03: Trap::fmovq({{fault = new FpDisabled;}});
456 0x05: fnegs({{
457 //XXX might want to explicitly flip the sign bit
458 //So cases with Nan and +/-0 don't do weird things
459 Frd.sf = -Frs2.sf;
460 //fsr.ftt = fsr.cexc = 0
461 Fsr &= ~(7 << 14);
462 Fsr &= ~(0x1F);
463 }});
464 0x06: fnegd({{
465 //XXX might want to explicitly flip the sign bit
466 //So cases with Nan and +/-0 don't do weird things
467 Frd.df = -Frs2.df;
468 //fsr.ftt = fsr.cexc = 0
469 Fsr &= ~(7 << 14);
470 Fsr &= ~(0x1F);
471 }});
472 0x07: Trap::fnegq({{fault = new FpDisabled;}});
473 0x09: fabss({{
474 //XXX this instruction should be tested individually
475 //Clear the sign bit
476 Frd.sf = (float)(~(1 << 31) & ((uint32_t)Frs2.sf));
477 //fsr.ftt = fsr.cexc = 0
478 Fsr &= ~(7 << 14);
479 Fsr &= ~(0x1F);
480 }});
481 0x0A: fabsd({{
482 //XXX this instruction should be tested individually
483 //Clear the sign bit
484 Frd.df = (float)(~((uint64_t)1 << 63) & ((uint64_t)Frs2.df));
485 //fsr.ftt = fsr.cexc = 0
486 Fsr &= ~(7 << 14);
487 Fsr &= ~(0x1F);
488 }});
489 0x0B: Trap::fabsq({{fault = new FpDisabled;}});
490 0x29: fsqrts({{Frd.sf = sqrt(Frs2.sf);}});
491 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}});
492 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});

--- 93 unchanged lines hidden (view full) ---

586 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}});
587 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}});
588 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}});
589 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
590 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
591 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
592 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
593 0x48: BasicOperate::faligndata({{
594 uint64_t msbX = (uint64_t)Frs1;
595 uint64_t lsbX = (uint64_t)Frs2;
596 uint64_t msbShift = Gsr<2:0> * 8;
597 uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
598 uint64_t msbMask = ((uint64_t)(-1)) << msbShift;
599 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
600 Frd = ((msbX << msbShift) & msbMask) |
601 ((lsbX << lsbShift) & lsbMask);
602 }});
603 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
604 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}});
605 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}});
606 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}});
607 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}});
608 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}});
609 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}});

--- 24 unchanged lines hidden (view full) ---

634 0x6C: Trap::fxor({{fault = new IllegalInstruction;}});
635 0x6D: Trap::fxors({{fault = new IllegalInstruction;}});
636 0x6E: Trap::fnand({{fault = new IllegalInstruction;}});
637 0x6F: Trap::fnands({{fault = new IllegalInstruction;}});
638 0x70: Trap::fand({{fault = new IllegalInstruction;}});
639 0x71: Trap::fands({{fault = new IllegalInstruction;}});
640 0x72: Trap::fxnor({{fault = new IllegalInstruction;}});
641 0x73: Trap::fxnors({{fault = new IllegalInstruction;}});
642 0x74: BasicOperate::fsrc1({{Frd.df = Frs1.df;}});
643 0x75: BasicOperate::fsrc1s({{Frd.sf = Frs1.sf;}});
644 0x76: Trap::fornot2({{fault = new IllegalInstruction;}});
645 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}});
646 0x78: BasicOperate::fsrc2({{Frd.df = Frs2.df;}});
647 0x79: BasicOperate::fsrc2s({{Frd.sf = Frs2.sf;}});
648 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}});
649 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}});
650 0x7C: Trap::for({{fault = new IllegalInstruction;}});
651 0x7D: Trap::fors({{fault = new IllegalInstruction;}});
652 0x7E: Trap::fone({{fault = new IllegalInstruction;}});
653 0x7F: Trap::fones({{fault = new IllegalInstruction;}});
654 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
655 0x81: Trap::siam({{fault = new IllegalInstruction;}});

--- 164 unchanged lines hidden (view full) ---

820 RdLow = val<31:0>;
821 RdHigh = val<63:32>;
822 }}, {{64}});
823 }
824 format Store {
825 0x04: stw({{Mem = Rd.sw;}}, {{32}});
826 0x05: stb({{Mem = Rd.sb;}}, {{8}});
827 0x06: sth({{Mem = Rd.shw;}}, {{16}});
828 0x07: std({{Mem = RdLow<31:0> | RdHigh<31:0> << 32;}}, {{64}});
829 }
830 format Load {
831 0x08: ldsw({{Rd = (int32_t)Mem;}}, {{32}});
832 0x09: ldsb({{Rd = (int8_t)Mem;}}, {{8}});
833 0x0A: ldsh({{Rd = (int16_t)Mem;}}, {{16}});
834 0x0B: ldx({{Rd = (int64_t)Mem;}}, {{64}});
835 0x0D: ldstub({{
836 Rd = Mem;

--- 34 unchanged lines hidden (view full) ---

871 }}, {{8}});
872 0x1E: Store::stxa({{Mem = Rd}}, {{64}});
873 0x1F: LoadStore::swapa({{
874 uint32_t temp = Rd;
875 Rd = Mem;
876 Mem = temp;
877 }}, {{32}});
878 format Trap {
879 0x20: Load::ldf({{Frd.sf = ((float)Mem);}}, {{32}});
880 0x21: decode X {
881 0x0: Load::ldfsr({{Fsr = Mem<31:0> | Fsr<63:32>;}}, {{32}});
882 0x1: Load::ldxfsr({{Fsr = Mem;}}, {{64}});
883 }
884 0x22: ldqf({{fault = new FpDisabled;}});
885 0x23: Load::lddf({{Frd.df = ((double)Mem);}}, {{64}});
886 0x24: Store::stf({{Mem = ((int32_t)Frd.sf);}}, {{32}});
887 0x25: decode X {
888 0x0: Store::stfsr({{Mem = Fsr<31:0>;}}, {{32}});
889 0x1: Store::stxfsr({{Mem = Fsr;}}, {{64}});
890 }
891 0x26: stqf({{fault = new FpDisabled;}});
892 0x27: Store::stdf({{Mem = ((int64_t)Frd.df);}}, {{64}});
893 0x2D: Nop::prefetch({{ }});
894 0x30: Load::ldfa({{Frd.sf = ((float)Mem);}}, {{32}});
895 0x32: ldqfa({{fault = new FpDisabled;}});
896 0x33: Load::lddfa({{Frd.df = ((double)Mem);}}, {{64}});
897 0x34: Store::stfa({{Mem = ((int32_t)Frd.sf);}}, {{32}});
898 0x36: stqfa({{fault = new FpDisabled;}});
899 //XXX need to work in the ASI thing
900 0x37: Store::stdfa({{Mem = ((uint64_t)Frd.df);}}, {{64}});
901 0x3C: Cas::casa({{
902 uint64_t val = Mem.uw;
903 if(Rs2.uw == val)
904 Mem.uw = Rd.uw;
905 Rd.uw = val;
906 }});
907 0x3D: Nop::prefetcha({{ }});
908 0x3E: Cas::casxa({{
909 uint64_t val = Mem.udw;
910 if(Rs2 == val)
911 Mem.udw = Rd;
912 Rd = val;
913 }});
914 }
915 }
916}