1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

--- 23 unchanged lines hidden (view full) ---

32//
33// The actual decoder specification
34//
35
36decode OP default Unknown::unknown()
37{
38 0x0: decode OP2
39 {
40 // Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 // bpcc
45 0x1: decode COND2
46 {
47 // Branch Always
48 0x8: bpa(19, annul_code={{
49 SparcISA::PCState pc = PCS;
50 pc.npc(pc.pc() + disp);
51 pc.nnpc(pc.npc() + 4);
52 PCS = pc;
53 }});
54 // Branch Never
55 0x0: bpn(19, {{;}},
56 annul_code={{
57 SparcISA::PCState pc = PCS;
58 pc.nnpc(pc.npc() + 8);
59 pc.npc(pc.npc() + 4);
60 PCS = pc;
61 }});
62 default: decode BPCC
63 {
64 0x0: bpcci(19, test={{passesCondition(Ccr<3:0>, COND2)}});
65 0x2: bpccx(19, test={{passesCondition(Ccr<7:4>, COND2)}});
66 }
67 }
68 // bicc
69 0x2: decode COND2
70 {
71 // Branch Always
72 0x8: ba(22, annul_code={{
73 SparcISA::PCState pc = PCS;
74 pc.npc(pc.pc() + disp);
75 pc.nnpc(pc.npc() + 4);
76 PCS = pc;
77 }});
78 // Branch Never
79 0x0: bn(22, {{;}},
80 annul_code={{
81 SparcISA::PCState pc = PCS;
82 pc.nnpc(pc.npc() + 8);
83 pc.npc(pc.npc() + 4);
84 PCS = pc;
85 }});
86 default: bicc(22, test={{passesCondition(Ccr<3:0>, COND2)}});

--- 6 unchanged lines hidden (view full) ---

93 0x1: bpreq(test={{Rs1.sdw == 0}});
94 0x2: bprle(test={{Rs1.sdw <= 0}});
95 0x3: bprl(test={{Rs1.sdw < 0}});
96 0x5: bprne(test={{Rs1.sdw != 0}});
97 0x6: bprg(test={{Rs1.sdw > 0}});
98 0x7: bprge(test={{Rs1.sdw >= 0}});
99 }
100 }
101 // SETHI (or NOP if rd == 0 and imm == 0)
102 0x4: SetHi::sethi({{Rd.udw = imm;}});
103 // fbpfcc
104 0x5: decode COND2 {
105 format BranchN {
106 // Branch Always
107 0x8: fbpa(22, annul_code={{
108 SparcISA::PCState pc = PCS;
109 pc.npc(pc.pc() + disp);
110 pc.nnpc(pc.npc() + 4);
111 PCS = pc;
112 }});
113 // Branch Never
114 0x0: fbpn(22, {{;}},
115 annul_code={{
116 SparcISA::PCState pc = PCS;
117 pc.nnpc(pc.npc() + 8);
118 pc.npc(pc.npc() + 4);
119 PCS = pc;
120 }});
121 default: decode BPCC {
122 0x0: fbpfcc0(19, test=
123 {{passesFpCondition(Fsr<11:10>, COND2)}});
124 0x1: fbpfcc1(19, test=
125 {{passesFpCondition(Fsr<33:32>, COND2)}});
126 0x2: fbpfcc2(19, test=
127 {{passesFpCondition(Fsr<35:34>, COND2)}});
128 0x3: fbpfcc3(19, test=
129 {{passesFpCondition(Fsr<37:36>, COND2)}});
130 }
131 }
132 }
133 // fbfcc
134 0x6: decode COND2 {
135 format BranchN {
136 // Branch Always
137 0x8: fba(22, annul_code={{
138 SparcISA::PCState pc = PCS;
139 pc.npc(pc.pc() + disp);
140 pc.nnpc(pc.npc() + 4);
141 PCS = pc;
142 }});
143 // Branch Never
144 0x0: fbn(22, {{;}},
145 annul_code={{
146 SparcISA::PCState pc = PCS;
147 pc.nnpc(pc.npc() + 8);
148 pc.npc(pc.npc() + 4);
149 PCS = pc;
150 }});
151 default: fbfcc(22, test=

--- 27 unchanged lines hidden (view full) ---

179 Y = Rd<63:32>;
180 }});
181 0x0B: smul({{
182 Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
183 Y = Rd.sdw<63:32>;
184 }});
185 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
186 0x0D: udivx({{
187 if (Rs2_or_imm13 == 0)
188 fault = new DivisionByZero;
189 else
190 Rd.udw = Rs1.udw / Rs2_or_imm13;
191 }});
192 0x0E: udiv({{
193 if (Rs2_or_imm13 == 0) {
194 fault = new DivisionByZero;
195 } else {
196 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
197 if (Rd.udw >> 32 != 0)
198 Rd.udw = 0xFFFFFFFF;
199 }
200 }});
201 0x0F: sdiv({{
202 if (Rs2_or_imm13.sdw == 0) {
203 fault = new DivisionByZero;
204 } else {
205 Rd.udw = ((int64_t)((Y << 32) |
206 Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
207 if ((int64_t)Rd.udw >=
208 std::numeric_limits<int32_t>::max()) {
209 Rd.udw = 0x7FFFFFFF;
210 } else if ((int64_t)Rd.udw <=
211 std::numeric_limits<int32_t>::min()) {
212 Rd.udw = ULL(0xFFFFFFFF80000000);
213 }
214 }
215 }});
216 }
217 format IntOpCc {
218 0x10: addcc({{
219 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13;
220 Rd = res = op1 + op2;
221 }});

--- 19 unchanged lines hidden (view full) ---

241 int64_t resTemp;
242 Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
243 Y = resTemp<63:32>;}});
244 0x1C: subccc({{
245 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13;
246 Rd = res = op1 - op2 - Ccr<0:>;
247 }}, sub=True);
248 0x1D: IntOpCcRes::udivxcc({{
249 if (Rs2_or_imm13.udw == 0)
250 fault = new DivisionByZero;
251 else
252 Rd = Rs1.udw / Rs2_or_imm13.udw;}});
253 0x1E: IntOpCcRes::udivcc({{
254 uint64_t resTemp;
255 uint32_t val2 = Rs2_or_imm13.udw;
256 int32_t overflow = 0;
257 if (val2 == 0) {
258 fault = new DivisionByZero;
259 } else {
260 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
261 overflow = (resTemp<63:32> != 0);
262 if (overflow)
263 Rd = resTemp = 0xFFFFFFFF;
264 else
265 Rd = resTemp;
266 }
267 }}, iv={{overflow}});
268 0x1F: IntOpCcRes::sdivcc({{
269 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
270 bool overflow = false, underflow = false;
271 if (val2 == 0) {
272 fault = new DivisionByZero;
273 } else {
274 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
275 overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max());
276 underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min());
277 if (overflow)
278 Rd = 0x7FFFFFFF;
279 else if (underflow)
280 Rd = ULL(0xFFFFFFFF80000000);
281 }
282 }}, iv={{overflow || underflow}});
283 0x20: taddcc({{
284 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13;
285 Rd = res = Rs1 + op2;
286 }}, iv={{
287 (op1 & mask(2)) || (op2 & mask(2)) ||
288 findOverflow(32, res, op1, op2)

--- 5 unchanged lines hidden (view full) ---

294 (op1 & mask(2)) || (op2 & mask(2)) ||
295 findOverflow(32, res, op1, ~op2)
296 }}, sub=True);
297 0x22: taddcctv({{
298 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13;
299 Rd = res = op1 + op2;
300 bool overflow = (op1 & mask(2)) || (op2 & mask(2)) ||
301 findOverflow(32, res, op1, op2);
302 if (overflow)
303 fault = new TagOverflow;
304 }}, iv={{overflow}});
305 0x23: tsubcctv({{
306 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13;
307 Rd = res = op1 - op2;
308 bool overflow = (op1 & mask(2)) || (op2 & mask(2)) ||
309 findOverflow(32, res, op1, ~op2);
310 if (overflow)
311 fault = new TagOverflow;
312 }}, iv={{overflow}}, sub=True);
313 0x24: mulscc({{
314 int32_t savedLSB = Rs1<0:>;
315
316 // Step 1
317 int64_t multiplicand = Rs2_or_imm13;
318 // Step 2
319 int32_t partialP = Rs1<31:1> |
320 ((Ccr<3:3> ^ Ccr<1:1>) << 31);
321 // Step 3
322 int32_t added = Y<0:> ? multiplicand : 0;
323 int64_t res, op1 = partialP, op2 = added;
324 Rd = res = partialP + added;
325 // Steps 4 & 5
326 Y = Y<31:1> | (savedLSB << 31);
327 }});
328 }
329 format IntOp
330 {
331 0x25: decode X {
332 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
333 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
334 }
335 0x26: decode X {
336 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
337 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
338 }
339 0x27: decode X {
340 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
341 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
342 }
343 0x28: decode RS1 {
344 0x00: NoPriv::rdy({{Rd = Y<31:0>;}});
345 // 1 should cause an illegal instruction exception
346 0x02: NoPriv::rdccr({{Rd = Ccr;}});
347 0x03: NoPriv::rdasi({{Rd = Asi;}});
348 0x04: Priv::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
349 0x05: NoPriv::rdpc({{
350 SparcISA::PCState pc = PCS;
351 if (Pstate<3:>)
352 Rd = (pc.pc())<31:0>;
353 else
354 Rd = pc.pc();
355 }});
356 0x06: NoPriv::rdfprs({{
357 // Wait for all fpops to finish.
358 Rd = Fprs;
359 }});
360 // 7-14 should cause an illegal instruction exception
361 0x0F: decode I {
362 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp);
363 0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp);
364 }
365 0x10: Priv::rdpcr({{Rd = Pcr;}});
366 0x11: Priv::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
367 // 0x12 should cause an illegal instruction exception
368 0x13: NoPriv::rdgsr({{
369 fault = checkFpEnableFault(xc);
370 if (fault)
371 return fault;
372 Rd = Gsr;
373 }});
374 // 0x14-0x15 should cause an illegal instruction exception
375 0x16: Priv::rdsoftint({{Rd = Softint;}});
376 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
377 0x18: Priv::rdstick({{Rd = Stick}}, {{Stick<63:>}});
378 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
379 0x1A: Priv::rdstrand_sts_reg({{
380 if (Pstate<2:> && !Hpstate<2:>)
381 Rd = StrandStsReg<0:>;
382 else
383 Rd = StrandStsReg;
384 }});
385 // 0x1A is supposed to be reserved, but it reads the strand
386 // status register.
387 // 0x1B-0x1F should cause an illegal instruction exception
388 }
389 0x29: decode RS1 {
390 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
391 0x01: HPriv::rdhprhtstate({{Rd = Htstate;}}, checkTl=true);
392 // 0x02 should cause an illegal instruction exception
393 0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
394 // 0x04 should cause an illegal instruction exception
395 0x05: HPriv::rdhprhtba({{Rd = Htba;}});
396 0x06: HPriv::rdhprhver({{Rd = Hver;}});
397 // 0x07-0x1E should cause an illegal instruction exception
398 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
399 }
400 0x2A: decode RS1 {
401 0x00: Priv::rdprtpc({{Rd = Tpc;}}, checkTl=true);
402 0x01: Priv::rdprtnpc({{Rd = Tnpc;}}, checkTl=true);
403 0x02: Priv::rdprtstate({{Rd = Tstate;}}, checkTl=true);
404 0x03: Priv::rdprtt({{Rd = Tt;}}, checkTl=true);
405 0x04: Priv::rdprtick({{Rd = Tick;}});
406 0x05: Priv::rdprtba({{Rd = Tba;}});
407 0x06: Priv::rdprpstate({{Rd = Pstate;}});
408 0x07: Priv::rdprtl({{Rd = Tl;}});
409 0x08: Priv::rdprpil({{Rd = Pil;}});
410 0x09: Priv::rdprcwp({{Rd = Cwp;}});
411 0x0A: Priv::rdprcansave({{Rd = Cansave;}});
412 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});
413 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});
414 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}});
415 0x0E: Priv::rdprwstate({{Rd = Wstate;}});
416 // 0x0F should cause an illegal instruction exception
417 0x10: Priv::rdprgl({{Rd = Gl;}});
418 // 0x11-0x1F should cause an illegal instruction exception
419 }
420 0x2B: BasicOperate::flushw({{
421 if (NWindows - 2 - Cansave != 0) {
422 if (Otherwin)
423 fault = new SpillNOther(4*Wstate<5:3>);
424 else
425 fault = new SpillNNormal(4*Wstate<2:0>);
426 }
427 }});
428 0x2C: decode MOVCC3
429 {
430 0x0: decode CC
431 {
432 0x0: movccfcc0({{
433 if (passesCondition(Fsr<11:10>, COND4))
434 Rd = Rs2_or_imm11;
435 else
436 Rd = Rd;
437 }});
438 0x1: movccfcc1({{
439 if (passesCondition(Fsr<33:32>, COND4))
440 Rd = Rs2_or_imm11;
441 else
442 Rd = Rd;
443 }});
444 0x2: movccfcc2({{
445 if (passesCondition(Fsr<35:34>, COND4))
446 Rd = Rs2_or_imm11;
447 else
448 Rd = Rd;
449 }});
450 0x3: movccfcc3({{
451 if (passesCondition(Fsr<37:36>, COND4))
452 Rd = Rs2_or_imm11;
453 else
454 Rd = Rd;
455 }});
456 }
457 0x1: decode CC
458 {
459 0x0: movcci({{
460 if (passesCondition(Ccr<3:0>, COND4))
461 Rd = Rs2_or_imm11;
462 else
463 Rd = Rd;
464 }});
465 0x2: movccx({{
466 if (passesCondition(Ccr<7:4>, COND4))
467 Rd = Rs2_or_imm11;
468 else
469 Rd = Rd;
470 }});
471 }
472 }
473 0x2D: sdivx({{
474 if (Rs2_or_imm13.sdw == 0)
475 fault = new DivisionByZero;
476 else
477 Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
478 }});
479 0x2E: Trap::popc({{fault = new IllegalInstruction;}});
480 0x2F: decode RCOND3
481 {
482 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
483 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
484 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
485 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
486 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
487 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
488 }
489 0x30: decode RD {
490 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}});
491 // 0x01 should cause an illegal instruction exception
492 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
493 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
494 // 0x04-0x05 should cause an illegal instruction exception
495 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
496 // 0x07-0x0E should cause an illegal instruction exception
497 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
498 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
499 0x11: Priv::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
500 // 0x12 should cause an illegal instruction exception
501 0x13: NoPriv::wrgsr({{
502 if (Fprs<2:> == 0 || Pstate<4:> == 0)
503 return new FpDisabled;
504 Gsr = Rs1 ^ Rs2_or_imm13;
505 }});
506 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
507 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});
508 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
509 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}});
510 0x18: NoPriv::wrstick({{
511 if (!Hpstate<2:>)
512 return new IllegalInstruction;
513 Stick = Rs1 ^ Rs2_or_imm13;
514 }});
515 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}});
516 0x1A: Priv::wrstrand_sts_reg({{
517 StrandStsReg = Rs1 ^ Rs2_or_imm13;
518 }});
519 // 0x1A is supposed to be reserved, but it writes the strand
520 // status register.
521 // 0x1B-0x1F should cause an illegal instruction exception
522 }
523 0x31: decode FCN {
524 0x0: Priv::saved({{
525 assert(Cansave < NWindows - 2);
526 assert(Otherwin || Canrestore);
527 Cansave = Cansave + 1;
528 if (Otherwin == 0)
529 Canrestore = Canrestore - 1;
530 else
531 Otherwin = Otherwin - 1;
532 }});
533 0x1: Priv::restored({{
534 assert(Cansave || Otherwin);
535 assert(Canrestore < NWindows - 2);
536 Canrestore = Canrestore + 1;
537 if (Otherwin == 0)
538 Cansave = Cansave - 1;
539 else
540 Otherwin = Otherwin - 1;
541
542 if (Cleanwin < NWindows - 1)
543 Cleanwin = Cleanwin + 1;
544 }});
545 }
546 0x32: decode RD {
547 0x00: Priv::wrprtpc(
548 {{Tpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
549 0x01: Priv::wrprtnpc(
550 {{Tnpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
551 0x02: Priv::wrprtstate(
552 {{Tstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
553 0x03: Priv::wrprtt(
554 {{Tt = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
555 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
556 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
557 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
558 0x07: Priv::wrprtl({{
559 if (Pstate<2:> && !Hpstate<2:>)
560 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
561 else
562 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);
563 }});
564 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
565 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
566 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
567 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
568 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
569 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
570 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
571 // 0x0F should cause an illegal instruction exception
572 0x10: Priv::wrprgl({{
573 if (Pstate<2:> && !Hpstate<2:>)
574 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL);
575 else
576 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
577 }});
578 // 0x11-0x1F should cause an illegal instruction exception
579 }
580 0x33: decode RD {
581 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
582 0x01: HPriv::wrhprhtstate(
583 {{Htstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
584 // 0x02 should cause an illegal instruction exception
585 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
586 // 0x04 should cause an illegal instruction exception
587 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
588 // 0x06-0x01D should cause an illegal instruction exception
589 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
590 }
591 0x34: decode OPF{
592 format FpBasic{
593 0x01: fmovs({{Frds.uw = Frs2s.uw;}});
594 0x02: fmovd({{Frd.udw = Frs2.udw;}});
595 0x03: FpUnimpl::fmovq();
596 0x05: fnegs({{Frds.uw = Frs2s.uw ^ (1UL << 31);}});

--- 48 unchanged lines hidden (view full) ---

645 }});
646 0xD3: FpUnimpl::fqtoi();
647 default: FailUnimpl::fpop1();
648 }
649 }
650 0x35: decode OPF{
651 format FpBasic{
652 0x01: fmovs_fcc0({{
653 if (passesFpCondition(Fsr<11:10>, COND4))
654 Frds = Frs2s;
655 else
656 Frds = Frds;
657 }});
658 0x02: fmovd_fcc0({{
659 if (passesFpCondition(Fsr<11:10>, COND4))
660 Frd = Frs2;
661 else
662 Frd = Frd;
663 }});
664 0x03: FpUnimpl::fmovq_fcc0();
665 0x25: fmovrsz({{
666 if (Rs1 == 0)
667 Frds = Frs2s;
668 else
669 Frds = Frds;
670 }});
671 0x26: fmovrdz({{
672 if (Rs1 == 0)
673 Frd = Frs2;
674 else
675 Frd = Frd;
676 }});
677 0x27: FpUnimpl::fmovrqz();
678 0x41: fmovs_fcc1({{
679 if (passesFpCondition(Fsr<33:32>, COND4))
680 Frds = Frs2s;
681 else
682 Frds = Frds;
683 }});
684 0x42: fmovd_fcc1({{
685 if (passesFpCondition(Fsr<33:32>, COND4))
686 Frd = Frs2;
687 else
688 Frd = Frd;
689 }});
690 0x43: FpUnimpl::fmovq_fcc1();
691 0x45: fmovrslez({{
692 if (Rs1 <= 0)
693 Frds = Frs2s;
694 else
695 Frds = Frds;
696 }});
697 0x46: fmovrdlez({{
698 if (Rs1 <= 0)
699 Frd = Frs2;
700 else
701 Frd = Frd;
702 }});
703 0x47: FpUnimpl::fmovrqlez();
704 0x51: fcmps({{
705 uint8_t fcc;
706 if (isnan(Frs1s) || isnan(Frs2s))
707 fcc = 3;
708 else if (Frs1s < Frs2s)
709 fcc = 1;
710 else if (Frs1s > Frs2s)
711 fcc = 2;
712 else
713 fcc = 0;
714 uint8_t firstbit = 10;
715 if (FCMPCC)
716 firstbit = FCMPCC * 2 + 30;
717 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
718 }});
719 0x52: fcmpd({{
720 uint8_t fcc;
721 if (isnan(Frs1) || isnan(Frs2))
722 fcc = 3;
723 else if (Frs1 < Frs2)
724 fcc = 1;
725 else if (Frs1 > Frs2)
726 fcc = 2;
727 else
728 fcc = 0;
729 uint8_t firstbit = 10;
730 if (FCMPCC)
731 firstbit = FCMPCC * 2 + 30;
732 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
733 }});
734 0x53: FpUnimpl::fcmpq();
735 0x55: fcmpes({{
736 uint8_t fcc = 0;
737 if (isnan(Frs1s) || isnan(Frs2s))
738 fault = new FpExceptionIEEE754;
739 if (Frs1s < Frs2s)
740 fcc = 1;
741 else if (Frs1s > Frs2s)
742 fcc = 2;
743 uint8_t firstbit = 10;
744 if (FCMPCC)
745 firstbit = FCMPCC * 2 + 30;
746 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
747 }});
748 0x56: fcmped({{
749 uint8_t fcc = 0;
750 if (isnan(Frs1) || isnan(Frs2))
751 fault = new FpExceptionIEEE754;
752 if (Frs1 < Frs2)
753 fcc = 1;
754 else if (Frs1 > Frs2)
755 fcc = 2;
756 uint8_t firstbit = 10;
757 if (FCMPCC)
758 firstbit = FCMPCC * 2 + 30;
759 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
760 }});
761 0x57: FpUnimpl::fcmpeq();
762 0x65: fmovrslz({{
763 if (Rs1 < 0)
764 Frds = Frs2s;
765 else
766 Frds = Frds;
767 }});
768 0x66: fmovrdlz({{
769 if (Rs1 < 0)
770 Frd = Frs2;
771 else
772 Frd = Frd;
773 }});
774 0x67: FpUnimpl::fmovrqlz();
775 0x81: fmovs_fcc2({{
776 if (passesFpCondition(Fsr<35:34>, COND4))
777 Frds = Frs2s;
778 else
779 Frds = Frds;
780 }});
781 0x82: fmovd_fcc2({{
782 if (passesFpCondition(Fsr<35:34>, COND4))
783 Frd = Frs2;
784 else
785 Frd = Frd;
786 }});
787 0x83: FpUnimpl::fmovq_fcc2();
788 0xA5: fmovrsnz({{
789 if (Rs1 != 0)
790 Frds = Frs2s;
791 else
792 Frds = Frds;
793 }});
794 0xA6: fmovrdnz({{
795 if (Rs1 != 0)
796 Frd = Frs2;
797 else
798 Frd = Frd;
799 }});
800 0xA7: FpUnimpl::fmovrqnz();
801 0xC1: fmovs_fcc3({{
802 if (passesFpCondition(Fsr<37:36>, COND4))
803 Frds = Frs2s;
804 else
805 Frds = Frds;
806 }});
807 0xC2: fmovd_fcc3({{
808 if (passesFpCondition(Fsr<37:36>, COND4))
809 Frd = Frs2;
810 else
811 Frd = Frd;
812 }});
813 0xC3: FpUnimpl::fmovq_fcc3();
814 0xC5: fmovrsgz({{
815 if (Rs1 > 0)
816 Frds = Frs2s;
817 else
818 Frds = Frds;
819 }});
820 0xC6: fmovrdgz({{
821 if (Rs1 > 0)
822 Frd = Frs2;
823 else
824 Frd = Frd;
825 }});
826 0xC7: FpUnimpl::fmovrqgz();
827 0xE5: fmovrsgez({{
828 if (Rs1 >= 0)
829 Frds = Frs2s;
830 else
831 Frds = Frds;
832 }});
833 0xE6: fmovrdgez({{
834 if (Rs1 >= 0)
835 Frd = Frs2;
836 else
837 Frd = Frd;
838 }});
839 0xE7: FpUnimpl::fmovrqgez();
840 0x101: fmovs_icc({{
841 if (passesCondition(Ccr<3:0>, COND4))
842 Frds = Frs2s;
843 else
844 Frds = Frds;
845 }});
846 0x102: fmovd_icc({{
847 if (passesCondition(Ccr<3:0>, COND4))
848 Frd = Frs2;
849 else
850 Frd = Frd;
851 }});
852 0x103: FpUnimpl::fmovq_icc();
853 0x181: fmovs_xcc({{
854 if (passesCondition(Ccr<7:4>, COND4))
855 Frds = Frs2s;
856 else
857 Frds = Frds;
858 }});
859 0x182: fmovd_xcc({{
860 if (passesCondition(Ccr<7:4>, COND4))
861 Frd = Frs2;
862 else
863 Frd = Frd;
864 }});
865 0x183: FpUnimpl::fmovq_xcc();
866 default: FailUnimpl::fpop2();
867 }
868 }
869 // This used to be just impdep1, but now it's a whole bunch
870 // of instructions
871 0x36: decode OPF{
872 0x00: FailUnimpl::edge8();
873 0x01: FailUnimpl::edge8n();
874 0x02: FailUnimpl::edge8l();
875 0x03: FailUnimpl::edge8ln();
876 0x04: FailUnimpl::edge16();
877 0x05: FailUnimpl::edge16n();
878 0x06: FailUnimpl::edge16l();

--- 33 unchanged lines hidden (view full) ---

912 0x39: FailUnimpl::fmuld8ulx16();
913 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
914 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
915 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
916 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
917 0x48: BasicOperate::faligndata({{
918 uint64_t msbX = Frs1.udw;
919 uint64_t lsbX = Frs2.udw;
920 // Some special cases need to be split out, first
921 // because they're the most likely to be used, and
922 // second because otherwise, we end up shifting by
923 // greater than the width of the type being shifted,
924 // namely 64, which produces undefined results
925 // according to the C standard.
926 switch (Gsr<2:0>) {
927 case 0:
928 Frd.udw = msbX;
929 break;
930 case 8:
931 Frd.udw = lsbX;
932 break;
933 default:
934 uint64_t msbShift = Gsr<2:0> * 8;
935 uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
936 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
937 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
938 Frd.udw = ((msbX & msbMask) << msbShift) |
939 ((lsbX & lsbMask) >> lsbShift);
940 }
941 }});
942 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
943 0x4C: FailUnimpl::bshuffle();
944 0x4D: FailUnimpl::fexpand();
945 0x50: FailUnimpl::fpadd16();
946 0x51: FailUnimpl::fpadd16s();
947 0x52: FailUnimpl::fpadd32();

--- 62 unchanged lines hidden (view full) ---

1010 panic("M5 panic instruction called at pc=%#x.", pc.pc());
1011 }}, No_OpClass, IsNonSpeculative);
1012 }
1013#endif
1014 default: Trap::impdep2({{fault = new IllegalInstruction;}});
1015 }
1016 0x38: Branch::jmpl({{
1017 Addr target = Rs1 + Rs2_or_imm13;
1018 if (target & 0x3) {
1019 fault = new MemAddressNotAligned;
1020 } else {
1021 SparcISA::PCState pc = PCS;
1022 if (Pstate<3:>)
1023 Rd = (pc.pc())<31:0>;
1024 else
1025 Rd = pc.pc();
1026 pc.nnpc(target);
1027 PCS = pc;
1028 }
1029 }});
1030 0x39: Branch::return({{
1031 Addr target = Rs1 + Rs2_or_imm13;
1032 if (fault == NoFault) {
1033 // Check for fills which are higher priority than alignment
1034 // faults.
1035 if (Canrestore == 0) {
1036 if (Otherwin)
1037 fault = new FillNOther(4*Wstate<5:3>);
1038 else
1039 fault = new FillNNormal(4*Wstate<2:0>);
1040 } else if (target & 0x3) { // Check for alignment faults
1041 fault = new MemAddressNotAligned;
1042 } else {
1043 SparcISA::PCState pc = PCS;
1044 pc.nnpc(target);
1045 PCS = pc;
1046 Cwp = (Cwp - 1 + NWindows) % NWindows;
1047 Cansave = Cansave + 1;
1048 Canrestore = Canrestore - 1;
1049 }
1050 }
1051 }});
1052 0x3A: decode CC
1053 {
1054 0x0: Trap::tcci({{
1055 if (passesCondition(Ccr<3:0>, COND2)) {
1056 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
1057 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
1058 fault = new TrapInstruction(lTrapNum);
1059 }
1060 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
1061 0x2: Trap::tccx({{
1062 if (passesCondition(Ccr<7:4>, COND2)) {
1063 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
1064 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
1065 fault = new TrapInstruction(lTrapNum);
1066 }
1067 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
1068 }
1069 0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier,
1070 MemWriteOp);
1071 0x3C: save({{
1072 if (Cansave == 0) {
1073 if (Otherwin)
1074 fault = new SpillNOther(4*Wstate<5:3>);
1075 else
1076 fault = new SpillNNormal(4*Wstate<2:0>);
1077 } else if (Cleanwin - Canrestore == 0) {
1078 fault = new CleanWindow;
1079 } else {
1080 Cwp = (Cwp + 1) % NWindows;
1081 Rd_next = Rs1 + Rs2_or_imm13;
1082 Cansave = Cansave - 1;
1083 Canrestore = Canrestore + 1;
1084 }
1085 }});
1086 0x3D: restore({{
1087 if (Canrestore == 0) {
1088 if (Otherwin)
1089 fault = new FillNOther(4*Wstate<5:3>);
1090 else
1091 fault = new FillNNormal(4*Wstate<2:0>);
1092 } else {
1093 Cwp = (Cwp - 1 + NWindows) % NWindows;
1094 Rd_prev = Rs1 + Rs2_or_imm13;
1095 Cansave = Cansave + 1;
1096 Canrestore = Canrestore - 1;
1097 }
1098 }});
1099 0x3E: decode FCN {
1100 0x0: Priv::done({{

--- 35 unchanged lines hidden (view full) ---

1136 RdHigh = (Mem.tuw).b;
1137 }});
1138 }
1139 format Store {
1140 0x04: stw({{Mem.uw = Rd.sw;}});
1141 0x05: stb({{Mem.ub = Rd.sb;}});
1142 0x06: sth({{Mem.uhw = Rd.shw;}});
1143 0x07: sttw({{
1144 // This temporary needs to be here so that the parser
1145 // will correctly identify this instruction as a store.
1146 // It's probably either the parenthesis or referencing
1147 // the member variable that throws confuses it.
1148 Twin32_t temp;
1149 temp.a = RdLow<31:0>;
1150 temp.b = RdHigh<31:0>;
1151 Mem.tuw = temp;
1152 }});
1153 }
1154 format Load {
1155 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});

--- 12 unchanged lines hidden (view full) ---

1168 uint32_t tmp = mem_data;
1169 Rd.uw = tmp;
1170 }}, MEM_SWAP);
1171 format LoadAlt {
1172 0x10: lduwa({{Rd = Mem.uw;}});
1173 0x11: lduba({{Rd = Mem.ub;}});
1174 0x12: lduha({{Rd = Mem.uhw;}});
1175 0x13: decode EXT_ASI {
1176 // ASI_LDTD_AIUP
1177 0x22: TwinLoad::ldtx_aiup(
1178 {{RdLow.udw = (Mem.tudw).a;
1179 RdHigh.udw = (Mem.tudw).b;}});
1180 // ASI_LDTD_AIUS
1181 0x23: TwinLoad::ldtx_aius(
1182 {{RdLow.udw = (Mem.tudw).a;
1183 RdHigh.udw = (Mem.tudw).b;}});
1184 // ASI_QUAD_LDD
1185 0x24: TwinLoad::ldtx_quad_ldd(
1186 {{RdLow.udw = (Mem.tudw).a;
1187 RdHigh.udw = (Mem.tudw).b;}});
1188 // ASI_LDTX_REAL
1189 0x26: TwinLoad::ldtx_real(
1190 {{RdLow.udw = (Mem.tudw).a;
1191 RdHigh.udw = (Mem.tudw).b;}});
1192 // ASI_LDTX_N
1193 0x27: TwinLoad::ldtx_n(
1194 {{RdLow.udw = (Mem.tudw).a;
1195 RdHigh.udw = (Mem.tudw).b;}});
1196 // ASI_LDTX_AIUP_L
1197 0x2A: TwinLoad::ldtx_aiup_l(
1198 {{RdLow.udw = (Mem.tudw).a;
1199 RdHigh.udw = (Mem.tudw).b;}});
1200 // ASI_LDTX_AIUS_L
1201 0x2B: TwinLoad::ldtx_aius_l(
1202 {{RdLow.udw = (Mem.tudw).a;
1203 RdHigh.udw = (Mem.tudw).b;}});
1204 // ASI_LDTX_L
1205 0x2C: TwinLoad::ldtx_l(
1206 {{RdLow.udw = (Mem.tudw).a;
1207 RdHigh.udw = (Mem.tudw).b;}});
1208 // ASI_LDTX_REAL_L
1209 0x2E: TwinLoad::ldtx_real_l(
1210 {{RdLow.udw = (Mem.tudw).a;
1211 RdHigh.udw = (Mem.tudw).b;}});
1212 // ASI_LDTX_N_L
1213 0x2F: TwinLoad::ldtx_n_l(
1214 {{RdLow.udw = (Mem.tudw).a;
1215 RdHigh.udw = (Mem.tudw).b;}});
1216 // ASI_LDTX_P
1217 0xE2: TwinLoad::ldtx_p(
1218 {{RdLow.udw = (Mem.tudw).a;
1219 RdHigh.udw = (Mem.tudw).b;}});
1220 // ASI_LDTX_S
1221 0xE3: TwinLoad::ldtx_s(
1222 {{RdLow.udw = (Mem.tudw).a;
1223 RdHigh.udw = (Mem.tudw).b;}});
1224 // ASI_LDTX_PL
1225 0xEA: TwinLoad::ldtx_pl(
1226 {{RdLow.udw = (Mem.tudw).a;
1227 RdHigh.udw = (Mem.tudw).b;}});
1228 // ASI_LDTX_SL
1229 0xEB: TwinLoad::ldtx_sl(
1230 {{RdLow.udw = (Mem.tudw).a;
1231 RdHigh.udw = (Mem.tudw).b;}});
1232 default: ldtwa({{
1233 RdLow = (Mem.tuw).a;
1234 RdHigh = (Mem.tuw).b;}});
1235 }
1236 }
1237 format StoreAlt {
1238 0x14: stwa({{Mem.uw = Rd;}});
1239 0x15: stba({{Mem.ub = Rd;}});
1240 0x16: stha({{Mem.uhw = Rd;}});
1241 0x17: sttwa({{
1242 // This temporary needs to be here so that the parser
1243 // will correctly identify this instruction as a store.
1244 // It's probably either the parenthesis or referencing
1245 // the member variable that throws confuses it.
1246 Twin32_t temp;
1247 temp.a = RdLow<31:0>;
1248 temp.b = RdHigh<31:0>;
1249 Mem.tuw = temp;
1250 }});
1251 }
1252 format LoadAlt {
1253 0x18: ldswa({{Rd = (int32_t)Mem.sw;}});

--- 42 unchanged lines hidden (view full) ---

1296 }
1297 0x26: stqf({{fault = new FpDisabled;}});
1298 0x27: Store::stdf({{Mem.udw = Frd.udw;}});
1299 0x2D: Nop::prefetch({{ }});
1300 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}});
1301 0x32: ldqfa({{fault = new FpDisabled;}});
1302 format LoadAlt {
1303 0x33: decode EXT_ASI {
1304 // ASI_NUCLEUS
1305 0x04: FailUnimpl::lddfa_n();
1306 // ASI_NUCLEUS_LITTLE
1307 0x0C: FailUnimpl::lddfa_nl();
1308 // ASI_AS_IF_USER_PRIMARY
1309 0x10: FailUnimpl::lddfa_aiup();
1310 // ASI_AS_IF_USER_PRIMARY_LITTLE
1311 0x18: FailUnimpl::lddfa_aiupl();
1312 // ASI_AS_IF_USER_SECONDARY
1313 0x11: FailUnimpl::lddfa_aius();
1314 // ASI_AS_IF_USER_SECONDARY_LITTLE
1315 0x19: FailUnimpl::lddfa_aiusl();
1316 // ASI_REAL
1317 0x14: FailUnimpl::lddfa_real();
1318 // ASI_REAL_LITTLE
1319 0x1C: FailUnimpl::lddfa_real_l();
1320 // ASI_REAL_IO
1321 0x15: FailUnimpl::lddfa_real_io();
1322 // ASI_REAL_IO_LITTLE
1323 0x1D: FailUnimpl::lddfa_real_io_l();
1324 // ASI_PRIMARY
1325 0x80: FailUnimpl::lddfa_p();
1326 // ASI_PRIMARY_LITTLE
1327 0x88: FailUnimpl::lddfa_pl();
1328 // ASI_SECONDARY
1329 0x81: FailUnimpl::lddfa_s();
1330 // ASI_SECONDARY_LITTLE
1331 0x89: FailUnimpl::lddfa_sl();
1332 // ASI_PRIMARY_NO_FAULT
1333 0x82: FailUnimpl::lddfa_pnf();
1334 // ASI_PRIMARY_NO_FAULT_LITTLE
1335 0x8A: FailUnimpl::lddfa_pnfl();
1336 // ASI_SECONDARY_NO_FAULT
1337 0x83: FailUnimpl::lddfa_snf();
1338 // ASI_SECONDARY_NO_FAULT_LITTLE
1339 0x8B: FailUnimpl::lddfa_snfl();
1340
1341 format BlockLoad {
1342 // LDBLOCKF
1343 // ASI_BLOCK_AS_IF_USER_PRIMARY
1344 0x16: FailUnimpl::ldblockf_aiup();
1345 // ASI_BLOCK_AS_IF_USER_SECONDARY
1346 0x17: FailUnimpl::ldblockf_aius();
1347 // ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1348 0x1E: FailUnimpl::ldblockf_aiupl();
1349 // ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1350 0x1F: FailUnimpl::ldblockf_aiusl();
1351 // ASI_BLOCK_PRIMARY
1352 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}});
1353 // ASI_BLOCK_SECONDARY
1354 0xF1: FailUnimpl::ldblockf_s();
1355 // ASI_BLOCK_PRIMARY_LITTLE
1356 0xF8: FailUnimpl::ldblockf_pl();
1357 // ASI_BLOCK_SECONDARY_LITTLE
1358 0xF9: FailUnimpl::ldblockf_sl();
1359 }
1360
1361 // LDSHORTF
1362 // ASI_FL8_PRIMARY
1363 0xD0: FailUnimpl::ldshortf_8p();
1364 // ASI_FL8_SECONDARY
1365 0xD1: FailUnimpl::ldshortf_8s();
1366 // ASI_FL8_PRIMARY_LITTLE
1367 0xD8: FailUnimpl::ldshortf_8pl();
1368 // ASI_FL8_SECONDARY_LITTLE
1369 0xD9: FailUnimpl::ldshortf_8sl();
1370 // ASI_FL16_PRIMARY
1371 0xD2: FailUnimpl::ldshortf_16p();
1372 // ASI_FL16_SECONDARY
1373 0xD3: FailUnimpl::ldshortf_16s();
1374 // ASI_FL16_PRIMARY_LITTLE
1375 0xDA: FailUnimpl::ldshortf_16pl();
1376 // ASI_FL16_SECONDARY_LITTLE
1377 0xDB: FailUnimpl::ldshortf_16sl();
1378 // Not an ASI which is legal with lddfa
1379 default: Trap::lddfa_bad_asi(
1380 {{fault = new DataAccessException;}});
1381 }
1382 }
1383 0x34: Store::stfa({{Mem.uw = Frds.uw;}});
1384 0x36: stqfa({{fault = new FpDisabled;}});
1385 format StoreAlt {
1386 0x37: decode EXT_ASI {
1387 // ASI_NUCLEUS
1388 0x04: FailUnimpl::stdfa_n();
1389 // ASI_NUCLEUS_LITTLE
1390 0x0C: FailUnimpl::stdfa_nl();
1391 // ASI_AS_IF_USER_PRIMARY
1392 0x10: FailUnimpl::stdfa_aiup();
1393 // ASI_AS_IF_USER_PRIMARY_LITTLE
1394 0x18: FailUnimpl::stdfa_aiupl();
1395 // ASI_AS_IF_USER_SECONDARY
1396 0x11: FailUnimpl::stdfa_aius();
1397 // ASI_AS_IF_USER_SECONDARY_LITTLE
1398 0x19: FailUnimpl::stdfa_aiusl();
1399 // ASI_REAL
1400 0x14: FailUnimpl::stdfa_real();
1401 // ASI_REAL_LITTLE
1402 0x1C: FailUnimpl::stdfa_real_l();
1403 // ASI_REAL_IO
1404 0x15: FailUnimpl::stdfa_real_io();
1405 // ASI_REAL_IO_LITTLE
1406 0x1D: FailUnimpl::stdfa_real_io_l();
1407 // ASI_PRIMARY
1408 0x80: FailUnimpl::stdfa_p();
1409 // ASI_PRIMARY_LITTLE
1410 0x88: FailUnimpl::stdfa_pl();
1411 // ASI_SECONDARY
1412 0x81: FailUnimpl::stdfa_s();
1413 // ASI_SECONDARY_LITTLE
1414 0x89: FailUnimpl::stdfa_sl();
1415 // ASI_PRIMARY_NO_FAULT
1416 0x82: FailUnimpl::stdfa_pnf();
1417 // ASI_PRIMARY_NO_FAULT_LITTLE
1418 0x8A: FailUnimpl::stdfa_pnfl();
1419 // ASI_SECONDARY_NO_FAULT
1420 0x83: FailUnimpl::stdfa_snf();
1421 // ASI_SECONDARY_NO_FAULT_LITTLE
1422 0x8B: FailUnimpl::stdfa_snfl();
1423
1424 format BlockStore {
1425 // STBLOCKF
1426 // ASI_BLOCK_AS_IF_USER_PRIMARY
1427 0x16: FailUnimpl::stblockf_aiup();
1428 // ASI_BLOCK_AS_IF_USER_SECONDARY
1429 0x17: FailUnimpl::stblockf_aius();
1430 // ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1431 0x1E: FailUnimpl::stblockf_aiupl();
1432 // ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1433 0x1F: FailUnimpl::stblockf_aiusl();
1434 // ASI_BLOCK_PRIMARY
1435 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}});
1436 // ASI_BLOCK_SECONDARY
1437 0xF1: FailUnimpl::stblockf_s();
1438 // ASI_BLOCK_PRIMARY_LITTLE
1439 0xF8: FailUnimpl::stblockf_pl();
1440 // ASI_BLOCK_SECONDARY_LITTLE
1441 0xF9: FailUnimpl::stblockf_sl();
1442 }
1443
1444 // STSHORTF
1445 // ASI_FL8_PRIMARY
1446 0xD0: FailUnimpl::stshortf_8p();
1447 // ASI_FL8_SECONDARY
1448 0xD1: FailUnimpl::stshortf_8s();
1449 // ASI_FL8_PRIMARY_LITTLE
1450 0xD8: FailUnimpl::stshortf_8pl();
1451 // ASI_FL8_SECONDARY_LITTLE
1452 0xD9: FailUnimpl::stshortf_8sl();
1453 // ASI_FL16_PRIMARY
1454 0xD2: FailUnimpl::stshortf_16p();
1455 // ASI_FL16_SECONDARY
1456 0xD3: FailUnimpl::stshortf_16s();
1457 // ASI_FL16_PRIMARY_LITTLE
1458 0xDA: FailUnimpl::stshortf_16pl();
1459 // ASI_FL16_SECONDARY_LITTLE
1460 0xDB: FailUnimpl::stshortf_16sl();
1461 // Not an ASI which is legal with lddfa
1462 default: Trap::stdfa_bad_asi(
1463 {{fault = new DataAccessException;}});
1464 }
1465 }
1466 0x3C: CasAlt::casa({{
1467 mem_data = htog(Rs2.uw);
1468 Mem.uw = Rd.uw;}},
1469 {{
1470 uint32_t tmp = mem_data;
1471 Rd.uw = tmp;
1472 }}, MEM_SWAP_COND);
1473 0x3D: Nop::prefetcha({{ }});
1474 0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2);
1475 Mem.udw = Rd.udw; }},
1476 {{ Rd.udw = mem_data; }}, MEM_SWAP_COND);
1477 }
1478 }
1479}