1// Copyright (c) 2006 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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39 {
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 0x1: decode BPCC
43 {
44 format Branch19
45 {
46 0x0: bpcci({{
47 if(passesCondition(Ccr<3:0>, COND2))
48 NNPC = xc->readPC() + disp;
49 else
50 handle_annul
51 }});
52 0x2: bpccx({{
53 if(passesCondition(Ccr<7:4>, COND2))
54 NNPC = xc->readPC() + disp;
55 else
56 handle_annul
57 }});
58 }
59 }
60 0x2: Branch22::bicc({{
61 if(passesCondition(Ccr<3:0>, COND2))
62 NNPC = xc->readPC() + disp;
63 else
64 handle_annul
65 }});
66 0x3: decode RCOND2
67 {
68 format BranchSplit
69 {

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119 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
120 0x01: and({{Rd = Rs1.udw & Rs2_or_imm13;}});
121 0x02: or({{Rd = Rs1.udw | Rs2_or_imm13;}});
122 0x03: xor({{Rd = Rs1.udw ^ Rs2_or_imm13;}});
123 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
124 0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm13;}});
125 0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm13;}});
126 0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm13);}});
127 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
128 0x09: mulx({{Rd = Rs1 * Rs2_or_imm13;}});
129 0x0A: umul({{
130 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
131 Y = Rd<63:32>;
132 }});
133 0x0B: smul({{
134 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
135 Y = Rd.sdw;
136 }});
137 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 + Ccr<0:0>}});
138 0x0D: udivx({{
139 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
140 else Rd.udw = Rs1.udw / Rs2_or_imm13;
141 }});
142 0x0E: udiv({{
143 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
144 else
145 {
146 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
147 if(Rd.udw >> 32 != 0)
148 Rd.udw = 0xFFFFFFFF;
149 }
150 }});
151 0x0F: sdiv({{
152 if(Rs2_or_imm13.sdw == 0)
153 fault = new DivisionByZero;
154 else
155 {
156 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
157 if(Rd.udw<63:31> != 0)
158 Rd.udw = 0x7FFFFFFF;
159 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
160 Rd.udw = 0xFFFFFFFF80000000ULL;
161 }
162 }});
163 }
164 format IntOpCc {

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182 (Rs1 | ~val2)<0:>))<63:>}},
183 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
184 );
185 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
186 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
187 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
188 0x18: addccc({{
189 int64_t resTemp, val2 = Rs2_or_imm13;
190 int64_t carryin = Ccr<0:0>;
191 Rd = resTemp = Rs1 + val2 + carryin;}},
192 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
193 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
194 {{(Rs1<63:1> + val2<63:1> +
195 ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
196 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
197 );
198 0x1A: umulcc({{
199 uint64_t resTemp;
200 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
201 Y = resTemp<63:32>;}},
202 {{0}},{{0}},{{0}},{{0}});
203 0x1B: smulcc({{
204 int64_t resTemp;
205 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>;
206 Y = resTemp<63:32>;}},
207 {{0}},{{0}},{{0}},{{0}});
208 0x1C: subccc({{
209 int64_t resTemp, val2 = Rs2_or_imm13;
210 int64_t carryin = Ccr<0:0>;
211 Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}},
212 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
213 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
214 {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
215 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
216 );
217 0x1D: udivxcc({{
218 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
219 else Rd = Rs1.udw / Rs2_or_imm13.udw;}}
220 ,{{0}},{{0}},{{0}},{{0}});
221 0x1E: udivcc({{
222 uint32_t resTemp, val2 = Rs2_or_imm13.udw;
223 int32_t overflow;
224 if(val2 == 0) fault = new DivisionByZero;
225 else
226 {
227 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
228 overflow = (resTemp<63:32> != 0);
229 if(overflow) Rd = resTemp = 0xFFFFFFFF;
230 else Rd = resTemp;
231 } }},
232 {{0}},
233 {{overflow}},
234 {{0}},
235 {{0}}
236 );
237 0x1F: sdivcc({{
238 int32_t resTemp, val2 = Rs2_or_imm13.sdw;
239 int32_t overflow, underflow;
240 if(val2 == 0) fault = new DivisionByZero;
241 else
242 {
243 Rd = resTemp = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
244 overflow = (resTemp<63:31> != 0);
245 underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
246 if(overflow) Rd = resTemp = 0x7FFFFFFF;
247 else if(underflow) Rd = resTemp = 0xFFFFFFFF80000000ULL;
248 else Rd = resTemp;
249 } }},
250 {{0}},
251 {{overflow || underflow}},

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290 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
291 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
292 );
293 0x24: mulscc({{
294 int64_t resTemp, multiplicand = Rs2_or_imm13;
295 int32_t multiplier = Rs1<31:0>;
296 int32_t savedLSB = Rs1<0:>;
297 multiplier = multiplier<31:1> |
298 ((Ccr<3:3>
299 ^ Ccr<1:1>) << 32);
300 if(!Y<0:>)
301 multiplicand = 0;
302 Rd = resTemp = multiplicand + multiplier;
303 Y = Y<31:1> | (savedLSB << 31);}},
304 {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
305 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
306 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
307 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
308 );
309 }
310 format IntOp
311 {

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316 0x26: decode X {
317 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
318 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
319 }
320 0x27: decode X {
321 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
322 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
323 }
324 // XXX might want a format rdipr thing here
325 0x28: rdasr({{
326 Rd = xc->readMiscRegWithEffect(RS1 + AsrStart, fault);
327 }});
328 0x29: rdhpr({{
329 // XXX Need to protect with format that traps non-priv/priv
330 // access
331 Rd = xc->readMiscRegWithEffect(RS1 + HprStart, fault);
332 }});
333 0x2A: rdpr({{
334 // XXX Need to protect with format that traps non-priv
335 // access
336 Rd = xc->readMiscRegWithEffect(RS1 + PrStart, fault);
337 }});
338 0x2B: BasicOperate::flushw({{
339 if(NWindows - 2 - Cansave == 0)
340 {
341 if(Otherwin)
342 fault = new SpillNOther(Wstate<5:3>);
343 else
344 fault = new SpillNNormal(Wstate<2:0>);
345 }
346 }});
347 0x2C: decode MOVCC3
348 {
349 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
350 0x1: decode CC
351 {
352 0x0: movcci({{
353 if(passesCondition(Ccr<3:0>, COND4))
354 Rd = Rs2_or_imm11;
355 else
356 Rd = Rd;
357 }});
358 0x2: movccx({{
359 if(passesCondition(Ccr<7:4>, COND4))
360 Rd = Rs2_or_imm11;
361 else
362 Rd = Rd;
363 }});
364 }
365 }
366 0x2D: sdivx({{
367 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;

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385 {
386 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
387 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
388 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
389 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
390 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
391 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
392 }
393 0x30: wrasr({{
394 xc->setMiscRegWithEffect(RD + AsrStart, Rs1 ^ Rs2_or_imm13);
395 }});
396 0x31: decode FCN {
397 0x0: BasicOperate::saved({{/*Boogy Boogy*/}});
398 0x1: BasicOperate::restored({{/*Boogy Boogy*/}});
399 }
400 0x32: wrpr({{
401 // XXX Need to protect with format that traps non-priv
402 // access
403 xc->setMiscRegWithEffect(RD + PrStart, Rs1 ^ Rs2_or_imm13);
404 }});
405 0x33: wrhpr({{
406 // XXX Need to protect with format that traps non-priv/priv
407 // access
408 xc->setMiscRegWithEffect(RD + HprStart, Rs1 ^ Rs2_or_imm13);
409 }});
410 0x34: Trap::fpop1({{fault = new FpDisabled;}});
411 0x35: Trap::fpop2({{fault = new FpDisabled;}});
412 0x38: Branch::jmpl({{
413 Addr target = Rs1 + Rs2_or_imm13;
414 if(target & 0x3)
415 fault = new MemAddressNotAligned;
416 else
417 {

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432 {
433 //CWP should be set directly so that it always happens
434 //Also, this will allow writing to the new window and
435 //reading from the old one
436 Cwp = (Cwp - 1 + NWindows) % NWindows;
437 if(Canrestore == 0)
438 {
439 if(Otherwin)
440 fault = new FillNOther(Wstate<5:3>);
441 else
442 fault = new FillNNormal(Wstate<2:0>);
443 }
444 else
445 {
446 Rd = Rs1 + Rs2_or_imm13;
447 Cansave = Cansave + 1;
448 Canrestore = Canrestore - 1;
449 }
450 //This is here to make sure the CWP is written
451 //no matter what. This ensures that the results
452 //are written in the new window as well.
453 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
454 }
455 }});
456 0x3A: decode CC
457 {
458 0x0: Trap::tcci({{
459 if(passesCondition(Ccr<3:0>, COND2))
460 {
461 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
462 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
463#if FULL_SYSTEM
464 fault = new TrapInstruction(lTrapNum);
465#else
466 DPRINTF(Sparc, "The syscall number is %d\n", R1);
467 xc->syscall(R1);
468#endif
469 }
470 }});
471 0x2: Trap::tccx({{
472 if(passesCondition(Ccr<7:4>, COND2))
473 {
474 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
475 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
476#if FULL_SYSTEM
477 fault = new TrapInstruction(lTrapNum);
478#else
479 DPRINTF(Sparc, "The syscall number is %d\n", R1);
480 xc->syscall(R1);

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485 0x3B: Nop::flush({{/*Instruction memory flush*/}});
486 0x3C: save({{
487 //CWP should be set directly so that it always happens
488 //Also, this will allow writing to the new window and
489 //reading from the old one
490 if(Cansave == 0)
491 {
492 if(Otherwin)
493 fault = new SpillNOther(Wstate<5:3>);
494 else
495 fault = new SpillNNormal(Wstate<2:0>);
496 Cwp = (Cwp + 2) % NWindows;
497 }
498 else if(Cleanwin - Canrestore == 0)
499 {
500 Cwp = (Cwp + 1) % NWindows;
501 fault = new CleanWindow;
502 }
503 else

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515 0x3D: restore({{
516 //CWP should be set directly so that it always happens
517 //Also, this will allow writing to the new window and
518 //reading from the old one
519 Cwp = (Cwp - 1 + NWindows) % NWindows;
520 if(Canrestore == 0)
521 {
522 if(Otherwin)
523 fault = new FillNOther(Wstate<5:3>);
524 else
525 fault = new FillNNormal(Wstate<2:0>);
526 }
527 else
528 {
529 Rd = Rs1 + Rs2_or_imm13;
530 Cansave = Cansave + 1;
531 Canrestore = Canrestore - 1;
532 }
533 //This is here to make sure the CWP is written
534 //no matter what. This ensures that the results
535 //are written in the new window as well.
536 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
537 }});
538 0x3E: decode FCN {
539 0x0: Priv::done({{
540 if(Tl == 0)
541 return new IllegalInstruction;
542
543 Cwp = Tstate<4:0>;
544 Pstate = Tstate<20:8>;
545 Asi = Tstate<31:24>;
546 Ccr = Tstate<39:32>;
547 Gl = Tstate<42:40>;
548 NPC = Tnpc;
549 NNPC = Tnpc + 4;
550 Tl = Tl - 1;
551 }});
552 0x1: BasicOperate::retry({{
553 if(Tl == 0)
554 return new IllegalInstruction;
555 Cwp = Tstate<4:0>;
556 Pstate = Tstate<20:8>;
557 Asi = Tstate<31:24>;
558 Ccr = Tstate<39:32>;
559 Gl = Tstate<42:40>;
560 NPC = Tpc;
561 NNPC = Tnpc + 4;
562 Tl = Tl - 1;
563 }});
564 }
565 }
566 }
567 0x3: decode OP3 {
568 format Load {
569 0x00: lduw({{Rd = Mem;}}, {{32}});

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