base.isa (7720:65d338a8dba4) | base.isa (7741:340b6f01d69b) |
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1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 105 unchanged lines hidden (view full) --- 114 115 void advancePC(SparcISA::PCState &pcState) const; 116 }; 117 118 bool passesFpCondition(uint32_t fcc, uint32_t condition); 119 120 bool passesCondition(uint32_t codes, uint32_t condition); 121 | 1// Copyright (c) 2006-2007 The Regents of The University of Michigan 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are 6// met: redistributions of source code must retain the above copyright 7// notice, this list of conditions and the following disclaimer; 8// redistributions in binary form must reproduce the above copyright --- 105 unchanged lines hidden (view full) --- 114 115 void advancePC(SparcISA::PCState &pcState) const; 116 }; 117 118 bool passesFpCondition(uint32_t fcc, uint32_t condition); 119 120 bool passesCondition(uint32_t codes, uint32_t condition); 121 |
122 inline int64_t sign_ext(uint64_t data, int origWidth) | 122 inline int64_t 123 sign_ext(uint64_t data, int origWidth) |
123 { 124 int shiftAmount = 64 - origWidth; 125 return (((int64_t)data) << shiftAmount) >> shiftAmount; 126 } 127}}; 128 129output decoder {{ 130 131 const char *CondTestAbbrev[] = 132 { | 124 { 125 int shiftAmount = 64 - origWidth; 126 return (((int64_t)data) << shiftAmount) >> shiftAmount; 127 } 128}}; 129 130output decoder {{ 131 132 const char *CondTestAbbrev[] = 133 { |
133 "nev", //Never 134 "e", //Equal 135 "le", //Less or Equal 136 "l", //Less 137 "leu", //Less or Equal Unsigned 138 "c", //Carry set 139 "n", //Negative 140 "o", //Overflow set 141 "a", //Always 142 "ne", //Not Equal 143 "g", //Greater 144 "ge", //Greater or Equal 145 "gu", //Greater Unsigned 146 "cc", //Carry clear 147 "p", //Positive 148 "oc" //Overflow Clear | 134 "nev", // Never 135 "e", // Equal 136 "le", // Less or Equal 137 "l", // Less 138 "leu", // Less or Equal Unsigned 139 "c", // Carry set 140 "n", // Negative 141 "o", // Overflow set 142 "a", // Always 143 "ne", // Not Equal 144 "g", // Greater 145 "ge", // Greater or Equal 146 "gu", // Greater Unsigned 147 "cc", // Carry clear 148 "p", // Positive 149 "oc" // Overflow Clear |
149 }; 150}}; 151 152def template ROrImmDecode {{ 153 { 154 return (I ? (SparcStaticInst *)(new %(class_name)sImm(machInst)) 155 : (SparcStaticInst *)(new %(class_name)s(machInst))); 156 } --- 90 unchanged lines hidden (view full) --- 247 inline void printMnemonic(std::ostream &os, const char * mnemonic) 248 { 249 ccprintf(os, "\t%s ", mnemonic); 250 } 251 252 void SparcStaticInst::printRegArray(std::ostream &os, 253 const RegIndex indexArray[], int num) const 254 { | 150 }; 151}}; 152 153def template ROrImmDecode {{ 154 { 155 return (I ? (SparcStaticInst *)(new %(class_name)sImm(machInst)) 156 : (SparcStaticInst *)(new %(class_name)s(machInst))); 157 } --- 90 unchanged lines hidden (view full) --- 248 inline void printMnemonic(std::ostream &os, const char * mnemonic) 249 { 250 ccprintf(os, "\t%s ", mnemonic); 251 } 252 253 void SparcStaticInst::printRegArray(std::ostream &os, 254 const RegIndex indexArray[], int num) const 255 { |
255 if(num <= 0) | 256 if (num <= 0) |
256 return; 257 printReg(os, indexArray[0]); | 257 return; 258 printReg(os, indexArray[0]); |
258 for(int x = 1; x < num; x++) 259 { | 259 for (int x = 1; x < num; x++) { |
260 os << ", "; 261 printReg(os, indexArray[x]); 262 } 263 } 264 265 void 266 SparcStaticInst::advancePC(SparcISA::PCState &pcState) const 267 { 268 pcState.advance(); 269 } 270 271 void 272 SparcStaticInst::printSrcReg(std::ostream &os, int reg) const 273 { | 260 os << ", "; 261 printReg(os, indexArray[x]); 262 } 263 } 264 265 void 266 SparcStaticInst::advancePC(SparcISA::PCState &pcState) const 267 { 268 pcState.advance(); 269 } 270 271 void 272 SparcStaticInst::printSrcReg(std::ostream &os, int reg) const 273 { |
274 if(_numSrcRegs > reg) | 274 if (_numSrcRegs > reg) |
275 printReg(os, _srcRegIdx[reg]); 276 } 277 278 void 279 SparcStaticInst::printDestReg(std::ostream &os, int reg) const 280 { | 275 printReg(os, _srcRegIdx[reg]); 276 } 277 278 void 279 SparcStaticInst::printDestReg(std::ostream &os, int reg) const 280 { |
281 if(_numDestRegs > reg) | 281 if (_numDestRegs > reg) |
282 printReg(os, _destRegIdx[reg]); 283 } 284 285 void 286 SparcStaticInst::printReg(std::ostream &os, int reg) const 287 { 288 const int MaxGlobal = 8; 289 const int MaxOutput = 16; 290 const int MaxLocal = 24; 291 const int MaxInput = 32; 292 const int MaxMicroReg = 40; 293 if (reg < FP_Base_DepTag) { | 282 printReg(os, _destRegIdx[reg]); 283 } 284 285 void 286 SparcStaticInst::printReg(std::ostream &os, int reg) const 287 { 288 const int MaxGlobal = 8; 289 const int MaxOutput = 16; 290 const int MaxLocal = 24; 291 const int MaxInput = 32; 292 const int MaxMicroReg = 40; 293 if (reg < FP_Base_DepTag) { |
294 //If we used a register from the next or previous window, 295 //take out the offset. | 294 // If we used a register from the next or previous window, 295 // take out the offset. |
296 while (reg >= MaxMicroReg) 297 reg -= MaxMicroReg; 298 if (reg == FramePointerReg) 299 ccprintf(os, "%%fp"); 300 else if (reg == StackPointerReg) 301 ccprintf(os, "%%sp"); | 296 while (reg >= MaxMicroReg) 297 reg -= MaxMicroReg; 298 if (reg == FramePointerReg) 299 ccprintf(os, "%%fp"); 300 else if (reg == StackPointerReg) 301 ccprintf(os, "%%sp"); |
302 else if(reg < MaxGlobal) | 302 else if (reg < MaxGlobal) |
303 ccprintf(os, "%%g%d", reg); | 303 ccprintf(os, "%%g%d", reg); |
304 else if(reg < MaxOutput) | 304 else if (reg < MaxOutput) |
305 ccprintf(os, "%%o%d", reg - MaxGlobal); | 305 ccprintf(os, "%%o%d", reg - MaxGlobal); |
306 else if(reg < MaxLocal) | 306 else if (reg < MaxLocal) |
307 ccprintf(os, "%%l%d", reg - MaxOutput); | 307 ccprintf(os, "%%l%d", reg - MaxOutput); |
308 else if(reg < MaxInput) | 308 else if (reg < MaxInput) |
309 ccprintf(os, "%%i%d", reg - MaxLocal); | 309 ccprintf(os, "%%i%d", reg - MaxLocal); |
310 else if(reg < MaxMicroReg) | 310 else if (reg < MaxMicroReg) |
311 ccprintf(os, "%%u%d", reg - MaxInput); | 311 ccprintf(os, "%%u%d", reg - MaxInput); |
312 //The fake int regs that are really control regs | 312 // The fake int regs that are really control regs |
313 else { 314 switch (reg - MaxMicroReg) { 315 case 1: 316 ccprintf(os, "%%y"); 317 break; 318 case 2: 319 ccprintf(os, "%%ccr"); 320 break; --- 109 unchanged lines hidden (view full) --- 430 ccprintf(os, "%%fsr"); 431 break; 432 default: 433 ccprintf(os, "%%ctrl%d", reg - Ctrl_Base_DepTag); 434 } 435 } 436 } 437 | 313 else { 314 switch (reg - MaxMicroReg) { 315 case 1: 316 ccprintf(os, "%%y"); 317 break; 318 case 2: 319 ccprintf(os, "%%ccr"); 320 break; --- 109 unchanged lines hidden (view full) --- 430 ccprintf(os, "%%fsr"); 431 break; 432 default: 433 ccprintf(os, "%%ctrl%d", reg - Ctrl_Base_DepTag); 434 } 435 } 436 } 437 |
438 std::string SparcStaticInst::generateDisassembly(Addr pc, 439 const SymbolTable *symtab) const | 438 std::string 439 SparcStaticInst::generateDisassembly(Addr pc, 440 const SymbolTable *symtab) const |
440 { 441 std::stringstream ss; 442 443 printMnemonic(ss, mnemonic); 444 445 // just print the first two source regs... if there's 446 // a third one, it's a read-modify-write dest (Rc), 447 // e.g. for CMOVxx | 441 { 442 std::stringstream ss; 443 444 printMnemonic(ss, mnemonic); 445 446 // just print the first two source regs... if there's 447 // a third one, it's a read-modify-write dest (Rc), 448 // e.g. for CMOVxx |
448 if(_numSrcRegs > 0) 449 { | 449 if (_numSrcRegs > 0) |
450 printReg(ss, _srcRegIdx[0]); | 450 printReg(ss, _srcRegIdx[0]); |
451 } 452 if(_numSrcRegs > 1) 453 { | 451 if (_numSrcRegs > 1) { |
454 ss << ","; 455 printReg(ss, _srcRegIdx[1]); 456 } 457 458 // just print the first dest... if there's a second one, 459 // it's generally implicit | 452 ss << ","; 453 printReg(ss, _srcRegIdx[1]); 454 } 455 456 // just print the first dest... if there's a second one, 457 // it's generally implicit |
460 if(_numDestRegs > 0) 461 { 462 if(_numSrcRegs > 0) | 458 if (_numDestRegs > 0) { 459 if (_numSrcRegs > 0) |
463 ss << ","; 464 printReg(ss, _destRegIdx[0]); 465 } 466 467 return ss.str(); 468 } 469 | 460 ss << ","; 461 printReg(ss, _destRegIdx[0]); 462 } 463 464 return ss.str(); 465 } 466 |
470 bool passesFpCondition(uint32_t fcc, uint32_t condition) | 467 bool 468 passesFpCondition(uint32_t fcc, uint32_t condition) |
471 { 472 bool u = (fcc == 3); 473 bool g = (fcc == 2); 474 bool l = (fcc == 1); 475 bool e = (fcc == 0); | 469 { 470 bool u = (fcc == 3); 471 bool g = (fcc == 2); 472 bool l = (fcc == 1); 473 bool e = (fcc == 0); |
476 switch(condition) 477 { | 474 switch (condition) { |
478 case FAlways: 479 return 1; 480 case FNever: 481 return 0; 482 case FUnordered: 483 return u; 484 case FGreater: 485 return g; --- 21 unchanged lines hidden (view full) --- 507 return u || l || e; 508 case FOrdered: 509 return e || l || g; 510 } 511 panic("Tried testing condition nonexistant " 512 "condition code %d", condition); 513 } 514 | 475 case FAlways: 476 return 1; 477 case FNever: 478 return 0; 479 case FUnordered: 480 return u; 481 case FGreater: 482 return g; --- 21 unchanged lines hidden (view full) --- 504 return u || l || e; 505 case FOrdered: 506 return e || l || g; 507 } 508 panic("Tried testing condition nonexistant " 509 "condition code %d", condition); 510 } 511 |
515 bool passesCondition(uint32_t codes, uint32_t condition) | 512 bool 513 passesCondition(uint32_t codes, uint32_t condition) |
516 { 517 CondCodes condCodes; 518 condCodes.bits = 0; 519 condCodes.c = codes & 0x1 ? 1 : 0; 520 condCodes.v = codes & 0x2 ? 1 : 0; 521 condCodes.z = codes & 0x4 ? 1 : 0; 522 condCodes.n = codes & 0x8 ? 1 : 0; 523 | 514 { 515 CondCodes condCodes; 516 condCodes.bits = 0; 517 condCodes.c = codes & 0x1 ? 1 : 0; 518 condCodes.v = codes & 0x2 ? 1 : 0; 519 condCodes.z = codes & 0x4 ? 1 : 0; 520 condCodes.n = codes & 0x8 ? 1 : 0; 521 |
524 switch(condition) 525 { | 522 switch (condition) { |
526 case Always: 527 return true; 528 case Never: 529 return false; 530 case NotEqual: 531 return !condCodes.z; 532 case Equal: 533 return condCodes.z; --- 28 unchanged lines hidden (view full) --- 562}}; 563 564output exec {{ 565 /// Check "FP enabled" machine status bit. Called when executing any FP 566 /// instruction in full-system mode. 567 /// @retval Full-system mode: NoFault if FP is enabled, FpDisabled 568 /// if not. Non-full-system mode: always returns NoFault. 569#if FULL_SYSTEM | 523 case Always: 524 return true; 525 case Never: 526 return false; 527 case NotEqual: 528 return !condCodes.z; 529 case Equal: 530 return condCodes.z; --- 28 unchanged lines hidden (view full) --- 559}}; 560 561output exec {{ 562 /// Check "FP enabled" machine status bit. Called when executing any FP 563 /// instruction in full-system mode. 564 /// @retval Full-system mode: NoFault if FP is enabled, FpDisabled 565 /// if not. Non-full-system mode: always returns NoFault. 566#if FULL_SYSTEM |
570 inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) | 567 inline Fault 568 checkFpEnableFault(%(CPU_exec_context)s *xc) |
571 { 572 Fault fault = NoFault; // dummy... this ipr access should not fault 573 if (xc->readMiscReg(MISCREG_PSTATE) & PSTATE::pef && | 569 { 570 Fault fault = NoFault; // dummy... this ipr access should not fault 571 if (xc->readMiscReg(MISCREG_PSTATE) & PSTATE::pef && |
574 xc->readMiscReg(MISCREG_FPRS) & 0x4) | 572 xc->readMiscReg(MISCREG_FPRS) & 0x4) { |
575 return NoFault; | 573 return NoFault; |
576 else | 574 } else { |
577 return new FpDisabled; | 575 return new FpDisabled; |
576 } |
|
578 } 579#else | 577 } 578#else |
580 inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) | 579 inline Fault 580 checkFpEnableFault(%(CPU_exec_context)s *xc) |
581 { 582 return NoFault; 583 } 584#endif 585}}; 586 587 | 581 { 582 return NoFault; 583 } 584#endif 585}}; 586 587 |