base.isa (11981:0c5089b6133d) base.isa (12104:edd63f9c6184)
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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100 ExtMachInst _machInst, OpClass __opClass)
101 : StaticInst(mnem, _machInst, __opClass)
102 {
103 }
104
105 std::string generateDisassembly(Addr pc,
106 const SymbolTable *symtab) const;
107
1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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100 ExtMachInst _machInst, OpClass __opClass)
101 : StaticInst(mnem, _machInst, __opClass)
102 {
103 }
104
105 std::string generateDisassembly(Addr pc,
106 const SymbolTable *symtab) const;
107
108 void printReg(std::ostream &os, int reg) const;
108 void printReg(std::ostream &os, RegId reg) const;
109 void printSrcReg(std::ostream &os, int reg) const;
110 void printDestReg(std::ostream &os, int reg) const;
111
112 void printRegArray(std::ostream &os,
109 void printSrcReg(std::ostream &os, int reg) const;
110 void printDestReg(std::ostream &os, int reg) const;
111
112 void printRegArray(std::ostream &os,
113 const RegIndex indexArray[], int num) const;
113 const RegId indexArray[], int num) const;
114
115 void advancePC(SparcISA::PCState &pcState) const;
116 };
117
118 bool passesFpCondition(uint32_t fcc, uint32_t condition);
119
120 bool passesCondition(uint32_t codes, uint32_t condition);
121

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246output decoder {{
247
248 inline void printMnemonic(std::ostream &os, const char * mnemonic)
249 {
250 ccprintf(os, "\t%s ", mnemonic);
251 }
252
253 void SparcStaticInst::printRegArray(std::ostream &os,
114
115 void advancePC(SparcISA::PCState &pcState) const;
116 };
117
118 bool passesFpCondition(uint32_t fcc, uint32_t condition);
119
120 bool passesCondition(uint32_t codes, uint32_t condition);
121

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246output decoder {{
247
248 inline void printMnemonic(std::ostream &os, const char * mnemonic)
249 {
250 ccprintf(os, "\t%s ", mnemonic);
251 }
252
253 void SparcStaticInst::printRegArray(std::ostream &os,
254 const RegIndex indexArray[], int num) const
254 const RegId indexArray[], int num) const
255 {
256 if (num <= 0)
257 return;
258 printReg(os, indexArray[0]);
259 for (int x = 1; x < num; x++) {
260 os << ", ";
261 printReg(os, indexArray[x]);
262 }

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278 void
279 SparcStaticInst::printDestReg(std::ostream &os, int reg) const
280 {
281 if (_numDestRegs > reg)
282 printReg(os, _destRegIdx[reg]);
283 }
284
285 void
255 {
256 if (num <= 0)
257 return;
258 printReg(os, indexArray[0]);
259 for (int x = 1; x < num; x++) {
260 os << ", ";
261 printReg(os, indexArray[x]);
262 }

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278 void
279 SparcStaticInst::printDestReg(std::ostream &os, int reg) const
280 {
281 if (_numDestRegs > reg)
282 printReg(os, _destRegIdx[reg]);
283 }
284
285 void
286 SparcStaticInst::printReg(std::ostream &os, int reg) const
286 SparcStaticInst::printReg(std::ostream &os, RegId reg) const
287 {
288 const int MaxGlobal = 8;
289 const int MaxOutput = 16;
290 const int MaxLocal = 24;
291 const int MaxInput = 32;
292 const int MaxMicroReg = 40;
287 {
288 const int MaxGlobal = 8;
289 const int MaxOutput = 16;
290 const int MaxLocal = 24;
291 const int MaxInput = 32;
292 const int MaxMicroReg = 40;
293 if (reg < FP_Reg_Base) {
293 RegIndex reg_idx = reg.regIdx;
294 if (reg.regClass == IntRegClass) {
294 // If we used a register from the next or previous window,
295 // take out the offset.
295 // If we used a register from the next or previous window,
296 // take out the offset.
296 while (reg >= MaxMicroReg)
297 reg -= MaxMicroReg;
298 if (reg == FramePointerReg)
297 while (reg_idx >= MaxMicroReg)
298 reg_idx -= MaxMicroReg;
299 if (reg_idx == FramePointerReg)
299 ccprintf(os, "%%fp");
300 ccprintf(os, "%%fp");
300 else if (reg == StackPointerReg)
301 else if (reg_idx == StackPointerReg)
301 ccprintf(os, "%%sp");
302 ccprintf(os, "%%sp");
302 else if (reg < MaxGlobal)
303 ccprintf(os, "%%g%d", reg);
304 else if (reg < MaxOutput)
305 ccprintf(os, "%%o%d", reg - MaxGlobal);
306 else if (reg < MaxLocal)
307 ccprintf(os, "%%l%d", reg - MaxOutput);
308 else if (reg < MaxInput)
309 ccprintf(os, "%%i%d", reg - MaxLocal);
310 else if (reg < MaxMicroReg)
311 ccprintf(os, "%%u%d", reg - MaxInput);
303 else if (reg_idx < MaxGlobal)
304 ccprintf(os, "%%g%d", reg_idx);
305 else if (reg_idx < MaxOutput)
306 ccprintf(os, "%%o%d", reg_idx - MaxGlobal);
307 else if (reg_idx < MaxLocal)
308 ccprintf(os, "%%l%d", reg_idx - MaxOutput);
309 else if (reg_idx < MaxInput)
310 ccprintf(os, "%%i%d", reg_idx - MaxLocal);
311 else if (reg_idx < MaxMicroReg)
312 ccprintf(os, "%%u%d", reg_idx - MaxInput);
312 // The fake int regs that are really control regs
313 else {
313 // The fake int regs that are really control regs
314 else {
314 switch (reg - MaxMicroReg) {
315 switch (reg_idx - MaxMicroReg) {
315 case 1:
316 ccprintf(os, "%%y");
317 break;
318 case 2:
319 ccprintf(os, "%%ccr");
320 break;
321 case 3:
322 ccprintf(os, "%%cansave");

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330 case 6:
331 ccprintf(os, "%%otherwin");
332 break;
333 case 7:
334 ccprintf(os, "%%wstate");
335 break;
336 }
337 }
316 case 1:
317 ccprintf(os, "%%y");
318 break;
319 case 2:
320 ccprintf(os, "%%ccr");
321 break;
322 case 3:
323 ccprintf(os, "%%cansave");

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331 case 6:
332 ccprintf(os, "%%otherwin");
333 break;
334 case 7:
335 ccprintf(os, "%%wstate");
336 break;
337 }
338 }
338 } else if (reg < Misc_Reg_Base) {
339 ccprintf(os, "%%f%d", reg - FP_Reg_Base);
339 } else if (reg.regClass == FloatRegClass) {
340 ccprintf(os, "%%f%d", reg_idx);
340 } else {
341 } else {
341 switch (reg - Misc_Reg_Base) {
342 switch (reg_idx) {
342 case MISCREG_ASI:
343 ccprintf(os, "%%asi");
344 break;
345 case MISCREG_FPRS:
346 ccprintf(os, "%%fprs");
347 break;
348 case MISCREG_PCR:
349 ccprintf(os, "%%pcr");

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425 break;
426 case MISCREG_STRAND_STS_REG:
427 ccprintf(os, "%%strand_sts_reg");
428 break;
429 case MISCREG_FSR:
430 ccprintf(os, "%%fsr");
431 break;
432 default:
343 case MISCREG_ASI:
344 ccprintf(os, "%%asi");
345 break;
346 case MISCREG_FPRS:
347 ccprintf(os, "%%fprs");
348 break;
349 case MISCREG_PCR:
350 ccprintf(os, "%%pcr");

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426 break;
427 case MISCREG_STRAND_STS_REG:
428 ccprintf(os, "%%strand_sts_reg");
429 break;
430 case MISCREG_FSR:
431 ccprintf(os, "%%fsr");
432 break;
433 default:
433 ccprintf(os, "%%ctrl%d", reg - Misc_Reg_Base);
434 ccprintf(os, "%%ctrl%d", reg_idx);
434 }
435 }
436 }
437
438 std::string
439 SparcStaticInst::generateDisassembly(Addr pc,
440 const SymbolTable *symtab) const
441 {

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436 }
437 }
438
439 std::string
440 SparcStaticInst::generateDisassembly(Addr pc,
441 const SymbolTable *symtab) const
442 {

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