1// Copyright (c) 2006-2007 The Regents of The University of Michigan
2// All rights reserved.
3//
4// Redistribution and use in source and binary forms, with or without
5// modification, are permitted provided that the following conditions are
6// met: redistributions of source code must retain the above copyright
7// notice, this list of conditions and the following disclaimer;
8// redistributions in binary form must reproduce the above copyright

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114
115 void advancePC(SparcISA::PCState &pcState) const;
116 };
117
118 bool passesFpCondition(uint32_t fcc, uint32_t condition);
119
120 bool passesCondition(uint32_t codes, uint32_t condition);
121
122 inline int64_t
123 sign_ext(uint64_t data, int origWidth)
124 {
125 int shiftAmount = 64 - origWidth;
126 return (((int64_t)data) << shiftAmount) >> shiftAmount;
127 }
128}};
129
130output decoder {{
131
132 const char *CondTestAbbrev[] =
133 {
134 "nev", // Never
135 "e", // Equal
136 "le", // Less or Equal
137 "l", // Less
138 "leu", // Less or Equal Unsigned
139 "c", // Carry set
140 "n", // Negative
141 "o", // Overflow set
142 "a", // Always
143 "ne", // Not Equal
144 "g", // Greater
145 "ge", // Greater or Equal
146 "gu", // Greater Unsigned
147 "cc", // Carry clear
148 "p", // Positive
149 "oc" // Overflow Clear
150 };
151}};
152
153def template ROrImmDecode {{
154 {
155 return (I ? (SparcStaticInst *)(new %(class_name)sImm(machInst))
156 : (SparcStaticInst *)(new %(class_name)s(machInst)));
157 }

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248 inline void printMnemonic(std::ostream &os, const char * mnemonic)
249 {
250 ccprintf(os, "\t%s ", mnemonic);
251 }
252
253 void SparcStaticInst::printRegArray(std::ostream &os,
254 const RegIndex indexArray[], int num) const
255 {
256 if (num <= 0)
257 return;
258 printReg(os, indexArray[0]);
259 for (int x = 1; x < num; x++) {
260 os << ", ";
261 printReg(os, indexArray[x]);
262 }
263 }
264
265 void
266 SparcStaticInst::advancePC(SparcISA::PCState &pcState) const
267 {
268 pcState.advance();
269 }
270
271 void
272 SparcStaticInst::printSrcReg(std::ostream &os, int reg) const
273 {
274 if (_numSrcRegs > reg)
275 printReg(os, _srcRegIdx[reg]);
276 }
277
278 void
279 SparcStaticInst::printDestReg(std::ostream &os, int reg) const
280 {
281 if (_numDestRegs > reg)
282 printReg(os, _destRegIdx[reg]);
283 }
284
285 void
286 SparcStaticInst::printReg(std::ostream &os, int reg) const
287 {
288 const int MaxGlobal = 8;
289 const int MaxOutput = 16;
290 const int MaxLocal = 24;
291 const int MaxInput = 32;
292 const int MaxMicroReg = 40;
293 if (reg < FP_Base_DepTag) {
294 // If we used a register from the next or previous window,
295 // take out the offset.
296 while (reg >= MaxMicroReg)
297 reg -= MaxMicroReg;
298 if (reg == FramePointerReg)
299 ccprintf(os, "%%fp");
300 else if (reg == StackPointerReg)
301 ccprintf(os, "%%sp");
302 else if (reg < MaxGlobal)
303 ccprintf(os, "%%g%d", reg);
304 else if (reg < MaxOutput)
305 ccprintf(os, "%%o%d", reg - MaxGlobal);
306 else if (reg < MaxLocal)
307 ccprintf(os, "%%l%d", reg - MaxOutput);
308 else if (reg < MaxInput)
309 ccprintf(os, "%%i%d", reg - MaxLocal);
310 else if (reg < MaxMicroReg)
311 ccprintf(os, "%%u%d", reg - MaxInput);
312 // The fake int regs that are really control regs
313 else {
314 switch (reg - MaxMicroReg) {
315 case 1:
316 ccprintf(os, "%%y");
317 break;
318 case 2:
319 ccprintf(os, "%%ccr");
320 break;

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430 ccprintf(os, "%%fsr");
431 break;
432 default:
433 ccprintf(os, "%%ctrl%d", reg - Ctrl_Base_DepTag);
434 }
435 }
436 }
437
438 std::string
439 SparcStaticInst::generateDisassembly(Addr pc,
440 const SymbolTable *symtab) const
441 {
442 std::stringstream ss;
443
444 printMnemonic(ss, mnemonic);
445
446 // just print the first two source regs... if there's
447 // a third one, it's a read-modify-write dest (Rc),
448 // e.g. for CMOVxx
449 if (_numSrcRegs > 0)
450 printReg(ss, _srcRegIdx[0]);
451 if (_numSrcRegs > 1) {
452 ss << ",";
453 printReg(ss, _srcRegIdx[1]);
454 }
455
456 // just print the first dest... if there's a second one,
457 // it's generally implicit
458 if (_numDestRegs > 0) {
459 if (_numSrcRegs > 0)
460 ss << ",";
461 printReg(ss, _destRegIdx[0]);
462 }
463
464 return ss.str();
465 }
466
467 bool
468 passesFpCondition(uint32_t fcc, uint32_t condition)
469 {
470 bool u = (fcc == 3);
471 bool g = (fcc == 2);
472 bool l = (fcc == 1);
473 bool e = (fcc == 0);
474 switch (condition) {
475 case FAlways:
476 return 1;
477 case FNever:
478 return 0;
479 case FUnordered:
480 return u;
481 case FGreater:
482 return g;

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504 return u || l || e;
505 case FOrdered:
506 return e || l || g;
507 }
508 panic("Tried testing condition nonexistant "
509 "condition code %d", condition);
510 }
511
512 bool
513 passesCondition(uint32_t codes, uint32_t condition)
514 {
515 CondCodes condCodes;
516 condCodes.bits = 0;
517 condCodes.c = codes & 0x1 ? 1 : 0;
518 condCodes.v = codes & 0x2 ? 1 : 0;
519 condCodes.z = codes & 0x4 ? 1 : 0;
520 condCodes.n = codes & 0x8 ? 1 : 0;
521
522 switch (condition) {
523 case Always:
524 return true;
525 case Never:
526 return false;
527 case NotEqual:
528 return !condCodes.z;
529 case Equal:
530 return condCodes.z;

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559}};
560
561output exec {{
562 /// Check "FP enabled" machine status bit. Called when executing any FP
563 /// instruction in full-system mode.
564 /// @retval Full-system mode: NoFault if FP is enabled, FpDisabled
565 /// if not. Non-full-system mode: always returns NoFault.
566#if FULL_SYSTEM
567 inline Fault
568 checkFpEnableFault(%(CPU_exec_context)s *xc)
569 {
570 Fault fault = NoFault; // dummy... this ipr access should not fault
571 if (xc->readMiscReg(MISCREG_PSTATE) & PSTATE::pef &&
572 xc->readMiscReg(MISCREG_FPRS) & 0x4) {
573 return NoFault;
574 } else {
575 return new FpDisabled;
576 }
577 }
578#else
579 inline Fault
580 checkFpEnableFault(%(CPU_exec_context)s *xc)
581 {
582 return NoFault;
583 }
584#endif
585}};
586
587