isa.hh (8229:78bf55f23338) isa.hh (8747:017e5bbbb4e2)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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109 uint64_t dev_mondo_tail;
110 uint64_t res_error_head;
111 uint64_t res_error_tail;
112 uint64_t nres_error_head;
113 uint64_t nres_error_tail;
114
115 // These need to check the int_dis field and if 0 then
116 // set appropriate bit in softint and checkinterrutps on the cpu
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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109 uint64_t dev_mondo_tail;
110 uint64_t res_error_head;
111 uint64_t res_error_tail;
112 uint64_t nres_error_head;
113 uint64_t nres_error_tail;
114
115 // These need to check the int_dis field and if 0 then
116 // set appropriate bit in softint and checkinterrutps on the cpu
117#if FULL_SYSTEM
118 void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
119 MiscReg readFSReg(int miscReg, ThreadContext * tc);
120
121 // Update interrupt state on softint or pil change
122 void checkSoftInt(ThreadContext *tc);
123
124 /** Process a tick compare event and generate an interrupt on the cpu if
125 * appropriate. */

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133
134 typedef CpuEventWrapper<ISA,
135 &ISA::processSTickCompare> STickCompareEvent;
136 STickCompareEvent *sTickCompare;
137
138 typedef CpuEventWrapper<ISA,
139 &ISA::processHSTickCompare> HSTickCompareEvent;
140 HSTickCompareEvent *hSTickCompare;
117 void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
118 MiscReg readFSReg(int miscReg, ThreadContext * tc);
119
120 // Update interrupt state on softint or pil change
121 void checkSoftInt(ThreadContext *tc);
122
123 /** Process a tick compare event and generate an interrupt on the cpu if
124 * appropriate. */

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132
133 typedef CpuEventWrapper<ISA,
134 &ISA::processSTickCompare> STickCompareEvent;
135 STickCompareEvent *sTickCompare;
136
137 typedef CpuEventWrapper<ISA,
138 &ISA::processHSTickCompare> HSTickCompareEvent;
139 HSTickCompareEvent *hSTickCompare;
141#endif
142
143 static const int NumGlobalRegs = 8;
144 static const int NumWindowedRegs = 24;
145 static const int WindowOverlap = 8;
146
147 static const int TotalGlobals = (MaxGL + 1) * NumGlobalRegs;
148 static const int RegsPerWindow = NumWindowedRegs - WindowOverlap;
149 static const int TotalWindowed = NWindows * RegsPerWindow;

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200 int
201 flattenFloatIndex(int reg)
202 {
203 return reg;
204 }
205
206 ISA()
207 {
140
141 static const int NumGlobalRegs = 8;
142 static const int NumWindowedRegs = 24;
143 static const int WindowOverlap = 8;
144
145 static const int TotalGlobals = (MaxGL + 1) * NumGlobalRegs;
146 static const int RegsPerWindow = NumWindowedRegs - WindowOverlap;
147 static const int TotalWindowed = NWindows * RegsPerWindow;

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198 int
199 flattenFloatIndex(int reg)
200 {
201 return reg;
202 }
203
204 ISA()
205 {
208#if FULL_SYSTEM
209 tickCompare = NULL;
210 sTickCompare = NULL;
211 hSTickCompare = NULL;
206 tickCompare = NULL;
207 sTickCompare = NULL;
208 hSTickCompare = NULL;
212#endif
213
214 clear();
215 }
216};
217}
218
219#endif
209
210 clear();
211 }
212};
213}
214
215#endif