isa.hh (6331:d947798df4a1) isa.hh (6335:a08470cb53e5)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 17 unchanged lines hidden (view full) ---

26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_ISA_HH__
32#define __ARCH_SPARC_ISA_HH__
33
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 17 unchanged lines hidden (view full) ---

26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_ISA_HH__
32#define __ARCH_SPARC_ISA_HH__
33
34#include "arch/sparc/miscregfile.hh"
34#include "arch/sparc/registers.hh"
35#include "arch/sparc/types.hh"
35#include "arch/sparc/types.hh"
36#include "config/full_system.hh"
37#include "cpu/cpuevent.hh"
36
38
39#include <string>
40#include <ostream>
41
37class Checkpoint;
38class EventManager;
42class Checkpoint;
43class EventManager;
44class ThreadContext;
39
40namespace SparcISA
41{
42 class ISA
43 {
45
46namespace SparcISA
47{
48 class ISA
49 {
44 protected:
45 MiscRegFile miscRegFile;
50 private:
46
51
52 /* ASR Registers */
53 //uint64_t y; // Y (used in obsolete multiplication)
54 //uint8_t ccr; // Condition Code Register
55 uint8_t asi; // Address Space Identifier
56 uint64_t tick; // Hardware clock-tick counter
57 uint8_t fprs; // Floating-Point Register State
58 uint64_t gsr; // General Status Register
59 uint64_t softint;
60 uint64_t tick_cmpr; // Hardware tick compare registers
61 uint64_t stick; // Hardware clock-tick counter
62 uint64_t stick_cmpr; // Hardware tick compare registers
63
64
65 /* Privileged Registers */
66 uint64_t tpc[MaxTL]; // Trap Program Counter (value from
67 // previous trap level)
68 uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
69 // previous trap level)
70 uint64_t tstate[MaxTL]; // Trap State
71 uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
72 // on the previous level)
73 uint64_t tba; // Trap Base Address
74
75 uint16_t pstate; // Process State Register
76 uint8_t tl; // Trap Level
77 uint8_t pil; // Process Interrupt Register
78 uint8_t cwp; // Current Window Pointer
79 //uint8_t cansave; // Savable windows
80 //uint8_t canrestore; // Restorable windows
81 //uint8_t cleanwin; // Clean windows
82 //uint8_t otherwin; // Other windows
83 //uint8_t wstate; // Window State
84 uint8_t gl; // Global level register
85
86 /** Hyperprivileged Registers */
87 uint64_t hpstate; // Hyperprivileged State Register
88 uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
89 uint64_t hintp;
90 uint64_t htba; // Hyperprivileged Trap Base Address register
91 uint64_t hstick_cmpr; // Hardware tick compare registers
92
93 uint64_t strandStatusReg;// Per strand status register
94
95 /** Floating point misc registers. */
96 uint64_t fsr; // Floating-Point State Register
97
98 /** MMU Internal Registers */
99 uint16_t priContext;
100 uint16_t secContext;
101 uint16_t partId;
102 uint64_t lsuCtrlReg;
103
104 uint64_t scratchPad[8];
105
106 uint64_t cpu_mondo_head;
107 uint64_t cpu_mondo_tail;
108 uint64_t dev_mondo_head;
109 uint64_t dev_mondo_tail;
110 uint64_t res_error_head;
111 uint64_t res_error_tail;
112 uint64_t nres_error_head;
113 uint64_t nres_error_tail;
114
115 // These need to check the int_dis field and if 0 then
116 // set appropriate bit in softint and checkinterrutps on the cpu
117#if FULL_SYSTEM
118 void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
119 MiscReg readFSReg(int miscReg, ThreadContext * tc);
120
121 // Update interrupt state on softint or pil change
122 void checkSoftInt(ThreadContext *tc);
123
124 /** Process a tick compare event and generate an interrupt on the cpu if
125 * appropriate. */
126 void processTickCompare(ThreadContext *tc);
127 void processSTickCompare(ThreadContext *tc);
128 void processHSTickCompare(ThreadContext *tc);
129
130 typedef CpuEventWrapper<ISA,
131 &ISA::processTickCompare> TickCompareEvent;
132 TickCompareEvent *tickCompare;
133
134 typedef CpuEventWrapper<ISA,
135 &ISA::processSTickCompare> STickCompareEvent;
136 STickCompareEvent *sTickCompare;
137
138 typedef CpuEventWrapper<ISA,
139 &ISA::processHSTickCompare> HSTickCompareEvent;
140 HSTickCompareEvent *hSTickCompare;
141#endif
47 public:
142 public:
143
48 void clear();
49
144 void clear();
145
146 void serialize(EventManager *em, std::ostream & os);
147
148 void unserialize(EventManager *em, Checkpoint *cp,
149 const std::string & section);
150
151 protected:
152
153 bool isHyperPriv() { return (hpstate & (1 << 2)); }
154 bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); }
155 bool isNonPriv() { return !isPriv(); }
156
157 public:
158
50 MiscReg readMiscRegNoEffect(int miscReg);
51 MiscReg readMiscReg(int miscReg, ThreadContext *tc);
52
53 void setMiscRegNoEffect(int miscReg, const MiscReg val);
54 void setMiscReg(int miscReg, const MiscReg val,
55 ThreadContext *tc);
56
57 int flattenIntIndex(int reg);
58
59 int
60 flattenFloatIndex(int reg)
61 {
62 return reg;
63 }
64
159 MiscReg readMiscRegNoEffect(int miscReg);
160 MiscReg readMiscReg(int miscReg, ThreadContext *tc);
161
162 void setMiscRegNoEffect(int miscReg, const MiscReg val);
163 void setMiscReg(int miscReg, const MiscReg val,
164 ThreadContext *tc);
165
166 int flattenIntIndex(int reg);
167
168 int
169 flattenFloatIndex(int reg)
170 {
171 return reg;
172 }
173
65 void serialize(EventManager *em, std::ostream &os);
66 void unserialize(EventManager *em, Checkpoint *cp,
67 const std::string &section);
68
69 ISA()
70 {
71 clear();
72 }
73 };
74}
75
76#endif
174 ISA()
175 {
176 clear();
177 }
178 };
179}
180
181#endif