isa.hh (12109:f29e9c5418aa) | isa.hh (13582:989577bf6abc) |
---|---|
1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 102 unchanged lines hidden (view full) --- 111 uint64_t dev_mondo_tail; 112 uint64_t res_error_head; 113 uint64_t res_error_tail; 114 uint64_t nres_error_head; 115 uint64_t nres_error_tail; 116 117 // These need to check the int_dis field and if 0 then 118 // set appropriate bit in softint and checkinterrutps on the cpu | 1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 102 unchanged lines hidden (view full) --- 111 uint64_t dev_mondo_tail; 112 uint64_t res_error_head; 113 uint64_t res_error_tail; 114 uint64_t nres_error_head; 115 uint64_t nres_error_tail; 116 117 // These need to check the int_dis field and if 0 then 118 // set appropriate bit in softint and checkinterrutps on the cpu |
119 void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc); | 119 void setFSReg(int miscReg, MiscReg val, ThreadContext *tc); |
120 MiscReg readFSReg(int miscReg, ThreadContext * tc); 121 122 // Update interrupt state on softint or pil change 123 void checkSoftInt(ThreadContext *tc); 124 125 /** Process a tick compare event and generate an interrupt on the cpu if 126 * appropriate. */ 127 void processTickCompare(ThreadContext *tc); --- 53 unchanged lines hidden (view full) --- 181 bool isPriv() { return hpstate.hpriv || pstate.priv; } 182 bool isNonPriv() { return !isPriv(); } 183 184 public: 185 186 MiscReg readMiscRegNoEffect(int miscReg) const; 187 MiscReg readMiscReg(int miscReg, ThreadContext *tc); 188 | 120 MiscReg readFSReg(int miscReg, ThreadContext * tc); 121 122 // Update interrupt state on softint or pil change 123 void checkSoftInt(ThreadContext *tc); 124 125 /** Process a tick compare event and generate an interrupt on the cpu if 126 * appropriate. */ 127 void processTickCompare(ThreadContext *tc); --- 53 unchanged lines hidden (view full) --- 181 bool isPriv() { return hpstate.hpriv || pstate.priv; } 182 bool isNonPriv() { return !isPriv(); } 183 184 public: 185 186 MiscReg readMiscRegNoEffect(int miscReg) const; 187 MiscReg readMiscReg(int miscReg, ThreadContext *tc); 188 |
189 void setMiscRegNoEffect(int miscReg, const MiscReg val); 190 void setMiscReg(int miscReg, const MiscReg val, 191 ThreadContext *tc); | 189 void setMiscRegNoEffect(int miscReg, MiscReg val); 190 void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc); |
192 193 RegId 194 flattenRegId(const RegId& regId) const 195 { 196 switch (regId.classValue()) { 197 case IntRegClass: 198 return RegId(IntRegClass, flattenIntIndex(regId.index())); 199 case FloatRegClass: --- 60 unchanged lines hidden --- | 191 192 RegId 193 flattenRegId(const RegId& regId) const 194 { 195 switch (regId.classValue()) { 196 case IntRegClass: 197 return RegId(IntRegClass, flattenIntIndex(regId.index())); 198 case FloatRegClass: --- 60 unchanged lines hidden --- |