isa.hh (11168:f98eb2da15a4) isa.hh (12106:7784fac1b159)
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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32#define __ARCH_SPARC_ISA_HH__
33
34#include <ostream>
35#include <string>
36
37#include "arch/sparc/registers.hh"
38#include "arch/sparc/types.hh"
39#include "cpu/cpuevent.hh"
1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 23 unchanged lines hidden (view full) ---

32#define __ARCH_SPARC_ISA_HH__
33
34#include <ostream>
35#include <string>
36
37#include "arch/sparc/registers.hh"
38#include "arch/sparc/types.hh"
39#include "cpu/cpuevent.hh"
40#include "cpu/reg_class.hh"
40#include "sim/sim_object.hh"
41
42class Checkpoint;
43class EventManager;
44struct SparcISAParams;
45class ThreadContext;
46
47namespace SparcISA

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184
185 MiscReg readMiscRegNoEffect(int miscReg) const;
186 MiscReg readMiscReg(int miscReg, ThreadContext *tc);
187
188 void setMiscRegNoEffect(int miscReg, const MiscReg val);
189 void setMiscReg(int miscReg, const MiscReg val,
190 ThreadContext *tc);
191
41#include "sim/sim_object.hh"
42
43class Checkpoint;
44class EventManager;
45struct SparcISAParams;
46class ThreadContext;
47
48namespace SparcISA

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185
186 MiscReg readMiscRegNoEffect(int miscReg) const;
187 MiscReg readMiscReg(int miscReg, ThreadContext *tc);
188
189 void setMiscRegNoEffect(int miscReg, const MiscReg val);
190 void setMiscReg(int miscReg, const MiscReg val,
191 ThreadContext *tc);
192
193 RegId
194 flattenRegId(const RegId& regId) const
195 {
196 switch (regId.classValue()) {
197 case IntRegClass:
198 return RegId(IntRegClass, flattenIntIndex(regId.index()));
199 case FloatRegClass:
200 return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
201 case CCRegClass:
202 return RegId(CCRegClass, flattenCCIndex(regId.index()));
203 case MiscRegClass:
204 return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
205 }
206 return regId;
207 }
208
192 int
193 flattenIntIndex(int reg) const
194 {
195 assert(reg < TotalInstIntRegs);
196 RegIndex flatIndex = intRegMap[reg];
197 assert(flatIndex < NumIntRegs);
198 return flatIndex;
199 }

--- 29 unchanged lines hidden --- 		209 int
210 flattenIntIndex(int reg) const
211 {
212 assert(reg < TotalInstIntRegs);
213 RegIndex flatIndex = intRegMap[reg];
214 assert(flatIndex < NumIntRegs);
215 return flatIndex;
216 }

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