1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#ifndef __ARCH_SPARC_ISA_HH__ 32#define __ARCH_SPARC_ISA_HH__ 33 34#include "arch/sparc/registers.hh" 35#include "arch/sparc/types.hh" 36#include "config/full_system.hh" 37#include "cpu/cpuevent.hh" 38 39#include <string> 40#include <ostream> 41 42class Checkpoint; 43class EventManager; 44class ThreadContext; 45 46namespace SparcISA 47{
|
48 class ISA
49 {
50 private:
|
48class ISA 49{ 50 private: |
51
|
52 /* ASR Registers */
53 //uint64_t y; // Y (used in obsolete multiplication)
54 //uint8_t ccr; // Condition Code Register
55 uint8_t asi; // Address Space Identifier
56 uint64_t tick; // Hardware clock-tick counter
57 uint8_t fprs; // Floating-Point Register State
58 uint64_t gsr; // General Status Register
59 uint64_t softint;
60 uint64_t tick_cmpr; // Hardware tick compare registers
61 uint64_t stick; // Hardware clock-tick counter
62 uint64_t stick_cmpr; // Hardware tick compare registers
|
52 /* ASR Registers */ 53 // uint64_t y; // Y (used in obsolete multiplication) 54 // uint8_t ccr; // Condition Code Register 55 uint8_t asi; // Address Space Identifier 56 uint64_t tick; // Hardware clock-tick counter 57 uint8_t fprs; // Floating-Point Register State 58 uint64_t gsr; // General Status Register 59 uint64_t softint; 60 uint64_t tick_cmpr; // Hardware tick compare registers 61 uint64_t stick; // Hardware clock-tick counter 62 uint64_t stick_cmpr; // Hardware tick compare registers |
63 64
|
65 /* Privileged Registers */
66 uint64_t tpc[MaxTL]; // Trap Program Counter (value from
67 // previous trap level)
68 uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
69 // previous trap level)
70 uint64_t tstate[MaxTL]; // Trap State
71 uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
72 // on the previous level)
73 uint64_t tba; // Trap Base Address
|
65 /* Privileged Registers */ 66 uint64_t tpc[MaxTL]; // Trap Program Counter (value from 67 // previous trap level) 68 uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from 69 // previous trap level) 70 uint64_t tstate[MaxTL]; // Trap State 71 uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured 72 // on the previous level) 73 uint64_t tba; // Trap Base Address |
74
|
75 uint16_t pstate; // Process State Register
76 uint8_t tl; // Trap Level
77 uint8_t pil; // Process Interrupt Register
78 uint8_t cwp; // Current Window Pointer
79 //uint8_t cansave; // Savable windows
80 //uint8_t canrestore; // Restorable windows
81 //uint8_t cleanwin; // Clean windows
82 //uint8_t otherwin; // Other windows
83 //uint8_t wstate; // Window State
84 uint8_t gl; // Global level register
|
75 uint16_t pstate; // Process State Register 76 uint8_t tl; // Trap Level 77 uint8_t pil; // Process Interrupt Register 78 uint8_t cwp; // Current Window Pointer 79 // uint8_t cansave; // Savable windows 80 // uint8_t canrestore; // Restorable windows 81 // uint8_t cleanwin; // Clean windows 82 // uint8_t otherwin; // Other windows 83 // uint8_t wstate; // Window State 84 uint8_t gl; // Global level register |
85
|
86 /** Hyperprivileged Registers */
87 uint64_t hpstate; // Hyperprivileged State Register
88 uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
89 uint64_t hintp;
90 uint64_t htba; // Hyperprivileged Trap Base Address register
91 uint64_t hstick_cmpr; // Hardware tick compare registers
|
86 /** Hyperprivileged Registers */ 87 uint64_t hpstate; // Hyperprivileged State Register 88 uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register 89 uint64_t hintp; 90 uint64_t htba; // Hyperprivileged Trap Base Address register 91 uint64_t hstick_cmpr; // Hardware tick compare registers |
92
|
93 uint64_t strandStatusReg;// Per strand status register
|
93 uint64_t strandStatusReg;// Per strand status register |
94
|
95 /** Floating point misc registers. */
96 uint64_t fsr; // Floating-Point State Register
|
95 /** Floating point misc registers. */ 96 uint64_t fsr; // Floating-Point State Register |
97
|
98 /** MMU Internal Registers */
99 uint16_t priContext;
100 uint16_t secContext;
101 uint16_t partId;
102 uint64_t lsuCtrlReg;
|
98 /** MMU Internal Registers */ 99 uint16_t priContext; 100 uint16_t secContext; 101 uint16_t partId; 102 uint64_t lsuCtrlReg; |
103
|
104 uint64_t scratchPad[8];
|
104 uint64_t scratchPad[8]; |
105
|
106 uint64_t cpu_mondo_head;
107 uint64_t cpu_mondo_tail;
108 uint64_t dev_mondo_head;
109 uint64_t dev_mondo_tail;
110 uint64_t res_error_head;
111 uint64_t res_error_tail;
112 uint64_t nres_error_head;
113 uint64_t nres_error_tail;
|
106 uint64_t cpu_mondo_head; 107 uint64_t cpu_mondo_tail; 108 uint64_t dev_mondo_head; 109 uint64_t dev_mondo_tail; 110 uint64_t res_error_head; 111 uint64_t res_error_tail; 112 uint64_t nres_error_head; 113 uint64_t nres_error_tail; |
114
|
115 // These need to check the int_dis field and if 0 then
116 // set appropriate bit in softint and checkinterrutps on the cpu
|
115 // These need to check the int_dis field and if 0 then 116 // set appropriate bit in softint and checkinterrutps on the cpu |
117#if FULL_SYSTEM
|
118 void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
119 MiscReg readFSReg(int miscReg, ThreadContext * tc);
|
118 void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc); 119 MiscReg readFSReg(int miscReg, ThreadContext * tc); |
120
|
121 // Update interrupt state on softint or pil change
122 void checkSoftInt(ThreadContext *tc);
|
121 // Update interrupt state on softint or pil change 122 void checkSoftInt(ThreadContext *tc); |
123
|
124 /** Process a tick compare event and generate an interrupt on the cpu if
125 * appropriate. */
126 void processTickCompare(ThreadContext *tc);
127 void processSTickCompare(ThreadContext *tc);
128 void processHSTickCompare(ThreadContext *tc);
|
124 /** Process a tick compare event and generate an interrupt on the cpu if 125 * appropriate. */ 126 void processTickCompare(ThreadContext *tc); 127 void processSTickCompare(ThreadContext *tc); 128 void processHSTickCompare(ThreadContext *tc); |
129
|
130 typedef CpuEventWrapper<ISA,
131 &ISA::processTickCompare> TickCompareEvent;
132 TickCompareEvent *tickCompare;
|
130 typedef CpuEventWrapper131 &ISA::processTickCompare> TickCompareEvent; 132 TickCompareEvent *tickCompare; |
133
|
134 typedef CpuEventWrapper<ISA,
135 &ISA::processSTickCompare> STickCompareEvent;
136 STickCompareEvent *sTickCompare;
|
134 typedef CpuEventWrapper135 &ISA::processSTickCompare> STickCompareEvent; 136 STickCompareEvent *sTickCompare; |
137
|
138 typedef CpuEventWrapper<ISA,
139 &ISA::processHSTickCompare> HSTickCompareEvent;
140 HSTickCompareEvent *hSTickCompare;
|
138 typedef CpuEventWrapper139 &ISA::processHSTickCompare> HSTickCompareEvent; 140 HSTickCompareEvent *hSTickCompare; |
141#endif 142
|
143 static const int NumGlobalRegs = 8;
144 static const int NumWindowedRegs = 24;
145 static const int WindowOverlap = 8;
|
143 static const int NumGlobalRegs = 8; 144 static const int NumWindowedRegs = 24; 145 static const int WindowOverlap = 8; |
146
|
147 static const int TotalGlobals = (MaxGL + 1) * NumGlobalRegs;
148 static const int RegsPerWindow = NumWindowedRegs - WindowOverlap;
149 static const int TotalWindowed = NWindows * RegsPerWindow;
|
147 static const int TotalGlobals = (MaxGL + 1) * NumGlobalRegs; 148 static const int RegsPerWindow = NumWindowedRegs - WindowOverlap; 149 static const int TotalWindowed = NWindows * RegsPerWindow; |
150
|
151 enum InstIntRegOffsets {
152 CurrentGlobalsOffset = 0,
153 CurrentWindowOffset = CurrentGlobalsOffset + NumGlobalRegs,
154 MicroIntOffset = CurrentWindowOffset + NumWindowedRegs,
155 NextGlobalsOffset = MicroIntOffset + NumMicroIntRegs,
156 NextWindowOffset = NextGlobalsOffset + NumGlobalRegs,
157 PreviousGlobalsOffset = NextWindowOffset + NumWindowedRegs,
158 PreviousWindowOffset = PreviousGlobalsOffset + NumGlobalRegs,
159 TotalInstIntRegs = PreviousWindowOffset + NumWindowedRegs
160 };
|
151 enum InstIntRegOffsets { 152 CurrentGlobalsOffset = 0, 153 CurrentWindowOffset = CurrentGlobalsOffset + NumGlobalRegs, 154 MicroIntOffset = CurrentWindowOffset + NumWindowedRegs, 155 NextGlobalsOffset = MicroIntOffset + NumMicroIntRegs, 156 NextWindowOffset = NextGlobalsOffset + NumGlobalRegs, 157 PreviousGlobalsOffset = NextWindowOffset + NumWindowedRegs, 158 PreviousWindowOffset = PreviousGlobalsOffset + NumGlobalRegs, 159 TotalInstIntRegs = PreviousWindowOffset + NumWindowedRegs 160 }; |
161
|
162 RegIndex intRegMap[TotalInstIntRegs];
163 void installWindow(int cwp, int offset);
164 void installGlobals(int gl, int offset);
165 void reloadRegMap();
|
162 RegIndex intRegMap[TotalInstIntRegs]; 163 void installWindow(int cwp, int offset); 164 void installGlobals(int gl, int offset); 165 void reloadRegMap(); |
166
|
167 public:
|
167 public: |
168
|
169 void clear();
|
169 void clear(); |
170
|
171 void serialize(EventManager *em, std::ostream & os);
|
171 void serialize(EventManager *em, std::ostream & os); |
172
|
173 void unserialize(EventManager *em, Checkpoint *cp,
174 const std::string & section);
|
173 void unserialize(EventManager *em, Checkpoint *cp, 174 const std::string & section); |
175
|
176 protected:
|
176 protected: |
177
|
178 bool isHyperPriv() { return (hpstate & (1 << 2)); }
179 bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); }
180 bool isNonPriv() { return !isPriv(); }
|
178 bool isHyperPriv() { return (hpstate & (1 << 2)); } 179 bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); } 180 bool isNonPriv() { return !isPriv(); } |
181
|
182 public:
|
182 public: |
183
|
184 MiscReg readMiscRegNoEffect(int miscReg);
185 MiscReg readMiscReg(int miscReg, ThreadContext *tc);
|
184 MiscReg readMiscRegNoEffect(int miscReg); 185 MiscReg readMiscReg(int miscReg, ThreadContext *tc); |
186
|
187 void setMiscRegNoEffect(int miscReg, const MiscReg val);
188 void setMiscReg(int miscReg, const MiscReg val,
189 ThreadContext *tc);
|
187 void setMiscRegNoEffect(int miscReg, const MiscReg val); 188 void setMiscReg(int miscReg, const MiscReg val, 189 ThreadContext *tc); |
190
|
191 int
192 flattenIntIndex(int reg)
193 {
194 assert(reg < TotalInstIntRegs);
195 RegIndex flatIndex = intRegMap[reg];
196 assert(flatIndex < NumIntRegs);
197 return flatIndex;
198 }
|
191 int 192 flattenIntIndex(int reg) 193 { 194 assert(reg < TotalInstIntRegs); 195 RegIndex flatIndex = intRegMap[reg]; 196 assert(flatIndex < NumIntRegs); 197 return flatIndex; 198 } |
199
|
200 int
201 flattenFloatIndex(int reg)
202 {
203 return reg;
204 }
|
200 int 201 flattenFloatIndex(int reg) 202 { 203 return reg; 204 } |
205
|
206 ISA()
207 {
|
206 ISA() 207 { |
208#if FULL_SYSTEM
|
209 tickCompare = NULL;
210 sTickCompare = NULL;
211 hSTickCompare = NULL;
|
209 tickCompare = NULL; 210 sTickCompare = NULL; 211 hSTickCompare = NULL; |
212#endif 213
|
214 clear();
215 }
216 };
|
214 clear(); 215 } 216}; |
217} 218 219#endif
|