1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 23 unchanged lines hidden (view full) --- 32#define __ARCH_SPARC_ISA_HH__ 33 34#include <ostream> 35#include <string> 36 37#include "arch/sparc/registers.hh" 38#include "arch/sparc/types.hh" 39#include "cpu/cpuevent.hh" |
40#include "sim/sim_object.hh" |
41 42class Checkpoint; 43class EventManager; |
44struct SparcISAParams; |
45class ThreadContext; 46 47namespace SparcISA 48{ |
49class ISA : public SimObject |
50{ 51 private: 52 53 /* ASR Registers */ 54 // uint64_t y; // Y (used in obsolete multiplication) 55 // uint8_t ccr; // Condition Code Register 56 uint8_t asi; // Address Space Identifier 57 uint64_t tick; // Hardware clock-tick counter --- 139 unchanged lines hidden (view full) --- 197 } 198 199 int 200 flattenFloatIndex(int reg) 201 { 202 return reg; 203 } 204 |
205 typedef SparcISAParams Params; 206 const Params *params() const; |
207 |
208 ISA(Params *p); |
209}; 210} 211 212#endif |