1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 23 unchanged lines hidden (view full) --- 32#define __ARCH_SPARC_ISA_HH__ 33 34#include <ostream> 35#include <string> 36 37#include "arch/sparc/registers.hh" 38#include "arch/sparc/types.hh" 39#include "cpu/cpuevent.hh" |
40#include "cpu/reg_class.hh" |
41#include "sim/sim_object.hh" 42 43class Checkpoint; 44class EventManager; 45struct SparcISAParams; 46class ThreadContext; 47 48namespace SparcISA --- 136 unchanged lines hidden (view full) --- 185 186 MiscReg readMiscRegNoEffect(int miscReg) const; 187 MiscReg readMiscReg(int miscReg, ThreadContext *tc); 188 189 void setMiscRegNoEffect(int miscReg, const MiscReg val); 190 void setMiscReg(int miscReg, const MiscReg val, 191 ThreadContext *tc); 192 |
193 RegId 194 flattenRegId(const RegId& regId) const 195 { 196 switch (regId.classValue()) { 197 case IntRegClass: 198 return RegId(IntRegClass, flattenIntIndex(regId.index())); 199 case FloatRegClass: 200 return RegId(FloatRegClass, flattenFloatIndex(regId.index())); 201 case CCRegClass: 202 return RegId(CCRegClass, flattenCCIndex(regId.index())); 203 case MiscRegClass: 204 return RegId(MiscRegClass, flattenMiscIndex(regId.index())); 205 } 206 return regId; 207 } 208 |
209 int 210 flattenIntIndex(int reg) const 211 { 212 assert(reg < TotalInstIntRegs); 213 RegIndex flatIndex = intRegMap[reg]; 214 assert(flatIndex < NumIntRegs); 215 return flatIndex; 216 } --- 29 unchanged lines hidden --- |