48,50c48,50
< class ISA
< {
< private:
---
> class ISA
> {
> private:
52,62c52,62
< /* ASR Registers */
< //uint64_t y; // Y (used in obsolete multiplication)
< //uint8_t ccr; // Condition Code Register
< uint8_t asi; // Address Space Identifier
< uint64_t tick; // Hardware clock-tick counter
< uint8_t fprs; // Floating-Point Register State
< uint64_t gsr; // General Status Register
< uint64_t softint;
< uint64_t tick_cmpr; // Hardware tick compare registers
< uint64_t stick; // Hardware clock-tick counter
< uint64_t stick_cmpr; // Hardware tick compare registers
---
> /* ASR Registers */
> // uint64_t y; // Y (used in obsolete multiplication)
> // uint8_t ccr; // Condition Code Register
> uint8_t asi; // Address Space Identifier
> uint64_t tick; // Hardware clock-tick counter
> uint8_t fprs; // Floating-Point Register State
> uint64_t gsr; // General Status Register
> uint64_t softint;
> uint64_t tick_cmpr; // Hardware tick compare registers
> uint64_t stick; // Hardware clock-tick counter
> uint64_t stick_cmpr; // Hardware tick compare registers
65,73c65,73
< /* Privileged Registers */
< uint64_t tpc[MaxTL]; // Trap Program Counter (value from
< // previous trap level)
< uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
< // previous trap level)
< uint64_t tstate[MaxTL]; // Trap State
< uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
< // on the previous level)
< uint64_t tba; // Trap Base Address
---
> /* Privileged Registers */
> uint64_t tpc[MaxTL]; // Trap Program Counter (value from
> // previous trap level)
> uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
> // previous trap level)
> uint64_t tstate[MaxTL]; // Trap State
> uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
> // on the previous level)
> uint64_t tba; // Trap Base Address
75,84c75,84
< uint16_t pstate; // Process State Register
< uint8_t tl; // Trap Level
< uint8_t pil; // Process Interrupt Register
< uint8_t cwp; // Current Window Pointer
< //uint8_t cansave; // Savable windows
< //uint8_t canrestore; // Restorable windows
< //uint8_t cleanwin; // Clean windows
< //uint8_t otherwin; // Other windows
< //uint8_t wstate; // Window State
< uint8_t gl; // Global level register
---
> uint16_t pstate; // Process State Register
> uint8_t tl; // Trap Level
> uint8_t pil; // Process Interrupt Register
> uint8_t cwp; // Current Window Pointer
> // uint8_t cansave; // Savable windows
> // uint8_t canrestore; // Restorable windows
> // uint8_t cleanwin; // Clean windows
> // uint8_t otherwin; // Other windows
> // uint8_t wstate; // Window State
> uint8_t gl; // Global level register
86,91c86,91
< /** Hyperprivileged Registers */
< uint64_t hpstate; // Hyperprivileged State Register
< uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
< uint64_t hintp;
< uint64_t htba; // Hyperprivileged Trap Base Address register
< uint64_t hstick_cmpr; // Hardware tick compare registers
---
> /** Hyperprivileged Registers */
> uint64_t hpstate; // Hyperprivileged State Register
> uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
> uint64_t hintp;
> uint64_t htba; // Hyperprivileged Trap Base Address register
> uint64_t hstick_cmpr; // Hardware tick compare registers
93c93
< uint64_t strandStatusReg;// Per strand status register
---
> uint64_t strandStatusReg;// Per strand status register
95,96c95,96
< /** Floating point misc registers. */
< uint64_t fsr; // Floating-Point State Register
---
> /** Floating point misc registers. */
> uint64_t fsr; // Floating-Point State Register
98,102c98,102
< /** MMU Internal Registers */
< uint16_t priContext;
< uint16_t secContext;
< uint16_t partId;
< uint64_t lsuCtrlReg;
---
> /** MMU Internal Registers */
> uint16_t priContext;
> uint16_t secContext;
> uint16_t partId;
> uint64_t lsuCtrlReg;
104c104
< uint64_t scratchPad[8];
---
> uint64_t scratchPad[8];
106,113c106,113
< uint64_t cpu_mondo_head;
< uint64_t cpu_mondo_tail;
< uint64_t dev_mondo_head;
< uint64_t dev_mondo_tail;
< uint64_t res_error_head;
< uint64_t res_error_tail;
< uint64_t nres_error_head;
< uint64_t nres_error_tail;
---
> uint64_t cpu_mondo_head;
> uint64_t cpu_mondo_tail;
> uint64_t dev_mondo_head;
> uint64_t dev_mondo_tail;
> uint64_t res_error_head;
> uint64_t res_error_tail;
> uint64_t nres_error_head;
> uint64_t nres_error_tail;
115,116c115,116
< // These need to check the int_dis field and if 0 then
< // set appropriate bit in softint and checkinterrutps on the cpu
---
> // These need to check the int_dis field and if 0 then
> // set appropriate bit in softint and checkinterrutps on the cpu
118,119c118,119
< void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
< MiscReg readFSReg(int miscReg, ThreadContext * tc);
---
> void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
> MiscReg readFSReg(int miscReg, ThreadContext * tc);
121,122c121,122
< // Update interrupt state on softint or pil change
< void checkSoftInt(ThreadContext *tc);
---
> // Update interrupt state on softint or pil change
> void checkSoftInt(ThreadContext *tc);
124,128c124,128
< /** Process a tick compare event and generate an interrupt on the cpu if
< * appropriate. */
< void processTickCompare(ThreadContext *tc);
< void processSTickCompare(ThreadContext *tc);
< void processHSTickCompare(ThreadContext *tc);
---
> /** Process a tick compare event and generate an interrupt on the cpu if
> * appropriate. */
> void processTickCompare(ThreadContext *tc);
> void processSTickCompare(ThreadContext *tc);
> void processHSTickCompare(ThreadContext *tc);
130,132c130,132
< typedef CpuEventWrapper<ISA,
< &ISA::processTickCompare> TickCompareEvent;
< TickCompareEvent *tickCompare;
---
> typedef CpuEventWrapper<ISA,
> &ISA::processTickCompare> TickCompareEvent;
> TickCompareEvent *tickCompare;
134,136c134,136
< typedef CpuEventWrapper<ISA,
< &ISA::processSTickCompare> STickCompareEvent;
< STickCompareEvent *sTickCompare;
---
> typedef CpuEventWrapper<ISA,
> &ISA::processSTickCompare> STickCompareEvent;
> STickCompareEvent *sTickCompare;
138,140c138,140
< typedef CpuEventWrapper<ISA,
< &ISA::processHSTickCompare> HSTickCompareEvent;
< HSTickCompareEvent *hSTickCompare;
---
> typedef CpuEventWrapper<ISA,
> &ISA::processHSTickCompare> HSTickCompareEvent;
> HSTickCompareEvent *hSTickCompare;
143,145c143,145
< static const int NumGlobalRegs = 8;
< static const int NumWindowedRegs = 24;
< static const int WindowOverlap = 8;
---
> static const int NumGlobalRegs = 8;
> static const int NumWindowedRegs = 24;
> static const int WindowOverlap = 8;
147,149c147,149
< static const int TotalGlobals = (MaxGL + 1) * NumGlobalRegs;
< static const int RegsPerWindow = NumWindowedRegs - WindowOverlap;
< static const int TotalWindowed = NWindows * RegsPerWindow;
---
> static const int TotalGlobals = (MaxGL + 1) * NumGlobalRegs;
> static const int RegsPerWindow = NumWindowedRegs - WindowOverlap;
> static const int TotalWindowed = NWindows * RegsPerWindow;
151,160c151,160
< enum InstIntRegOffsets {
< CurrentGlobalsOffset = 0,
< CurrentWindowOffset = CurrentGlobalsOffset + NumGlobalRegs,
< MicroIntOffset = CurrentWindowOffset + NumWindowedRegs,
< NextGlobalsOffset = MicroIntOffset + NumMicroIntRegs,
< NextWindowOffset = NextGlobalsOffset + NumGlobalRegs,
< PreviousGlobalsOffset = NextWindowOffset + NumWindowedRegs,
< PreviousWindowOffset = PreviousGlobalsOffset + NumGlobalRegs,
< TotalInstIntRegs = PreviousWindowOffset + NumWindowedRegs
< };
---
> enum InstIntRegOffsets {
> CurrentGlobalsOffset = 0,
> CurrentWindowOffset = CurrentGlobalsOffset + NumGlobalRegs,
> MicroIntOffset = CurrentWindowOffset + NumWindowedRegs,
> NextGlobalsOffset = MicroIntOffset + NumMicroIntRegs,
> NextWindowOffset = NextGlobalsOffset + NumGlobalRegs,
> PreviousGlobalsOffset = NextWindowOffset + NumWindowedRegs,
> PreviousWindowOffset = PreviousGlobalsOffset + NumGlobalRegs,
> TotalInstIntRegs = PreviousWindowOffset + NumWindowedRegs
> };
162,165c162,165
< RegIndex intRegMap[TotalInstIntRegs];
< void installWindow(int cwp, int offset);
< void installGlobals(int gl, int offset);
< void reloadRegMap();
---
> RegIndex intRegMap[TotalInstIntRegs];
> void installWindow(int cwp, int offset);
> void installGlobals(int gl, int offset);
> void reloadRegMap();
167c167
< public:
---
> public:
169c169
< void clear();
---
> void clear();
171c171
< void serialize(EventManager *em, std::ostream & os);
---
> void serialize(EventManager *em, std::ostream & os);
173,174c173,174
< void unserialize(EventManager *em, Checkpoint *cp,
< const std::string & section);
---
> void unserialize(EventManager *em, Checkpoint *cp,
> const std::string & section);
176c176
< protected:
---
> protected:
178,180c178,180
< bool isHyperPriv() { return (hpstate & (1 << 2)); }
< bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); }
< bool isNonPriv() { return !isPriv(); }
---
> bool isHyperPriv() { return (hpstate & (1 << 2)); }
> bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); }
> bool isNonPriv() { return !isPriv(); }
182c182
< public:
---
> public:
184,185c184,185
< MiscReg readMiscRegNoEffect(int miscReg);
< MiscReg readMiscReg(int miscReg, ThreadContext *tc);
---
> MiscReg readMiscRegNoEffect(int miscReg);
> MiscReg readMiscReg(int miscReg, ThreadContext *tc);
187,189c187,189
< void setMiscRegNoEffect(int miscReg, const MiscReg val);
< void setMiscReg(int miscReg, const MiscReg val,
< ThreadContext *tc);
---
> void setMiscRegNoEffect(int miscReg, const MiscReg val);
> void setMiscReg(int miscReg, const MiscReg val,
> ThreadContext *tc);
191,198c191,198
< int
< flattenIntIndex(int reg)
< {
< assert(reg < TotalInstIntRegs);
< RegIndex flatIndex = intRegMap[reg];
< assert(flatIndex < NumIntRegs);
< return flatIndex;
< }
---
> int
> flattenIntIndex(int reg)
> {
> assert(reg < TotalInstIntRegs);
> RegIndex flatIndex = intRegMap[reg];
> assert(flatIndex < NumIntRegs);
> return flatIndex;
> }
200,204c200,204
< int
< flattenFloatIndex(int reg)
< {
< return reg;
< }
---
> int
> flattenFloatIndex(int reg)
> {
> return reg;
> }
206,207c206,207
< ISA()
< {
---
> ISA()
> {
209,211c209,211
< tickCompare = NULL;
< sTickCompare = NULL;
< hSTickCompare = NULL;
---
> tickCompare = NULL;
> sTickCompare = NULL;
> hSTickCompare = NULL;
214,216c214,216
< clear();
< }
< };
---
> clear();
> }
> };
< class ISA
< {
< private:
---
> class ISA
> {
> private:
52,62c52,62
< /* ASR Registers */
< //uint64_t y; // Y (used in obsolete multiplication)
< //uint8_t ccr; // Condition Code Register
< uint8_t asi; // Address Space Identifier
< uint64_t tick; // Hardware clock-tick counter
< uint8_t fprs; // Floating-Point Register State
< uint64_t gsr; // General Status Register
< uint64_t softint;
< uint64_t tick_cmpr; // Hardware tick compare registers
< uint64_t stick; // Hardware clock-tick counter
< uint64_t stick_cmpr; // Hardware tick compare registers
---
> /* ASR Registers */
> // uint64_t y; // Y (used in obsolete multiplication)
> // uint8_t ccr; // Condition Code Register
> uint8_t asi; // Address Space Identifier
> uint64_t tick; // Hardware clock-tick counter
> uint8_t fprs; // Floating-Point Register State
> uint64_t gsr; // General Status Register
> uint64_t softint;
> uint64_t tick_cmpr; // Hardware tick compare registers
> uint64_t stick; // Hardware clock-tick counter
> uint64_t stick_cmpr; // Hardware tick compare registers
65,73c65,73
< /* Privileged Registers */
< uint64_t tpc[MaxTL]; // Trap Program Counter (value from
< // previous trap level)
< uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
< // previous trap level)
< uint64_t tstate[MaxTL]; // Trap State
< uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
< // on the previous level)
< uint64_t tba; // Trap Base Address
---
> /* Privileged Registers */
> uint64_t tpc[MaxTL]; // Trap Program Counter (value from
> // previous trap level)
> uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
> // previous trap level)
> uint64_t tstate[MaxTL]; // Trap State
> uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
> // on the previous level)
> uint64_t tba; // Trap Base Address
75,84c75,84
< uint16_t pstate; // Process State Register
< uint8_t tl; // Trap Level
< uint8_t pil; // Process Interrupt Register
< uint8_t cwp; // Current Window Pointer
< //uint8_t cansave; // Savable windows
< //uint8_t canrestore; // Restorable windows
< //uint8_t cleanwin; // Clean windows
< //uint8_t otherwin; // Other windows
< //uint8_t wstate; // Window State
< uint8_t gl; // Global level register
---
> uint16_t pstate; // Process State Register
> uint8_t tl; // Trap Level
> uint8_t pil; // Process Interrupt Register
> uint8_t cwp; // Current Window Pointer
> // uint8_t cansave; // Savable windows
> // uint8_t canrestore; // Restorable windows
> // uint8_t cleanwin; // Clean windows
> // uint8_t otherwin; // Other windows
> // uint8_t wstate; // Window State
> uint8_t gl; // Global level register
86,91c86,91
< /** Hyperprivileged Registers */
< uint64_t hpstate; // Hyperprivileged State Register
< uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
< uint64_t hintp;
< uint64_t htba; // Hyperprivileged Trap Base Address register
< uint64_t hstick_cmpr; // Hardware tick compare registers
---
> /** Hyperprivileged Registers */
> uint64_t hpstate; // Hyperprivileged State Register
> uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
> uint64_t hintp;
> uint64_t htba; // Hyperprivileged Trap Base Address register
> uint64_t hstick_cmpr; // Hardware tick compare registers
93c93
< uint64_t strandStatusReg;// Per strand status register
---
> uint64_t strandStatusReg;// Per strand status register
95,96c95,96
< /** Floating point misc registers. */
< uint64_t fsr; // Floating-Point State Register
---
> /** Floating point misc registers. */
> uint64_t fsr; // Floating-Point State Register
98,102c98,102
< /** MMU Internal Registers */
< uint16_t priContext;
< uint16_t secContext;
< uint16_t partId;
< uint64_t lsuCtrlReg;
---
> /** MMU Internal Registers */
> uint16_t priContext;
> uint16_t secContext;
> uint16_t partId;
> uint64_t lsuCtrlReg;
104c104
< uint64_t scratchPad[8];
---
> uint64_t scratchPad[8];
106,113c106,113
< uint64_t cpu_mondo_head;
< uint64_t cpu_mondo_tail;
< uint64_t dev_mondo_head;
< uint64_t dev_mondo_tail;
< uint64_t res_error_head;
< uint64_t res_error_tail;
< uint64_t nres_error_head;
< uint64_t nres_error_tail;
---
> uint64_t cpu_mondo_head;
> uint64_t cpu_mondo_tail;
> uint64_t dev_mondo_head;
> uint64_t dev_mondo_tail;
> uint64_t res_error_head;
> uint64_t res_error_tail;
> uint64_t nres_error_head;
> uint64_t nres_error_tail;
115,116c115,116
< // These need to check the int_dis field and if 0 then
< // set appropriate bit in softint and checkinterrutps on the cpu
---
> // These need to check the int_dis field and if 0 then
> // set appropriate bit in softint and checkinterrutps on the cpu
118,119c118,119
< void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
< MiscReg readFSReg(int miscReg, ThreadContext * tc);
---
> void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
> MiscReg readFSReg(int miscReg, ThreadContext * tc);
121,122c121,122
< // Update interrupt state on softint or pil change
< void checkSoftInt(ThreadContext *tc);
---
> // Update interrupt state on softint or pil change
> void checkSoftInt(ThreadContext *tc);
124,128c124,128
< /** Process a tick compare event and generate an interrupt on the cpu if
< * appropriate. */
< void processTickCompare(ThreadContext *tc);
< void processSTickCompare(ThreadContext *tc);
< void processHSTickCompare(ThreadContext *tc);
---
> /** Process a tick compare event and generate an interrupt on the cpu if
> * appropriate. */
> void processTickCompare(ThreadContext *tc);
> void processSTickCompare(ThreadContext *tc);
> void processHSTickCompare(ThreadContext *tc);
130,132c130,132
< typedef CpuEventWrapper<ISA,
< &ISA::processTickCompare> TickCompareEvent;
< TickCompareEvent *tickCompare;
---
> typedef CpuEventWrapper<ISA,
> &ISA::processTickCompare> TickCompareEvent;
> TickCompareEvent *tickCompare;
134,136c134,136
< typedef CpuEventWrapper<ISA,
< &ISA::processSTickCompare> STickCompareEvent;
< STickCompareEvent *sTickCompare;
---
> typedef CpuEventWrapper<ISA,
> &ISA::processSTickCompare> STickCompareEvent;
> STickCompareEvent *sTickCompare;
138,140c138,140
< typedef CpuEventWrapper<ISA,
< &ISA::processHSTickCompare> HSTickCompareEvent;
< HSTickCompareEvent *hSTickCompare;
---
> typedef CpuEventWrapper<ISA,
> &ISA::processHSTickCompare> HSTickCompareEvent;
> HSTickCompareEvent *hSTickCompare;
143,145c143,145
< static const int NumGlobalRegs = 8;
< static const int NumWindowedRegs = 24;
< static const int WindowOverlap = 8;
---
> static const int NumGlobalRegs = 8;
> static const int NumWindowedRegs = 24;
> static const int WindowOverlap = 8;
147,149c147,149
< static const int TotalGlobals = (MaxGL + 1) * NumGlobalRegs;
< static const int RegsPerWindow = NumWindowedRegs - WindowOverlap;
< static const int TotalWindowed = NWindows * RegsPerWindow;
---
> static const int TotalGlobals = (MaxGL + 1) * NumGlobalRegs;
> static const int RegsPerWindow = NumWindowedRegs - WindowOverlap;
> static const int TotalWindowed = NWindows * RegsPerWindow;
151,160c151,160
< enum InstIntRegOffsets {
< CurrentGlobalsOffset = 0,
< CurrentWindowOffset = CurrentGlobalsOffset + NumGlobalRegs,
< MicroIntOffset = CurrentWindowOffset + NumWindowedRegs,
< NextGlobalsOffset = MicroIntOffset + NumMicroIntRegs,
< NextWindowOffset = NextGlobalsOffset + NumGlobalRegs,
< PreviousGlobalsOffset = NextWindowOffset + NumWindowedRegs,
< PreviousWindowOffset = PreviousGlobalsOffset + NumGlobalRegs,
< TotalInstIntRegs = PreviousWindowOffset + NumWindowedRegs
< };
---
> enum InstIntRegOffsets {
> CurrentGlobalsOffset = 0,
> CurrentWindowOffset = CurrentGlobalsOffset + NumGlobalRegs,
> MicroIntOffset = CurrentWindowOffset + NumWindowedRegs,
> NextGlobalsOffset = MicroIntOffset + NumMicroIntRegs,
> NextWindowOffset = NextGlobalsOffset + NumGlobalRegs,
> PreviousGlobalsOffset = NextWindowOffset + NumWindowedRegs,
> PreviousWindowOffset = PreviousGlobalsOffset + NumGlobalRegs,
> TotalInstIntRegs = PreviousWindowOffset + NumWindowedRegs
> };
162,165c162,165
< RegIndex intRegMap[TotalInstIntRegs];
< void installWindow(int cwp, int offset);
< void installGlobals(int gl, int offset);
< void reloadRegMap();
---
> RegIndex intRegMap[TotalInstIntRegs];
> void installWindow(int cwp, int offset);
> void installGlobals(int gl, int offset);
> void reloadRegMap();
167c167
< public:
---
> public:
169c169
< void clear();
---
> void clear();
171c171
< void serialize(EventManager *em, std::ostream & os);
---
> void serialize(EventManager *em, std::ostream & os);
173,174c173,174
< void unserialize(EventManager *em, Checkpoint *cp,
< const std::string & section);
---
> void unserialize(EventManager *em, Checkpoint *cp,
> const std::string & section);
176c176
< protected:
---
> protected:
178,180c178,180
< bool isHyperPriv() { return (hpstate & (1 << 2)); }
< bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); }
< bool isNonPriv() { return !isPriv(); }
---
> bool isHyperPriv() { return (hpstate & (1 << 2)); }
> bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); }
> bool isNonPriv() { return !isPriv(); }
182c182
< public:
---
> public:
184,185c184,185
< MiscReg readMiscRegNoEffect(int miscReg);
< MiscReg readMiscReg(int miscReg, ThreadContext *tc);
---
> MiscReg readMiscRegNoEffect(int miscReg);
> MiscReg readMiscReg(int miscReg, ThreadContext *tc);
187,189c187,189
< void setMiscRegNoEffect(int miscReg, const MiscReg val);
< void setMiscReg(int miscReg, const MiscReg val,
< ThreadContext *tc);
---
> void setMiscRegNoEffect(int miscReg, const MiscReg val);
> void setMiscReg(int miscReg, const MiscReg val,
> ThreadContext *tc);
191,198c191,198
< int
< flattenIntIndex(int reg)
< {
< assert(reg < TotalInstIntRegs);
< RegIndex flatIndex = intRegMap[reg];
< assert(flatIndex < NumIntRegs);
< return flatIndex;
< }
---
> int
> flattenIntIndex(int reg)
> {
> assert(reg < TotalInstIntRegs);
> RegIndex flatIndex = intRegMap[reg];
> assert(flatIndex < NumIntRegs);
> return flatIndex;
> }
200,204c200,204
< int
< flattenFloatIndex(int reg)
< {
< return reg;
< }
---
> int
> flattenFloatIndex(int reg)
> {
> return reg;
> }
206,207c206,207
< ISA()
< {
---
> ISA()
> {
209,211c209,211
< tickCompare = NULL;
< sTickCompare = NULL;
< hSTickCompare = NULL;
---
> tickCompare = NULL;
> sTickCompare = NULL;
> hSTickCompare = NULL;
214,216c214,216
< clear();
< }
< };
---
> clear();
> }
> };