1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#ifndef __ARCH_SPARC_ISA_HH__ 32#define __ARCH_SPARC_ISA_HH__ 33 34#include <ostream> 35#include <string> 36 37#include "arch/sparc/registers.hh" 38#include "arch/sparc/types.hh" 39#include "cpu/cpuevent.hh"
| 1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#ifndef __ARCH_SPARC_ISA_HH__ 32#define __ARCH_SPARC_ISA_HH__ 33 34#include <ostream> 35#include <string> 36 37#include "arch/sparc/registers.hh" 38#include "arch/sparc/types.hh" 39#include "cpu/cpuevent.hh"
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| 40#include "cpu/reg_class.hh"
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40#include "sim/sim_object.hh" 41 42class Checkpoint; 43class EventManager; 44struct SparcISAParams; 45class ThreadContext; 46 47namespace SparcISA 48{ 49class ISA : public SimObject 50{ 51 private: 52 53 /* ASR Registers */ 54 // uint64_t y; // Y (used in obsolete multiplication) 55 // uint8_t ccr; // Condition Code Register 56 uint8_t asi; // Address Space Identifier 57 uint64_t tick; // Hardware clock-tick counter 58 uint8_t fprs; // Floating-Point Register State 59 uint64_t gsr; // General Status Register 60 uint64_t softint; 61 uint64_t tick_cmpr; // Hardware tick compare registers 62 uint64_t stick; // Hardware clock-tick counter 63 uint64_t stick_cmpr; // Hardware tick compare registers 64 65 66 /* Privileged Registers */ 67 uint64_t tpc[MaxTL]; // Trap Program Counter (value from 68 // previous trap level) 69 uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from 70 // previous trap level) 71 uint64_t tstate[MaxTL]; // Trap State 72 uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured 73 // on the previous level) 74 uint64_t tba; // Trap Base Address 75 76 PSTATE pstate; // Process State Register 77 uint8_t tl; // Trap Level 78 uint8_t pil; // Process Interrupt Register 79 uint8_t cwp; // Current Window Pointer 80 // uint8_t cansave; // Savable windows 81 // uint8_t canrestore; // Restorable windows 82 // uint8_t cleanwin; // Clean windows 83 // uint8_t otherwin; // Other windows 84 // uint8_t wstate; // Window State 85 uint8_t gl; // Global level register 86 87 /** Hyperprivileged Registers */ 88 HPSTATE hpstate; // Hyperprivileged State Register 89 uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register 90 uint64_t hintp; 91 uint64_t htba; // Hyperprivileged Trap Base Address register 92 uint64_t hstick_cmpr; // Hardware tick compare registers 93 94 uint64_t strandStatusReg;// Per strand status register 95 96 /** Floating point misc registers. */ 97 uint64_t fsr; // Floating-Point State Register 98 99 /** MMU Internal Registers */ 100 uint16_t priContext; 101 uint16_t secContext; 102 uint16_t partId; 103 uint64_t lsuCtrlReg; 104 105 uint64_t scratchPad[8]; 106 107 uint64_t cpu_mondo_head; 108 uint64_t cpu_mondo_tail; 109 uint64_t dev_mondo_head; 110 uint64_t dev_mondo_tail; 111 uint64_t res_error_head; 112 uint64_t res_error_tail; 113 uint64_t nres_error_head; 114 uint64_t nres_error_tail; 115 116 // These need to check the int_dis field and if 0 then 117 // set appropriate bit in softint and checkinterrutps on the cpu 118 void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc); 119 MiscReg readFSReg(int miscReg, ThreadContext * tc); 120 121 // Update interrupt state on softint or pil change 122 void checkSoftInt(ThreadContext *tc); 123 124 /** Process a tick compare event and generate an interrupt on the cpu if 125 * appropriate. */ 126 void processTickCompare(ThreadContext *tc); 127 void processSTickCompare(ThreadContext *tc); 128 void processHSTickCompare(ThreadContext *tc); 129 130 typedef CpuEventWrapper<ISA, 131 &ISA::processTickCompare> TickCompareEvent; 132 TickCompareEvent *tickCompare; 133 134 typedef CpuEventWrapper<ISA, 135 &ISA::processSTickCompare> STickCompareEvent; 136 STickCompareEvent *sTickCompare; 137 138 typedef CpuEventWrapper<ISA, 139 &ISA::processHSTickCompare> HSTickCompareEvent; 140 HSTickCompareEvent *hSTickCompare; 141 142 static const int NumGlobalRegs = 8; 143 static const int NumWindowedRegs = 24; 144 static const int WindowOverlap = 8; 145 146 static const int TotalGlobals = (MaxGL + 1) * NumGlobalRegs; 147 static const int RegsPerWindow = NumWindowedRegs - WindowOverlap; 148 static const int TotalWindowed = NWindows * RegsPerWindow; 149 150 enum InstIntRegOffsets { 151 CurrentGlobalsOffset = 0, 152 CurrentWindowOffset = CurrentGlobalsOffset + NumGlobalRegs, 153 MicroIntOffset = CurrentWindowOffset + NumWindowedRegs, 154 NextGlobalsOffset = MicroIntOffset + NumMicroIntRegs, 155 NextWindowOffset = NextGlobalsOffset + NumGlobalRegs, 156 PreviousGlobalsOffset = NextWindowOffset + NumWindowedRegs, 157 PreviousWindowOffset = PreviousGlobalsOffset + NumGlobalRegs, 158 TotalInstIntRegs = PreviousWindowOffset + NumWindowedRegs 159 }; 160 161 RegIndex intRegMap[TotalInstIntRegs]; 162 void installWindow(int cwp, int offset); 163 void installGlobals(int gl, int offset); 164 void reloadRegMap(); 165 166 public: 167 168 void clear(); 169 170 void serialize(CheckpointOut &cp) const override; 171 void unserialize(CheckpointIn &cp) override; 172 173 void startup(ThreadContext *tc) {} 174 175 /// Explicitly import the otherwise hidden startup 176 using SimObject::startup; 177 178 protected: 179 bool isHyperPriv() { return hpstate.hpriv; } 180 bool isPriv() { return hpstate.hpriv || pstate.priv; } 181 bool isNonPriv() { return !isPriv(); } 182 183 public: 184 185 MiscReg readMiscRegNoEffect(int miscReg) const; 186 MiscReg readMiscReg(int miscReg, ThreadContext *tc); 187 188 void setMiscRegNoEffect(int miscReg, const MiscReg val); 189 void setMiscReg(int miscReg, const MiscReg val, 190 ThreadContext *tc); 191
| 41#include "sim/sim_object.hh" 42 43class Checkpoint; 44class EventManager; 45struct SparcISAParams; 46class ThreadContext; 47 48namespace SparcISA 49{ 50class ISA : public SimObject 51{ 52 private: 53 54 /* ASR Registers */ 55 // uint64_t y; // Y (used in obsolete multiplication) 56 // uint8_t ccr; // Condition Code Register 57 uint8_t asi; // Address Space Identifier 58 uint64_t tick; // Hardware clock-tick counter 59 uint8_t fprs; // Floating-Point Register State 60 uint64_t gsr; // General Status Register 61 uint64_t softint; 62 uint64_t tick_cmpr; // Hardware tick compare registers 63 uint64_t stick; // Hardware clock-tick counter 64 uint64_t stick_cmpr; // Hardware tick compare registers 65 66 67 /* Privileged Registers */ 68 uint64_t tpc[MaxTL]; // Trap Program Counter (value from 69 // previous trap level) 70 uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from 71 // previous trap level) 72 uint64_t tstate[MaxTL]; // Trap State 73 uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured 74 // on the previous level) 75 uint64_t tba; // Trap Base Address 76 77 PSTATE pstate; // Process State Register 78 uint8_t tl; // Trap Level 79 uint8_t pil; // Process Interrupt Register 80 uint8_t cwp; // Current Window Pointer 81 // uint8_t cansave; // Savable windows 82 // uint8_t canrestore; // Restorable windows 83 // uint8_t cleanwin; // Clean windows 84 // uint8_t otherwin; // Other windows 85 // uint8_t wstate; // Window State 86 uint8_t gl; // Global level register 87 88 /** Hyperprivileged Registers */ 89 HPSTATE hpstate; // Hyperprivileged State Register 90 uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register 91 uint64_t hintp; 92 uint64_t htba; // Hyperprivileged Trap Base Address register 93 uint64_t hstick_cmpr; // Hardware tick compare registers 94 95 uint64_t strandStatusReg;// Per strand status register 96 97 /** Floating point misc registers. */ 98 uint64_t fsr; // Floating-Point State Register 99 100 /** MMU Internal Registers */ 101 uint16_t priContext; 102 uint16_t secContext; 103 uint16_t partId; 104 uint64_t lsuCtrlReg; 105 106 uint64_t scratchPad[8]; 107 108 uint64_t cpu_mondo_head; 109 uint64_t cpu_mondo_tail; 110 uint64_t dev_mondo_head; 111 uint64_t dev_mondo_tail; 112 uint64_t res_error_head; 113 uint64_t res_error_tail; 114 uint64_t nres_error_head; 115 uint64_t nres_error_tail; 116 117 // These need to check the int_dis field and if 0 then 118 // set appropriate bit in softint and checkinterrutps on the cpu 119 void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc); 120 MiscReg readFSReg(int miscReg, ThreadContext * tc); 121 122 // Update interrupt state on softint or pil change 123 void checkSoftInt(ThreadContext *tc); 124 125 /** Process a tick compare event and generate an interrupt on the cpu if 126 * appropriate. */ 127 void processTickCompare(ThreadContext *tc); 128 void processSTickCompare(ThreadContext *tc); 129 void processHSTickCompare(ThreadContext *tc); 130 131 typedef CpuEventWrapper<ISA, 132 &ISA::processTickCompare> TickCompareEvent; 133 TickCompareEvent *tickCompare; 134 135 typedef CpuEventWrapper<ISA, 136 &ISA::processSTickCompare> STickCompareEvent; 137 STickCompareEvent *sTickCompare; 138 139 typedef CpuEventWrapper<ISA, 140 &ISA::processHSTickCompare> HSTickCompareEvent; 141 HSTickCompareEvent *hSTickCompare; 142 143 static const int NumGlobalRegs = 8; 144 static const int NumWindowedRegs = 24; 145 static const int WindowOverlap = 8; 146 147 static const int TotalGlobals = (MaxGL + 1) * NumGlobalRegs; 148 static const int RegsPerWindow = NumWindowedRegs - WindowOverlap; 149 static const int TotalWindowed = NWindows * RegsPerWindow; 150 151 enum InstIntRegOffsets { 152 CurrentGlobalsOffset = 0, 153 CurrentWindowOffset = CurrentGlobalsOffset + NumGlobalRegs, 154 MicroIntOffset = CurrentWindowOffset + NumWindowedRegs, 155 NextGlobalsOffset = MicroIntOffset + NumMicroIntRegs, 156 NextWindowOffset = NextGlobalsOffset + NumGlobalRegs, 157 PreviousGlobalsOffset = NextWindowOffset + NumWindowedRegs, 158 PreviousWindowOffset = PreviousGlobalsOffset + NumGlobalRegs, 159 TotalInstIntRegs = PreviousWindowOffset + NumWindowedRegs 160 }; 161 162 RegIndex intRegMap[TotalInstIntRegs]; 163 void installWindow(int cwp, int offset); 164 void installGlobals(int gl, int offset); 165 void reloadRegMap(); 166 167 public: 168 169 void clear(); 170 171 void serialize(CheckpointOut &cp) const override; 172 void unserialize(CheckpointIn &cp) override; 173 174 void startup(ThreadContext *tc) {} 175 176 /// Explicitly import the otherwise hidden startup 177 using SimObject::startup; 178 179 protected: 180 bool isHyperPriv() { return hpstate.hpriv; } 181 bool isPriv() { return hpstate.hpriv || pstate.priv; } 182 bool isNonPriv() { return !isPriv(); } 183 184 public: 185 186 MiscReg readMiscRegNoEffect(int miscReg) const; 187 MiscReg readMiscReg(int miscReg, ThreadContext *tc); 188 189 void setMiscRegNoEffect(int miscReg, const MiscReg val); 190 void setMiscReg(int miscReg, const MiscReg val, 191 ThreadContext *tc); 192
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| 193 RegId 194 flattenRegId(const RegId& regId) const 195 { 196 switch (regId.classValue()) { 197 case IntRegClass: 198 return RegId(IntRegClass, flattenIntIndex(regId.index())); 199 case FloatRegClass: 200 return RegId(FloatRegClass, flattenFloatIndex(regId.index())); 201 case CCRegClass: 202 return RegId(CCRegClass, flattenCCIndex(regId.index())); 203 case MiscRegClass: 204 return RegId(MiscRegClass, flattenMiscIndex(regId.index())); 205 } 206 return regId; 207 } 208
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192 int 193 flattenIntIndex(int reg) const 194 { 195 assert(reg < TotalInstIntRegs); 196 RegIndex flatIndex = intRegMap[reg]; 197 assert(flatIndex < NumIntRegs); 198 return flatIndex; 199 } 200 201 int 202 flattenFloatIndex(int reg) const 203 { 204 return reg; 205 } 206 207 // dummy 208 int 209 flattenCCIndex(int reg) const 210 { 211 return reg; 212 } 213 214 int 215 flattenMiscIndex(int reg) const 216 { 217 return reg; 218 } 219 220 221 typedef SparcISAParams Params; 222 const Params *params() const; 223 224 ISA(Params *p); 225}; 226} 227 228#endif
| 209 int 210 flattenIntIndex(int reg) const 211 { 212 assert(reg < TotalInstIntRegs); 213 RegIndex flatIndex = intRegMap[reg]; 214 assert(flatIndex < NumIntRegs); 215 return flatIndex; 216 } 217 218 int 219 flattenFloatIndex(int reg) const 220 { 221 return reg; 222 } 223 224 // dummy 225 int 226 flattenCCIndex(int reg) const 227 { 228 return reg; 229 } 230 231 int 232 flattenMiscIndex(int reg) const 233 { 234 return reg; 235 } 236 237 238 typedef SparcISAParams Params; 239 const Params *params() const; 240 241 ISA(Params *p); 242}; 243} 244 245#endif
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