1/*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_ISA_HH__
32#define __ARCH_SPARC_ISA_HH__
33
34#include <ostream>
35#include <string>
36
37#include "arch/sparc/registers.hh"
38#include "arch/sparc/types.hh"
39#include "cpu/cpuevent.hh"
40
41class Checkpoint;
42class EventManager;
43class ThreadContext;
44
45namespace SparcISA
46{
47class ISA
48{
49 private:
50
51 /* ASR Registers */
52 // uint64_t y; // Y (used in obsolete multiplication)
53 // uint8_t ccr; // Condition Code Register
54 uint8_t asi; // Address Space Identifier
55 uint64_t tick; // Hardware clock-tick counter
56 uint8_t fprs; // Floating-Point Register State
57 uint64_t gsr; // General Status Register
58 uint64_t softint;
59 uint64_t tick_cmpr; // Hardware tick compare registers
60 uint64_t stick; // Hardware clock-tick counter
61 uint64_t stick_cmpr; // Hardware tick compare registers
62
63
64 /* Privileged Registers */
65 uint64_t tpc[MaxTL]; // Trap Program Counter (value from
66 // previous trap level)
67 uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
68 // previous trap level)
69 uint64_t tstate[MaxTL]; // Trap State
70 uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
71 // on the previous level)
72 uint64_t tba; // Trap Base Address
73
74 PSTATE pstate; // Process State Register
75 uint8_t tl; // Trap Level
76 uint8_t pil; // Process Interrupt Register
77 uint8_t cwp; // Current Window Pointer
78 // uint8_t cansave; // Savable windows
79 // uint8_t canrestore; // Restorable windows
80 // uint8_t cleanwin; // Clean windows
81 // uint8_t otherwin; // Other windows
82 // uint8_t wstate; // Window State
83 uint8_t gl; // Global level register
84
85 /** Hyperprivileged Registers */
86 HPSTATE hpstate; // Hyperprivileged State Register
87 uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
88 uint64_t hintp;
89 uint64_t htba; // Hyperprivileged Trap Base Address register
90 uint64_t hstick_cmpr; // Hardware tick compare registers
91
92 uint64_t strandStatusReg;// Per strand status register
93
94 /** Floating point misc registers. */
95 uint64_t fsr; // Floating-Point State Register
96
97 /** MMU Internal Registers */
98 uint16_t priContext;
99 uint16_t secContext;
100 uint16_t partId;
101 uint64_t lsuCtrlReg;
102
103 uint64_t scratchPad[8];
104
105 uint64_t cpu_mondo_head;
106 uint64_t cpu_mondo_tail;
107 uint64_t dev_mondo_head;
108 uint64_t dev_mondo_tail;
109 uint64_t res_error_head;
110 uint64_t res_error_tail;
111 uint64_t nres_error_head;
112 uint64_t nres_error_tail;
113
114 // These need to check the int_dis field and if 0 then
115 // set appropriate bit in softint and checkinterrutps on the cpu
116 void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
117 MiscReg readFSReg(int miscReg, ThreadContext * tc);
118
119 // Update interrupt state on softint or pil change
120 void checkSoftInt(ThreadContext *tc);
121
122 /** Process a tick compare event and generate an interrupt on the cpu if
123 * appropriate. */
124 void processTickCompare(ThreadContext *tc);
125 void processSTickCompare(ThreadContext *tc);
126 void processHSTickCompare(ThreadContext *tc);
127
128 typedef CpuEventWrapper<ISA,
129 &ISA::processTickCompare> TickCompareEvent;
130 TickCompareEvent *tickCompare;
131
132 typedef CpuEventWrapper<ISA,
133 &ISA::processSTickCompare> STickCompareEvent;
134 STickCompareEvent *sTickCompare;
135
136 typedef CpuEventWrapper<ISA,
137 &ISA::processHSTickCompare> HSTickCompareEvent;
138 HSTickCompareEvent *hSTickCompare;
139
140 static const int NumGlobalRegs = 8;
141 static const int NumWindowedRegs = 24;
142 static const int WindowOverlap = 8;
143
144 static const int TotalGlobals = (MaxGL + 1) * NumGlobalRegs;
145 static const int RegsPerWindow = NumWindowedRegs - WindowOverlap;
146 static const int TotalWindowed = NWindows * RegsPerWindow;
147
148 enum InstIntRegOffsets {
149 CurrentGlobalsOffset = 0,
150 CurrentWindowOffset = CurrentGlobalsOffset + NumGlobalRegs,
151 MicroIntOffset = CurrentWindowOffset + NumWindowedRegs,
152 NextGlobalsOffset = MicroIntOffset + NumMicroIntRegs,
153 NextWindowOffset = NextGlobalsOffset + NumGlobalRegs,
154 PreviousGlobalsOffset = NextWindowOffset + NumWindowedRegs,
155 PreviousWindowOffset = PreviousGlobalsOffset + NumGlobalRegs,
156 TotalInstIntRegs = PreviousWindowOffset + NumWindowedRegs
157 };
158
159 RegIndex intRegMap[TotalInstIntRegs];
160 void installWindow(int cwp, int offset);
161 void installGlobals(int gl, int offset);
162 void reloadRegMap();
163
164 public:
165
166 void clear();
167
168 void serialize(EventManager *em, std::ostream & os);
169
170 void unserialize(EventManager *em, Checkpoint *cp,
171 const std::string & section);
172
173 protected:
174
175 bool isHyperPriv() { return hpstate.hpriv; }
176 bool isPriv() { return hpstate.hpriv || pstate.priv; }
177 bool isNonPriv() { return !isPriv(); }
178
179 public:
180
181 MiscReg readMiscRegNoEffect(int miscReg);
182 MiscReg readMiscReg(int miscReg, ThreadContext *tc);
183
184 void setMiscRegNoEffect(int miscReg, const MiscReg val);
185 void setMiscReg(int miscReg, const MiscReg val,
186 ThreadContext *tc);
187
188 int
189 flattenIntIndex(int reg)
190 {
191 assert(reg < TotalInstIntRegs);
192 RegIndex flatIndex = intRegMap[reg];
193 assert(flatIndex < NumIntRegs);
194 return flatIndex;
195 }
196
197 int
198 flattenFloatIndex(int reg)
199 {
200 return reg;
201 }
202
203 ISA()
204 {
205 tickCompare = NULL;
206 sTickCompare = NULL;
207 hSTickCompare = NULL;
208
209 clear();
210 }
211};
212}
213
214#endif
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_ISA_HH__
32#define __ARCH_SPARC_ISA_HH__
33
34#include <ostream>
35#include <string>
36
37#include "arch/sparc/registers.hh"
38#include "arch/sparc/types.hh"
39#include "cpu/cpuevent.hh"
40
41class Checkpoint;
42class EventManager;
43class ThreadContext;
44
45namespace SparcISA
46{
47class ISA
48{
49 private:
50
51 /* ASR Registers */
52 // uint64_t y; // Y (used in obsolete multiplication)
53 // uint8_t ccr; // Condition Code Register
54 uint8_t asi; // Address Space Identifier
55 uint64_t tick; // Hardware clock-tick counter
56 uint8_t fprs; // Floating-Point Register State
57 uint64_t gsr; // General Status Register
58 uint64_t softint;
59 uint64_t tick_cmpr; // Hardware tick compare registers
60 uint64_t stick; // Hardware clock-tick counter
61 uint64_t stick_cmpr; // Hardware tick compare registers
62
63
64 /* Privileged Registers */
65 uint64_t tpc[MaxTL]; // Trap Program Counter (value from
66 // previous trap level)
67 uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
68 // previous trap level)
69 uint64_t tstate[MaxTL]; // Trap State
70 uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
71 // on the previous level)
72 uint64_t tba; // Trap Base Address
73
74 PSTATE pstate; // Process State Register
75 uint8_t tl; // Trap Level
76 uint8_t pil; // Process Interrupt Register
77 uint8_t cwp; // Current Window Pointer
78 // uint8_t cansave; // Savable windows
79 // uint8_t canrestore; // Restorable windows
80 // uint8_t cleanwin; // Clean windows
81 // uint8_t otherwin; // Other windows
82 // uint8_t wstate; // Window State
83 uint8_t gl; // Global level register
84
85 /** Hyperprivileged Registers */
86 HPSTATE hpstate; // Hyperprivileged State Register
87 uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
88 uint64_t hintp;
89 uint64_t htba; // Hyperprivileged Trap Base Address register
90 uint64_t hstick_cmpr; // Hardware tick compare registers
91
92 uint64_t strandStatusReg;// Per strand status register
93
94 /** Floating point misc registers. */
95 uint64_t fsr; // Floating-Point State Register
96
97 /** MMU Internal Registers */
98 uint16_t priContext;
99 uint16_t secContext;
100 uint16_t partId;
101 uint64_t lsuCtrlReg;
102
103 uint64_t scratchPad[8];
104
105 uint64_t cpu_mondo_head;
106 uint64_t cpu_mondo_tail;
107 uint64_t dev_mondo_head;
108 uint64_t dev_mondo_tail;
109 uint64_t res_error_head;
110 uint64_t res_error_tail;
111 uint64_t nres_error_head;
112 uint64_t nres_error_tail;
113
114 // These need to check the int_dis field and if 0 then
115 // set appropriate bit in softint and checkinterrutps on the cpu
116 void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
117 MiscReg readFSReg(int miscReg, ThreadContext * tc);
118
119 // Update interrupt state on softint or pil change
120 void checkSoftInt(ThreadContext *tc);
121
122 /** Process a tick compare event and generate an interrupt on the cpu if
123 * appropriate. */
124 void processTickCompare(ThreadContext *tc);
125 void processSTickCompare(ThreadContext *tc);
126 void processHSTickCompare(ThreadContext *tc);
127
128 typedef CpuEventWrapper<ISA,
129 &ISA::processTickCompare> TickCompareEvent;
130 TickCompareEvent *tickCompare;
131
132 typedef CpuEventWrapper<ISA,
133 &ISA::processSTickCompare> STickCompareEvent;
134 STickCompareEvent *sTickCompare;
135
136 typedef CpuEventWrapper<ISA,
137 &ISA::processHSTickCompare> HSTickCompareEvent;
138 HSTickCompareEvent *hSTickCompare;
139
140 static const int NumGlobalRegs = 8;
141 static const int NumWindowedRegs = 24;
142 static const int WindowOverlap = 8;
143
144 static const int TotalGlobals = (MaxGL + 1) * NumGlobalRegs;
145 static const int RegsPerWindow = NumWindowedRegs - WindowOverlap;
146 static const int TotalWindowed = NWindows * RegsPerWindow;
147
148 enum InstIntRegOffsets {
149 CurrentGlobalsOffset = 0,
150 CurrentWindowOffset = CurrentGlobalsOffset + NumGlobalRegs,
151 MicroIntOffset = CurrentWindowOffset + NumWindowedRegs,
152 NextGlobalsOffset = MicroIntOffset + NumMicroIntRegs,
153 NextWindowOffset = NextGlobalsOffset + NumGlobalRegs,
154 PreviousGlobalsOffset = NextWindowOffset + NumWindowedRegs,
155 PreviousWindowOffset = PreviousGlobalsOffset + NumGlobalRegs,
156 TotalInstIntRegs = PreviousWindowOffset + NumWindowedRegs
157 };
158
159 RegIndex intRegMap[TotalInstIntRegs];
160 void installWindow(int cwp, int offset);
161 void installGlobals(int gl, int offset);
162 void reloadRegMap();
163
164 public:
165
166 void clear();
167
168 void serialize(EventManager *em, std::ostream & os);
169
170 void unserialize(EventManager *em, Checkpoint *cp,
171 const std::string & section);
172
173 protected:
174
175 bool isHyperPriv() { return hpstate.hpriv; }
176 bool isPriv() { return hpstate.hpriv || pstate.priv; }
177 bool isNonPriv() { return !isPriv(); }
178
179 public:
180
181 MiscReg readMiscRegNoEffect(int miscReg);
182 MiscReg readMiscReg(int miscReg, ThreadContext *tc);
183
184 void setMiscRegNoEffect(int miscReg, const MiscReg val);
185 void setMiscReg(int miscReg, const MiscReg val,
186 ThreadContext *tc);
187
188 int
189 flattenIntIndex(int reg)
190 {
191 assert(reg < TotalInstIntRegs);
192 RegIndex flatIndex = intRegMap[reg];
193 assert(flatIndex < NumIntRegs);
194 return flatIndex;
195 }
196
197 int
198 flattenFloatIndex(int reg)
199 {
200 return reg;
201 }
202
203 ISA()
204 {
205 tickCompare = NULL;
206 sTickCompare = NULL;
207 hSTickCompare = NULL;
208
209 clear();
210 }
211};
212}
213
214#endif